rduhr / TP-CN_rduhr_scruchet

Commit f7d9e147a05e9d0cf104a9cb9ee2b3bf863347de

Authored by rduhr
1 parent 025ff1a6

display.vhd

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7Segment_display/display.vhd
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... ... @@ -44,7 +44,7 @@ end display;
44 44  
45 45 architecture Behavioral of display is
46 46  
47   -signal count_int : integer range 3 downto 0 := 0;
  47 +signal count_an : integer range 3 downto 0 := 0;
48 48 signal clk_enable : integer range 4999 downto 0 := 0;
49 49 signal clk_counter : integer range 2999999 downto 0 := 0;
50 50 constant nb0 : std_logic_vector(7 downto 0) := "11000000";
... ... @@ -77,22 +77,22 @@ begin
77 77 -- clock d'affichage
78 78 if clk_enable = 4999 then
79 79 clk_enable <= 0;
80   - if count_int = 0 then
  80 + if count_an = 0 then
81 81 aff <= numbers(chiffre4);
82 82 an <= seg0;
83   - count_int <= count_int + 1;
84   - elsif count_int = 1 then
  83 + count_an <= count_an + 1;
  84 + elsif count_an = 1 then
85 85 aff <= numbers(chiffre3);
86 86 an <= seg1;
87   - count_int <= count_int + 1;
88   - elsif count_int = 2 then
  87 + count_an <= count_an + 1;
  88 + elsif count_an = 2 then
89 89 aff <= numbers(chiffre2);
90 90 an <= seg2;
91   - count_int <= count_int + 1;
92   - elsif count_int = 3 then
  91 + count_an <= count_an + 1;
  92 + elsif count_an = 3 then
93 93 aff <= numbers(chiffre1);
94 94 an <= seg3;
95   - count_int <= 0;
  95 + count_an <= 0;
96 96 end if;
97 97 else
98 98 clk_enable <= clk_enable + 1;
... ... @@ -130,4 +130,4 @@ begin
130 130 end if;
131 131 end if;
132 132 end process;
133 133 -end Behavioral;
  134 +end Behavioral;
134 135 \ No newline at end of file
... ...