rduhr / TP-CN_rduhr_scruchet

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7Segment_display readme

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  1 +----------------------------------------------------------------------------------
  2 +-- Company:
  3 +-- Engineer:
  4 +--
  5 +-- Create Date: 27.09.2023 17:03:49
  6 +-- Design Name:
  7 +-- Module Name: display - Behavioral
  8 +-- Project Name:
  9 +-- Target Devices:
  10 +-- Tool Versions:
  11 +-- Description:
  12 +--
  13 +-- Dependencies:
  14 +--
  15 +-- Revision:
  16 +-- Revision 0.01 - File Created
  17 +-- Additional Comments:
  18 +--
  19 +----------------------------------------------------------------------------------
  20 +
  21 +
  22 +library IEEE;
  23 +use IEEE.STD_LOGIC_1164.ALL;
  24 +use IEEE.STD_LOGIC_ARITH.ALL;
  25 +use IEEE.STD_LOGIC_UNSIGNED.ALL;
  26 +
  27 +-- Uncomment the following library declaration if using
  28 +-- arithmetic functions with Signed or Unsigned values
  29 +--use IEEE.NUMERIC_STD.ALL;
  30 +
  31 +-- Uncomment the following library declaration if instantiating
  32 +-- any Xilinx leaf cells in this code.
  33 +--library UNISIM;
  34 +--use UNISIM.VComponents.all;
  35 +
  36 +entity display is
  37 + port (
  38 + clk_fpga : in STD_LOGIC;
  39 + reset : in STD_LOGIC;
  40 + aff : out STD_LOGIC_VECTOR(7 downto 0);
  41 + an : out STD_LOGIC_VECTOR(3 downto 0)
  42 + );
  43 +end display;
  44 +
  45 +architecture Behavioral of display is
  46 +
  47 +signal count_int : integer range 3 downto 0 := 0;
  48 +signal clk_enable : integer range 4999 downto 0 := 0;
  49 +signal clk_counter : integer range 2999999 downto 0 := 0;
  50 +constant nb0 : std_logic_vector(7 downto 0) := "11000000";
  51 +constant nb1 : std_logic_vector(7 downto 0) := "11111001";
  52 +constant nb2 : std_logic_vector(7 downto 0) := "10100100";
  53 +constant nb3 : std_logic_vector(7 downto 0) := "10110000";
  54 +constant nb4 : std_logic_vector(7 downto 0) := "10011001";
  55 +constant nb5 : std_logic_vector(7 downto 0) := "10010010";
  56 +constant nb6 : std_logic_vector(7 downto 0) := "10000010";
  57 +constant nb7 : std_logic_vector(7 downto 0) := "11111000";
  58 +constant nb8 : std_logic_vector(7 downto 0) := "10000000";
  59 +constant nb9 : std_logic_vector(7 downto 0) := "10010000";
  60 +constant seg0 : std_logic_vector(3 downto 0) := "1110";
  61 +constant seg1 : std_logic_vector(3 downto 0) := "1101";
  62 +constant seg2 : std_logic_vector(3 downto 0) := "1011";
  63 +constant seg3 : std_logic_vector(3 downto 0) := "0111";
  64 +signal chiffre4 : integer range 9 downto 0 := 0;
  65 +signal chiffre3 : integer range 9 downto 0 := 0;
  66 +signal chiffre2 : integer range 9 downto 0 := 0;
  67 +signal chiffre1 : integer range 9 downto 0 := 0;
  68 +
  69 +type mynumbers is array(9 downto 0) of std_logic_vector(7 downto 0);
  70 +signal numbers : mynumbers := (nb9,nb8,nb7,nb6,nb5,nb4,nb3,nb2,nb1,nb0);
  71 +
  72 +begin
  73 +
  74 +process(clk_fpga)
  75 +begin
  76 + if clk_fpga'event and clk_fpga = '1' then
  77 + -- clock d'affichage
  78 + if clk_enable = 4999 then
  79 + clk_enable <= 0;
  80 + if count_int = 0 then
  81 + aff <= numbers(chiffre4);
  82 + an <= seg0;
  83 + count_int <= count_int + 1;
  84 + elsif count_int = 1 then
  85 + aff <= numbers(chiffre3);
  86 + an <= seg1;
  87 + count_int <= count_int + 1;
  88 + elsif count_int = 2 then
  89 + aff <= numbers(chiffre2);
  90 + an <= seg2;
  91 + count_int <= count_int + 1;
  92 + elsif count_int = 3 then
  93 + aff <= numbers(chiffre1);
  94 + an <= seg3;
  95 + count_int <= 0;
  96 + end if;
  97 + else
  98 + clk_enable <= clk_enable + 1;
  99 + end if;
  100 + -- clock de compteur
  101 + if clk_counter = 2999999 then
  102 + clk_counter <= 0;
  103 + if reset = '1' then
  104 + chiffre1 <= 0;
  105 + chiffre2 <= 0;
  106 + chiffre3 <= 0;
  107 + chiffre4 <= 0;
  108 + else if chiffre4 = 9 then
  109 + chiffre4 <= 0;
  110 + if chiffre3 = 9 then
  111 + chiffre3 <= 0;
  112 + if chiffre2 = 9 then
  113 + chiffre2 <= 0;
  114 + if chiffre1 = 9 then
  115 + chiffre1 <= 0;
  116 + else
  117 + chiffre1 <= chiffre1 + 1;
  118 + end if;
  119 + else
  120 + chiffre2 <= chiffre2 + 1;
  121 + end if;
  122 + else
  123 + chiffre3 <= chiffre3 + 1;
  124 + end if;
  125 + else
  126 + chiffre4 <= chiffre4 + 1;
  127 + end if;
  128 + else
  129 + clk_counter <= clk_counter + 1;
  130 + end if;
  131 + end if;
  132 +end process;
  133 +end Behavioral;
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