From f7d9e147a05e9d0cf104a9cb9ee2b3bf863347de Mon Sep 17 00:00:00 2001 From: rduhr Date: Tue, 31 Oct 2023 14:29:33 +0100 Subject: [PATCH] display.vhd --- 7Segment_display/display.vhd | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/7Segment_display/display.vhd b/7Segment_display/display.vhd index ab3e5c8..900e87b 100755 --- a/7Segment_display/display.vhd +++ b/7Segment_display/display.vhd @@ -44,7 +44,7 @@ end display; architecture Behavioral of display is -signal count_int : integer range 3 downto 0 := 0; +signal count_an : integer range 3 downto 0 := 0; signal clk_enable : integer range 4999 downto 0 := 0; signal clk_counter : integer range 2999999 downto 0 := 0; constant nb0 : std_logic_vector(7 downto 0) := "11000000"; @@ -77,22 +77,22 @@ begin -- clock d'affichage if clk_enable = 4999 then clk_enable <= 0; - if count_int = 0 then + if count_an = 0 then aff <= numbers(chiffre4); an <= seg0; - count_int <= count_int + 1; - elsif count_int = 1 then + count_an <= count_an + 1; + elsif count_an = 1 then aff <= numbers(chiffre3); an <= seg1; - count_int <= count_int + 1; - elsif count_int = 2 then + count_an <= count_an + 1; + elsif count_an = 2 then aff <= numbers(chiffre2); an <= seg2; - count_int <= count_int + 1; - elsif count_int = 3 then + count_an <= count_an + 1; + elsif count_an = 3 then aff <= numbers(chiffre1); an <= seg3; - count_int <= 0; + count_an <= 0; end if; else clk_enable <= clk_enable + 1; @@ -130,4 +130,4 @@ begin end if; end if; end process; -end Behavioral; +end Behavioral; \ No newline at end of file -- libgit2 0.21.2