bilalelhasnaoui / Travaux_pratiques_VHDL

Commit 231d00d3387b94551d4d93e69e45358d322bcea0

Authored by bilalelhasnaoui
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Les deux application 7segment et VGA control avec Basys3 FPGA

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Afficheur_7SEG/Afficheur_7SEG.cache/wt/gui_handlers.wdf 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.cache/wt/gui_handlers.wdf
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Afficheur_7SEG/Afficheur_7SEG.cache/wt/java_command_handlers.wdf 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.cache/wt/java_command_handlers.wdf
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Afficheur_7SEG/Afficheur_7SEG.cache/wt/project.wpc 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.cache/wt/project.wpc
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Afficheur_7SEG/Afficheur_7SEG.cache/wt/synthesis.wdf 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.cache/wt/synthesis.wdf
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Afficheur_7SEG/Afficheur_7SEG.cache/wt/synthesis_details.wdf 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.cache/wt/synthesis_details.wdf
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Afficheur_7SEG/Afficheur_7SEG.cache/wt/webtalk_pa.xml 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.cache/wt/webtalk_pa.xml
@@ -0,0 +1,81 @@ @@ -0,0 +1,81 @@
  1 +<?xml version="1.0" encoding="UTF-8" ?>
  2 +<document>
  3 +<!--The data in this file is primarily intended for consumption by Xilinx tools.
  4 +The structure and the elements are likely to change over the next few releases.
  5 +This means code written to parse this file will need to be revisited each subsequent release.-->
  6 +<application name="pa" timeStamp="Wed Oct 4 16:06:50 2023">
  7 +<section name="Project Information" visible="false">
  8 +<property name="ProjectID" value="2cf8949bbe7e4f6390d47f0056d5f60e" type="ProjectID"/>
  9 +<property name="ProjectIteration" value="14" type="ProjectIteration"/>
  10 +</section>
  11 +<section name="PlanAhead Usage" visible="true">
  12 +<item name="Project Data">
  13 +<property name="SrcSetCount" value="1" type="SrcSetCount"/>
  14 +<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
  15 +<property name="DesignMode" value="RTL" type="DesignMode"/>
  16 +<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
  17 +<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
  18 +</item>
  19 +<item name="Java Command Handlers">
  20 +<property name="AddSources" value="1" type="JavaHandler"/>
  21 +<property name="AutoConnectTarget" value="1" type="JavaHandler"/>
  22 +<property name="LaunchProgramFpga" value="2" type="JavaHandler"/>
  23 +<property name="NewProject" value="1" type="JavaHandler"/>
  24 +<property name="OpenHardwareManager" value="1" type="JavaHandler"/>
  25 +<property name="OpenProject" value="2" type="JavaHandler"/>
  26 +<property name="OpenRecentTarget" value="1" type="JavaHandler"/>
  27 +<property name="RunBitgen" value="8" type="JavaHandler"/>
  28 +<property name="RunImplementation" value="5" type="JavaHandler"/>
  29 +<property name="RunSchematic" value="2" type="JavaHandler"/>
  30 +<property name="RunSynthesis" value="7" type="JavaHandler"/>
  31 +<property name="ShowView" value="3" type="JavaHandler"/>
  32 +</item>
  33 +<item name="Gui Handlers">
  34 +<property name="AddSrcWizard_SPECIFY_HDL_NETLIST_BLOCK_DESIGN" value="1" type="GuiHandlerData"/>
  35 +<property name="BaseDialog_CANCEL" value="1" type="GuiHandlerData"/>
  36 +<property name="BaseDialog_OK" value="13" type="GuiHandlerData"/>
  37 +<property name="BaseDialog_YES" value="3" type="GuiHandlerData"/>
  38 +<property name="BoardChooser_BOARD_TABLE" value="2" type="GuiHandlerData"/>
  39 +<property name="CreateSrcFileDialog_FILE_NAME" value="1" type="GuiHandlerData"/>
  40 +<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="8" type="GuiHandlerData"/>
  41 +<property name="FilterToolBar_HIDE_ALL" value="1" type="GuiHandlerData"/>
  42 +<property name="FilterToolBar_SHOW_ALL" value="2" type="GuiHandlerData"/>
  43 +<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="17" type="GuiHandlerData"/>
  44 +<property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
  45 +<property name="LaunchPanel_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/>
  46 +<property name="LogMonitor_MONITOR" value="12" type="GuiHandlerData"/>
  47 +<property name="MainMenuMgr_EDIT" value="2" type="GuiHandlerData"/>
  48 +<property name="MainMenuMgr_FILE" value="6" type="GuiHandlerData"/>
  49 +<property name="MainMenuMgr_PROJECT" value="3" type="GuiHandlerData"/>
  50 +<property name="MainToolbarMgr_RUN" value="9" type="GuiHandlerData"/>
  51 +<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="6" type="GuiHandlerData"/>
  52 +<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="4" type="GuiHandlerData"/>
  53 +<property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="5" type="GuiHandlerData"/>
  54 +<property name="MsgView_INFORMATION_MESSAGES" value="1" type="GuiHandlerData"/>
  55 +<property name="NumJobsChooser_NUMBER_OF_JOBS" value="1" type="GuiHandlerData"/>
  56 +<property name="PACommandNames_ADD_SOURCES" value="1" type="GuiHandlerData"/>
  57 +<property name="PACommandNames_AUTO_CONNECT_TARGET" value="1" type="GuiHandlerData"/>
  58 +<property name="PACommandNames_NEW_PROJECT" value="1" type="GuiHandlerData"/>
  59 +<property name="PACommandNames_RUN_BITGEN" value="2" type="GuiHandlerData"/>
  60 +<property name="PACommandNames_RUN_IMPLEMENTATION" value="3" type="GuiHandlerData"/>
  61 +<property name="PACommandNames_RUN_SYNTHESIS" value="6" type="GuiHandlerData"/>
  62 +<property name="PAViews_CODE" value="2" type="GuiHandlerData"/>
  63 +<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiHandlerData"/>
  64 +<property name="PAViews_SCHEMATIC" value="2" type="GuiHandlerData"/>
  65 +<property name="ProgramDebugTab_PROGRAM_DEVICE" value="2" type="GuiHandlerData"/>
  66 +<property name="ProgramFpgaDialog_PROGRAM" value="2" type="GuiHandlerData"/>
  67 +<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="2" type="GuiHandlerData"/>
  68 +<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
  69 +<property name="ProjectTab_RELOAD" value="1" type="GuiHandlerData"/>
  70 +<property name="RDICommands_LINE_COMMENT" value="4" type="GuiHandlerData"/>
  71 +<property name="SaveProjectUtils_SAVE" value="3" type="GuiHandlerData"/>
  72 +<property name="SrcChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
  73 +</item>
  74 +<item name="Other">
  75 +<property name="GuiMode" value="1" type="GuiMode"/>
  76 +<property name="BatchMode" value="0" type="BatchMode"/>
  77 +<property name="TclMode" value="0" type="TclMode"/>
  78 +</item>
  79 +</section>
  80 +</application>
  81 +</document>
Afficheur_7SEG/Afficheur_7SEG.hw/Afficheur_7SEG.lpr 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.hw/Afficheur_7SEG.lpr
@@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
  1 +<?xml version="1.0" encoding="UTF-8"?>
  2 +<!-- Product Version: Vivado v2019.1 (64-bit) -->
  3 +<!-- -->
  4 +<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
  5 +
  6 +<labtools version="1" minor="0">
  7 + <HWSession Dir="hw_1" File="hw.xml"/>
  8 +</labtools>
Afficheur_7SEG/Afficheur_7SEG.hw/hw_1/hw.xml 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.hw/hw_1/hw.xml
@@ -0,0 +1,17 @@ @@ -0,0 +1,17 @@
  1 +<?xml version="1.0" encoding="UTF-8"?>
  2 +<!-- Product Version: Vivado v2019.1 (64-bit) -->
  3 +<!-- -->
  4 +<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
  5 +
  6 +<hwsession version="1" minor="2">
  7 + <device name="xc7a35t_0" gui_info=""/>
  8 + <ObjectList object_type="hw_device" gui_info="">
  9 + <Object name="xc7a35t_0" gui_info="">
  10 + <Properties Property="FULL_PROBES.FILE" value=""/>
  11 + <Properties Property="PROBES.FILE" value=""/>
  12 + <Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/$_project_name_.bit"/>
  13 + <Properties Property="SLR.COUNT" value="1"/>
  14 + </Object>
  15 + </ObjectList>
  16 + <probeset name="hw project" active="false"/>
  17 +</hwsession>
Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/.xsim_webtallk.info 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/.xsim_webtallk.info
@@ -0,0 +1,5 @@ @@ -0,0 +1,5 @@
  1 +1696428411
  2 +0
  3 +2
  4 +0
  5 +58edfc98-0772-4f04-8438-85f24cad8e0d
Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/labtool_webtalk.log 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/labtool_webtalk.log
@@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
  1 +
  2 +****** Webtalk v2019.1 (64-bit)
  3 + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
  4 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
  5 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  6 +
  7 +source C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/labtool_webtalk.tcl -notrace
  8 +INFO: [Common 17-206] Exiting Webtalk at Wed Oct 4 16:06:53 2023...
Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/usage_statistics_ext_labtool.html 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/usage_statistics_ext_labtool.html
@@ -0,0 +1,45 @@ @@ -0,0 +1,45 @@
  1 +<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
  2 +<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>LABTOOL Usage Report</H3><BR>
  3 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  4 + <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
  5 +<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
  6 + <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2552052</TD>
  7 +</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Wed Oct 4 16:06:51 2023</TD>
  8 + <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
  9 +</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2019.1 (64-bit)</TD>
  10 + <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>58edfc98-0772-4f04-8438-85f24cad8e0d</TD>
  11 +</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>1</TD>
  12 + <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>543ca123-eb9d-49cf-8266-de8eac9687e5</TD>
  13 +</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>543ca123-eb9d-49cf-8266-de8eac9687e5</TD>
  14 + <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>FALSE</TD>
  15 +</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>not_applicable</TD>
  16 + <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>not_applicable</TD>
  17 +</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>not_applicable</TD>
  18 + <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>not_applicable</TD>
  19 +</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>labtool</TD>
  20 +</TR> </TABLE><BR>
  21 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  22 + <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
  23 +<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i5-8500 CPU @ 3.00GHz</TD>
  24 + <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>3000 MHz</TD>
  25 +</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Windows Server 2016 or Windows 10</TD>
  26 + <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release (build 9200)</TD>
  27 +</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>12.000 GB</TD>
  28 + <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
  29 +</TR> </TABLE><BR>
  30 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  31 + <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
  32 + </TABLE><BR>
  33 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  34 + <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>labtool</B></TD></TR>
  35 + <TR><TD>
  36 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  37 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
  38 +<TR ALIGN='LEFT'> <TD>cable=Digilent/Basys3/15000000:</TD>
  39 + <TD>chain=0362D093</TD>
  40 + <TD>pgmcnt=02:00:00</TD>
  41 +</TR> </TABLE>
  42 + </TD></TR>
  43 + </TABLE><BR>
  44 +</BODY>
  45 +</HTML>
Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/usage_statistics_ext_labtool.xml 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/usage_statistics_ext_labtool.xml
@@ -0,0 +1,39 @@ @@ -0,0 +1,39 @@
  1 +<?xml version="1.0" encoding="UTF-8" ?>
  2 +<webTalkData fileName='usage_statistics_ext_labtool.xml' majorVersion='1' minorVersion='0' timeStamp='Wed Oct 4 16:06:52 2023'>
  3 +<section name="__ROOT__" level="0" order="1" description="">
  4 + <section name="software_version_and_target_device" level="1" order="1" description="">
  5 + <keyValuePair key="beta" value="FALSE" description="" />
  6 + <keyValuePair key="build_version" value="2552052" description="" />
  7 + <keyValuePair key="date_generated" value="Wed Oct 4 16:06:51 2023" description="" />
  8 + <keyValuePair key="os_platform" value="WIN64" description="" />
  9 + <keyValuePair key="product_version" value="Vivado v2019.1 (64-bit)" description="" />
  10 + <keyValuePair key="project_id" value="58edfc98-0772-4f04-8438-85f24cad8e0d" description="" />
  11 + <keyValuePair key="project_iteration" value="1" description="" />
  12 + <keyValuePair key="random_id" value="543ca123-eb9d-49cf-8266-de8eac9687e5" description="" />
  13 + <keyValuePair key="registration_id" value="543ca123-eb9d-49cf-8266-de8eac9687e5" description="" />
  14 + <keyValuePair key="route_design" value="FALSE" description="" />
  15 + <keyValuePair key="target_device" value="not_applicable" description="" />
  16 + <keyValuePair key="target_family" value="not_applicable" description="" />
  17 + <keyValuePair key="target_package" value="not_applicable" description="" />
  18 + <keyValuePair key="target_speed" value="not_applicable" description="" />
  19 + <keyValuePair key="tool_flow" value="labtool" description="" />
  20 + </section>
  21 + <section name="user_environment" level="1" order="2" description="">
  22 + <keyValuePair key="cpu_name" value="Intel(R) Core(TM) i5-8500 CPU @ 3.00GHz" description="" />
  23 + <keyValuePair key="cpu_speed" value="3000 MHz" description="" />
  24 + <keyValuePair key="os_name" value="Windows Server 2016 or Windows 10" description="" />
  25 + <keyValuePair key="os_release" value="major release (build 9200)" description="" />
  26 + <keyValuePair key="system_ram" value="12.000 GB" description="" />
  27 + <keyValuePair key="total_processors" value="1" description="" />
  28 + </section>
  29 + <section name="labtool" level="1" order="3" description="">
  30 + <section name="usage" level="2" order="1" description="">
  31 + <keyValuePair key="cable" value="Digilent/Basys3/15000000:" description="" />
  32 + <keyValuePair key="chain" value="0362D093" description="" />
  33 + <keyValuePair key="pgmcnt" value="02:00:00" description="" />
  34 + </section>
  35 + </section>
  36 + <section name="vivado_usage" level="1" order="4" description="">
  37 + </section>
  38 +</section>
  39 +</webTalkData>
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_1.xml 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_1.xml
@@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="synth_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
  4 + <Parameters>
  5 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  6 + </Parameters>
  7 +</Runs>
  8 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_10.xml 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_10.xml
@@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="impl_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
  4 + <Parameters>
  5 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  6 + </Parameters>
  7 +</Runs>
  8 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_11.xml 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_11.xml
@@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="impl_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
  4 + <Parameters>
  5 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  6 + </Parameters>
  7 +</Runs>
  8 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_12.xml 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_12.xml
@@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="impl_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
  4 + <Parameters>
  5 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  6 + </Parameters>
  7 +</Runs>
  8 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_13.xml 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_13.xml
@@ -0,0 +1,11 @@ @@ -0,0 +1,11 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="synth_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
  4 + <Run Id="impl_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
  5 + <Parent Id="synth_1"/>
  6 + </Run>
  7 + <Parameters>
  8 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  9 + </Parameters>
  10 +</Runs>
  11 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_14.xml 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_14.xml
@@ -0,0 +1,11 @@ @@ -0,0 +1,11 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="synth_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
  4 + <Run Id="impl_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
  5 + <Parent Id="synth_1"/>
  6 + </Run>
  7 + <Parameters>
  8 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  9 + </Parameters>
  10 +</Runs>
  11 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_15.xml 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_15.xml
@@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="impl_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
  4 + <Parameters>
  5 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  6 + </Parameters>
  7 +</Runs>
  8 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_16.xml 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_16.xml
@@ -0,0 +1,11 @@ @@ -0,0 +1,11 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="synth_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
  4 + <Run Id="impl_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
  5 + <Parent Id="synth_1"/>
  6 + </Run>
  7 + <Parameters>
  8 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  9 + </Parameters>
  10 +</Runs>
  11 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_17.xml 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_17.xml
@@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="impl_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
  4 + <Parameters>
  5 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  6 + </Parameters>
  7 +</Runs>
  8 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_18.xml 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_18.xml
@@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="synth_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
  4 + <Parameters>
  5 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  6 + </Parameters>
  7 +</Runs>
  8 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_19.xml 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_19.xml
@@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="impl_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream"/>
  4 + <Parameters>
  5 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  6 + </Parameters>
  7 +</Runs>
  8 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_2.xml 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_2.xml
@@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="synth_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
  4 + <Parameters>
  5 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  6 + </Parameters>
  7 +</Runs>
  8 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_20.xml 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_20.xml
@@ -0,0 +1,11 @@ @@ -0,0 +1,11 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="synth_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
  4 + <Run Id="impl_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
  5 + <Parent Id="synth_1"/>
  6 + </Run>
  7 + <Parameters>
  8 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  9 + </Parameters>
  10 +</Runs>
  11 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_3.xml 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_3.xml
@@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="impl_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
  4 + <Parameters>
  5 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  6 + </Parameters>
  7 +</Runs>
  8 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_4.xml 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_4.xml
@@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="impl_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
  4 + <Parameters>
  5 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  6 + </Parameters>
  7 +</Runs>
  8 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_5.xml 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_5.xml
@@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="synth_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
  4 + <Parameters>
  5 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  6 + </Parameters>
  7 +</Runs>
  8 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_6.xml 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_6.xml
@@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="synth_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
  4 + <Parameters>
  5 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  6 + </Parameters>
  7 +</Runs>
  8 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_7.xml 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_7.xml
@@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="synth_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
  4 + <Parameters>
  5 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  6 + </Parameters>
  7 +</Runs>
  8 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_8.xml 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_8.xml
@@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="impl_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
  4 + <Parameters>
  5 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  6 + </Parameters>
  7 +</Runs>
  8 +
Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_9.xml 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_9.xml
@@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
  1 +<?xml version="1.0"?>
  2 +<Runs Version="1" Minor="0">
  3 + <Run Id="synth_1" LaunchDir="C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
  4 + <Parameters>
  5 + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
  6 + </Parameters>
  7 +</Runs>
  8 +
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.Vivado_Implementation.queue.rst 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.Vivado_Implementation.queue.rst
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.init_design.begin.rst 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.init_design.begin.rst
@@ -0,0 +1,5 @@ @@ -0,0 +1,5 @@
  1 +<?xml version="1.0"?>
  2 +<ProcessHandle Version="1" Minor="0">
  3 + <Process Command=".planAhead." Owner="profil" Host="WIN10-TP" Pid="9160">
  4 + </Process>
  5 +</ProcessHandle>
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.init_design.end.rst 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.init_design.end.rst
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.opt_design.begin.rst 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.opt_design.begin.rst
@@ -0,0 +1,5 @@ @@ -0,0 +1,5 @@
  1 +<?xml version="1.0"?>
  2 +<ProcessHandle Version="1" Minor="0">
  3 + <Process Command=".planAhead." Owner="profil" Host="WIN10-TP" Pid="9160">
  4 + </Process>
  5 +</ProcessHandle>
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.opt_design.end.rst 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.opt_design.end.rst
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.place_design.begin.rst 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.place_design.begin.rst
@@ -0,0 +1,5 @@ @@ -0,0 +1,5 @@
  1 +<?xml version="1.0"?>
  2 +<ProcessHandle Version="1" Minor="0">
  3 + <Process Command=".planAhead." Owner="profil" Host="WIN10-TP" Pid="9160">
  4 + </Process>
  5 +</ProcessHandle>
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.place_design.end.rst 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.place_design.end.rst
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.route_design.begin.rst 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.route_design.begin.rst
@@ -0,0 +1,5 @@ @@ -0,0 +1,5 @@
  1 +<?xml version="1.0"?>
  2 +<ProcessHandle Version="1" Minor="0">
  3 + <Process Command=".planAhead." Owner="profil" Host="WIN10-TP" Pid="9160">
  4 + </Process>
  5 +</ProcessHandle>
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.route_design.end.rst 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.route_design.end.rst
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.vivado.begin.rst 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.vivado.begin.rst
@@ -0,0 +1,5 @@ @@ -0,0 +1,5 @@
  1 +<?xml version="1.0"?>
  2 +<ProcessHandle Version="1" Minor="0">
  3 + <Process Command="vivado.bat" Owner="profil" Host="WIN10-TP" Pid="6576" HostCore="4" HostMemory="012884365312">
  4 + </Process>
  5 +</ProcessHandle>
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.vivado.end.rst 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.vivado.end.rst
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.write_bitstream.begin.rst 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.write_bitstream.begin.rst
@@ -0,0 +1,5 @@ @@ -0,0 +1,5 @@
  1 +<?xml version="1.0"?>
  2 +<ProcessHandle Version="1" Minor="0">
  3 + <Process Command=".planAhead." Owner="profil" Host="WIN10-TP" Pid="9160">
  4 + </Process>
  5 +</ProcessHandle>
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.write_bitstream.end.rst 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.write_bitstream.end.rst
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.bit 0 → 100755
View file @231d00d
No preview for this file type
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.tcl 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.tcl
@@ -0,0 +1,175 @@ @@ -0,0 +1,175 @@
  1 +#
  2 +# Report generation script generated by Vivado
  3 +#
  4 +
  5 +proc create_report { reportName command } {
  6 + set status "."
  7 + append status $reportName ".fail"
  8 + if { [file exists $status] } {
  9 + eval file delete [glob $status]
  10 + }
  11 + send_msg_id runtcl-4 info "Executing : $command"
  12 + set retval [eval catch { $command } msg]
  13 + if { $retval != 0 } {
  14 + set fp [open $status w]
  15 + close $fp
  16 + send_msg_id runtcl-5 warning "$msg"
  17 + }
  18 +}
  19 +proc start_step { step } {
  20 + set stopFile ".stop.rst"
  21 + if {[file isfile .stop.rst]} {
  22 + puts ""
  23 + puts "*** Halting run - EA reset detected ***"
  24 + puts ""
  25 + puts ""
  26 + return -code error
  27 + }
  28 + set beginFile ".$step.begin.rst"
  29 + set platform "$::tcl_platform(platform)"
  30 + set user "$::tcl_platform(user)"
  31 + set pid [pid]
  32 + set host ""
  33 + if { [string equal $platform unix] } {
  34 + if { [info exist ::env(HOSTNAME)] } {
  35 + set host $::env(HOSTNAME)
  36 + }
  37 + } else {
  38 + if { [info exist ::env(COMPUTERNAME)] } {
  39 + set host $::env(COMPUTERNAME)
  40 + }
  41 + }
  42 + set ch [open $beginFile w]
  43 + puts $ch "<?xml version=\"1.0\"?>"
  44 + puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
  45 + puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
  46 + puts $ch " </Process>"
  47 + puts $ch "</ProcessHandle>"
  48 + close $ch
  49 +}
  50 +
  51 +proc end_step { step } {
  52 + set endFile ".$step.end.rst"
  53 + set ch [open $endFile w]
  54 + close $ch
  55 +}
  56 +
  57 +proc step_failed { step } {
  58 + set endFile ".$step.error.rst"
  59 + set ch [open $endFile w]
  60 + close $ch
  61 +}
  62 +
  63 +set_msg_config -id {Synth 8-256} -limit 10000
  64 +set_msg_config -id {Synth 8-638} -limit 10000
  65 +
  66 +start_step init_design
  67 +set ACTIVE_STEP init_design
  68 +set rc [catch {
  69 + create_msg_db init_design.pb
  70 + set_param chipscope.maxJobs 1
  71 + set_param synth.incrementalSynthesisCache C:/Xilinx/Vivado/2019.1/bin/.Xil/Vivado-7292-WIN10-TP/incrSyn
  72 + set_param xicom.use_bs_reader 1
  73 + create_project -in_memory -part xc7a35tcpg236-1
  74 + set_property board_part digilentinc.com:basys3:part0:1.2 [current_project]
  75 + set_property design_mode GateLvl [current_fileset]
  76 + set_param project.singleFileAddWarning.threshold 0
  77 + set_property webtalk.parent_dir C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.cache/wt [current_project]
  78 + set_property parent.project_path C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.xpr [current_project]
  79 + set_property ip_output_repo C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.cache/ip [current_project]
  80 + set_property ip_cache_permissions {read write} [current_project]
  81 + add_files -quiet C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG.dcp
  82 + read_xdc C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc
  83 + link_design -top Afficheur_7SEG -part xc7a35tcpg236-1
  84 + close_msg_db -file init_design.pb
  85 +} RESULT]
  86 +if {$rc} {
  87 + step_failed init_design
  88 + return -code error $RESULT
  89 +} else {
  90 + end_step init_design
  91 + unset ACTIVE_STEP
  92 +}
  93 +
  94 +start_step opt_design
  95 +set ACTIVE_STEP opt_design
  96 +set rc [catch {
  97 + create_msg_db opt_design.pb
  98 + opt_design
  99 + write_checkpoint -force Afficheur_7SEG_opt.dcp
  100 + create_report "impl_1_opt_report_drc_0" "report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx"
  101 + close_msg_db -file opt_design.pb
  102 +} RESULT]
  103 +if {$rc} {
  104 + step_failed opt_design
  105 + return -code error $RESULT
  106 +} else {
  107 + end_step opt_design
  108 + unset ACTIVE_STEP
  109 +}
  110 +
  111 +start_step place_design
  112 +set ACTIVE_STEP place_design
  113 +set rc [catch {
  114 + create_msg_db place_design.pb
  115 + if { [llength [get_debug_cores -quiet] ] > 0 } {
  116 + implement_debug_core
  117 + }
  118 + place_design
  119 + write_checkpoint -force Afficheur_7SEG_placed.dcp
  120 + create_report "impl_1_place_report_io_0" "report_io -file Afficheur_7SEG_io_placed.rpt"
  121 + create_report "impl_1_place_report_utilization_0" "report_utilization -file Afficheur_7SEG_utilization_placed.rpt -pb Afficheur_7SEG_utilization_placed.pb"
  122 + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file Afficheur_7SEG_control_sets_placed.rpt"
  123 + close_msg_db -file place_design.pb
  124 +} RESULT]
  125 +if {$rc} {
  126 + step_failed place_design
  127 + return -code error $RESULT
  128 +} else {
  129 + end_step place_design
  130 + unset ACTIVE_STEP
  131 +}
  132 +
  133 +start_step route_design
  134 +set ACTIVE_STEP route_design
  135 +set rc [catch {
  136 + create_msg_db route_design.pb
  137 + route_design
  138 + write_checkpoint -force Afficheur_7SEG_routed.dcp
  139 + create_report "impl_1_route_report_drc_0" "report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx"
  140 + create_report "impl_1_route_report_methodology_0" "report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx"
  141 + create_report "impl_1_route_report_power_0" "report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx"
  142 + create_report "impl_1_route_report_route_status_0" "report_route_status -file Afficheur_7SEG_route_status.rpt -pb Afficheur_7SEG_route_status.pb"
  143 + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file Afficheur_7SEG_timing_summary_routed.rpt -pb Afficheur_7SEG_timing_summary_routed.pb -rpx Afficheur_7SEG_timing_summary_routed.rpx -warn_on_violation "
  144 + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file Afficheur_7SEG_incremental_reuse_routed.rpt"
  145 + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file Afficheur_7SEG_clock_utilization_routed.rpt"
  146 + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file Afficheur_7SEG_bus_skew_routed.rpt -pb Afficheur_7SEG_bus_skew_routed.pb -rpx Afficheur_7SEG_bus_skew_routed.rpx"
  147 + close_msg_db -file route_design.pb
  148 +} RESULT]
  149 +if {$rc} {
  150 + write_checkpoint -force Afficheur_7SEG_routed_error.dcp
  151 + step_failed route_design
  152 + return -code error $RESULT
  153 +} else {
  154 + end_step route_design
  155 + unset ACTIVE_STEP
  156 +}
  157 +
  158 +start_step write_bitstream
  159 +set ACTIVE_STEP write_bitstream
  160 +set rc [catch {
  161 + create_msg_db write_bitstream.pb
  162 + catch { write_mem_info -force Afficheur_7SEG.mmi }
  163 + write_bitstream -force Afficheur_7SEG.bit
  164 + catch {write_debug_probes -quiet -force Afficheur_7SEG}
  165 + catch {file copy -force Afficheur_7SEG.ltx debug_nets.ltx}
  166 + close_msg_db -file write_bitstream.pb
  167 +} RESULT]
  168 +if {$rc} {
  169 + step_failed write_bitstream
  170 + return -code error $RESULT
  171 +} else {
  172 + end_step write_bitstream
  173 + unset ACTIVE_STEP
  174 +}
  175 +
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi
@@ -0,0 +1,500 @@ @@ -0,0 +1,500 @@
  1 +#-----------------------------------------------------------
  2 +# Vivado v2019.1 (64-bit)
  3 +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
  4 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
  5 +# Start of session at: Wed Oct 4 15:35:14 2023
  6 +# Process ID: 9160
  7 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1
  8 +# Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace
  9 +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi
  10 +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou
  11 +#-----------------------------------------------------------
  12 +source Afficheur_7SEG.tcl -notrace
  13 +Command: link_design -top Afficheur_7SEG -part xc7a35tcpg236-1
  14 +Design is defaulting to srcset: sources_1
  15 +Design is defaulting to constrset: constrs_1
  16 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1
  17 +INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement
  18 +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
  19 +INFO: [Project 1-479] Netlist was created with Vivado 2019.1
  20 +INFO: [Project 1-570] Preparing netlist for logic optimization
  21 +Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc]
  22 +Finished Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc]
  23 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  24 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 662.551 ; gain = 0.000
  25 +INFO: [Project 1-111] Unisim Transformation Summary:
  26 +No Unisim elements were transformed.
  27 +
  28 +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  29 +link_design completed successfully
  30 +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 666.586 ; gain = 375.434
  31 +Command: opt_design
  32 +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  33 +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  34 +Running DRC as a precondition to command opt_design
  35 +
  36 +Starting DRC Task
  37 +INFO: [DRC 23-27] Running DRC with 2 threads
  38 +INFO: [Project 1-461] DRC finished with 0 Errors
  39 +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
  40 +
  41 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.643 . Memory (MB): peak = 686.492 ; gain = 19.906
  42 +
  43 +Starting Cache Timing Information Task
  44 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  45 +Ending Cache Timing Information Task | Checksum: 1b472ca95
  46 +
  47 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1200.875 ; gain = 514.383
  48 +
  49 +Starting Logic Optimization Task
  50 +
  51 +Phase 1 Retarget
  52 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  53 +INFO: [Opt 31-49] Retargeted 0 cell(s).
  54 +Phase 1 Retarget | Checksum: 1b472ca95
  55 +
  56 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1341.555 ; gain = 0.000
  57 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
  58 +
  59 +Phase 2 Constant propagation
  60 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  61 +Phase 2 Constant propagation | Checksum: 1b472ca95
  62 +
  63 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1341.555 ; gain = 0.000
  64 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
  65 +
  66 +Phase 3 Sweep
  67 +Phase 3 Sweep | Checksum: 1f526e7c3
  68 +
  69 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1341.555 ; gain = 0.000
  70 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
  71 +
  72 +Phase 4 BUFG optimization
  73 +Phase 4 BUFG optimization | Checksum: 1f526e7c3
  74 +
  75 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1341.555 ; gain = 0.000
  76 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
  77 +
  78 +Phase 5 Shift Register Optimization
  79 +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
  80 +Phase 5 Shift Register Optimization | Checksum: 1f526e7c3
  81 +
  82 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1341.555 ; gain = 0.000
  83 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
  84 +
  85 +Phase 6 Post Processing Netlist
  86 +Phase 6 Post Processing Netlist | Checksum: 1f526e7c3
  87 +
  88 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1341.555 ; gain = 0.000
  89 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
  90 +Opt_design Change Summary
  91 +=========================
  92 +
  93 +
  94 +-------------------------------------------------------------------------------------------------------------------------
  95 +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
  96 +-------------------------------------------------------------------------------------------------------------------------
  97 +| Retarget | 0 | 0 | 0 |
  98 +| Constant propagation | 0 | 0 | 0 |
  99 +| Sweep | 0 | 0 | 0 |
  100 +| BUFG optimization | 0 | 0 | 0 |
  101 +| Shift Register Optimization | 0 | 0 | 0 |
  102 +| Post Processing Netlist | 0 | 0 | 0 |
  103 +-------------------------------------------------------------------------------------------------------------------------
  104 +
  105 +
  106 +
  107 +Starting Connectivity Check Task
  108 +
  109 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1341.555 ; gain = 0.000
  110 +Ending Logic Optimization Task | Checksum: 260393764
  111 +
  112 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1341.555 ; gain = 0.000
  113 +
  114 +Starting Power Optimization Task
  115 +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
  116 +Ending Power Optimization Task | Checksum: 260393764
  117 +
  118 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1341.555 ; gain = 0.000
  119 +
  120 +Starting Final Cleanup Task
  121 +Ending Final Cleanup Task | Checksum: 260393764
  122 +
  123 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000
  124 +
  125 +Starting Netlist Obfuscation Task
  126 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000
  127 +Ending Netlist Obfuscation Task | Checksum: 260393764
  128 +
  129 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000
  130 +INFO: [Common 17-83] Releasing license: Implementation
  131 +24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  132 +opt_design completed successfully
  133 +opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1341.555 ; gain = 674.969
  134 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000
  135 +INFO: [Timing 38-480] Writing timing data to binary archive.
  136 +Writing placer database...
  137 +Writing XDEF routing.
  138 +Writing XDEF routing logical nets.
  139 +Writing XDEF routing special nets.
  140 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1341.555 ; gain = 0.000
  141 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_opt.dcp' has been generated.
  142 +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx
  143 +Command: report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx
  144 +INFO: [IP_Flow 19-234] Refreshing IP repositories
  145 +INFO: [IP_Flow 19-1704] No user IP repositories specified
  146 +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'.
  147 +INFO: [DRC 23-27] Running DRC with 2 threads
  148 +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpt.
  149 +report_drc completed successfully
  150 +Command: place_design
  151 +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  152 +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  153 +INFO: [DRC 23-27] Running DRC with 2 threads
  154 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  155 +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  156 +Running DRC as a precondition to command place_design
  157 +INFO: [DRC 23-27] Running DRC with 2 threads
  158 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  159 +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  160 +
  161 +Starting Placer Task
  162 +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
  163 +
  164 +Phase 1 Placer Initialization
  165 +
  166 +Phase 1.1 Placer Initialization Netlist Sorting
  167 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000
  168 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1d171f48f
  169 +
  170 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1341.555 ; gain = 0.000
  171 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1341.555 ; gain = 0.000
  172 +
  173 +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
  174 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  175 +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1b8f8806f
  176 +
  177 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.835 . Memory (MB): peak = 1341.555 ; gain = 0.000
  178 +
  179 +Phase 1.3 Build Placer Netlist Model
  180 +Phase 1.3 Build Placer Netlist Model | Checksum: 2ac1244c8
  181 +
  182 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.847 . Memory (MB): peak = 1341.555 ; gain = 0.000
  183 +
  184 +Phase 1.4 Constrain Clocks/Macros
  185 +Phase 1.4 Constrain Clocks/Macros | Checksum: 2ac1244c8
  186 +
  187 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.849 . Memory (MB): peak = 1341.555 ; gain = 0.000
  188 +Phase 1 Placer Initialization | Checksum: 2ac1244c8
  189 +
  190 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.850 . Memory (MB): peak = 1341.555 ; gain = 0.000
  191 +
  192 +Phase 2 Global Placement
  193 +
  194 +Phase 2.1 Floorplanning
  195 +Phase 2.1 Floorplanning | Checksum: 2ac1244c8
  196 +
  197 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.852 . Memory (MB): peak = 1341.555 ; gain = 0.000
  198 +
  199 +Phase 2.2 Global Placement Core
  200 +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
  201 +Phase 2.2 Global Placement Core | Checksum: 21c4ed49b
  202 +
  203 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  204 +Phase 2 Global Placement | Checksum: 21c4ed49b
  205 +
  206 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  207 +
  208 +Phase 3 Detail Placement
  209 +
  210 +Phase 3.1 Commit Multi Column Macros
  211 +Phase 3.1 Commit Multi Column Macros | Checksum: 21c4ed49b
  212 +
  213 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  214 +
  215 +Phase 3.2 Commit Most Macros & LUTRAMs
  216 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18a378908
  217 +
  218 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  219 +
  220 +Phase 3.3 Area Swap Optimization
  221 +Phase 3.3 Area Swap Optimization | Checksum: 216e3a3c1
  222 +
  223 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  224 +
  225 +Phase 3.4 Pipeline Register Optimization
  226 +Phase 3.4 Pipeline Register Optimization | Checksum: 216e3a3c1
  227 +
  228 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  229 +
  230 +Phase 3.5 Small Shape Detail Placement
  231 +Phase 3.5 Small Shape Detail Placement | Checksum: 19592b163
  232 +
  233 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  234 +
  235 +Phase 3.6 Re-assign LUT pins
  236 +Phase 3.6 Re-assign LUT pins | Checksum: 19592b163
  237 +
  238 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  239 +
  240 +Phase 3.7 Pipeline Register Optimization
  241 +Phase 3.7 Pipeline Register Optimization | Checksum: 19592b163
  242 +
  243 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  244 +Phase 3 Detail Placement | Checksum: 19592b163
  245 +
  246 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  247 +
  248 +Phase 4 Post Placement Optimization and Clean-Up
  249 +
  250 +Phase 4.1 Post Commit Optimization
  251 +Phase 4.1 Post Commit Optimization | Checksum: 19592b163
  252 +
  253 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  254 +
  255 +Phase 4.2 Post Placement Cleanup
  256 +Phase 4.2 Post Placement Cleanup | Checksum: 19592b163
  257 +
  258 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  259 +
  260 +Phase 4.3 Placer Reporting
  261 +Phase 4.3 Placer Reporting | Checksum: 19592b163
  262 +
  263 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  264 +
  265 +Phase 4.4 Final Placement Cleanup
  266 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1341.555 ; gain = 0.000
  267 +Phase 4.4 Final Placement Cleanup | Checksum: 19592b163
  268 +
  269 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  270 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 19592b163
  271 +
  272 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  273 +Ending Placer Task | Checksum: 16b3cb9b6
  274 +
  275 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  276 +INFO: [Common 17-83] Releasing license: Implementation
  277 +42 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
  278 +place_design completed successfully
  279 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000
  280 +INFO: [Timing 38-480] Writing timing data to binary archive.
  281 +Writing placer database...
  282 +Writing XDEF routing.
  283 +Writing XDEF routing logical nets.
  284 +Writing XDEF routing special nets.
  285 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1352.461 ; gain = 10.906
  286 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_placed.dcp' has been generated.
  287 +INFO: [runtcl-4] Executing : report_io -file Afficheur_7SEG_io_placed.rpt
  288 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1352.461 ; gain = 0.000
  289 +INFO: [runtcl-4] Executing : report_utilization -file Afficheur_7SEG_utilization_placed.rpt -pb Afficheur_7SEG_utilization_placed.pb
  290 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file Afficheur_7SEG_control_sets_placed.rpt
  291 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1352.461 ; gain = 0.000
  292 +Command: route_design
  293 +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  294 +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  295 +Running DRC as a precondition to command route_design
  296 +INFO: [DRC 23-27] Running DRC with 2 threads
  297 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  298 +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  299 +
  300 +
  301 +Starting Routing Task
  302 +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
  303 +Checksum: PlaceDB: 92aaeef2 ConstDB: 0 ShapeSum: d891cac4 RouteDB: 0
  304 +
  305 +Phase 1 Build RT Design
  306 +Phase 1 Build RT Design | Checksum: 9fc16879
  307 +
  308 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1442.992 ; gain = 79.531
  309 +Post Restoration Checksum: NetGraph: 769cd3b9 NumContArr: 292494c0 Constraints: 0 Timing: 0
  310 +
  311 +Phase 2 Router Initialization
  312 +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
  313 +
  314 +Phase 2.1 Fix Topology Constraints
  315 +Phase 2.1 Fix Topology Constraints | Checksum: 9fc16879
  316 +
  317 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1449.000 ; gain = 85.539
  318 +
  319 +Phase 2.2 Pre Route Cleanup
  320 +Phase 2.2 Pre Route Cleanup | Checksum: 9fc16879
  321 +
  322 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1449.000 ; gain = 85.539
  323 + Number of Nodes with overlaps = 0
  324 +Phase 2 Router Initialization | Checksum: 16939516a
  325 +
  326 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1452.375 ; gain = 88.914
  327 +
  328 +Router Utilization Summary
  329 + Global Vertical Routing Utilization = 0 %
  330 + Global Horizontal Routing Utilization = 0 %
  331 + Routable Net Status*
  332 + *Does not include unroutable nets such as driverless and loadless.
  333 + Run report_route_status for detailed report.
  334 + Number of Failed Nets = 32
  335 + (Failed Nets is the sum of unrouted and partially routed nets)
  336 + Number of Unrouted Nets = 32
  337 + Number of Partially Routed Nets = 0
  338 + Number of Node Overlaps = 0
  339 +
  340 +
  341 +Phase 3 Initial Routing
  342 +Phase 3 Initial Routing | Checksum: 106a7763c
  343 +
  344 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027
  345 +
  346 +Phase 4 Rip-up And Reroute
  347 +
  348 +Phase 4.1 Global Iteration 0
  349 + Number of Nodes with overlaps = 0
  350 +Phase 4.1 Global Iteration 0 | Checksum: 131215cb1
  351 +
  352 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027
  353 +Phase 4 Rip-up And Reroute | Checksum: 131215cb1
  354 +
  355 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027
  356 +
  357 +Phase 5 Delay and Skew Optimization
  358 +Phase 5 Delay and Skew Optimization | Checksum: 131215cb1
  359 +
  360 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027
  361 +
  362 +Phase 6 Post Hold Fix
  363 +
  364 +Phase 6.1 Hold Fix Iter
  365 +Phase 6.1 Hold Fix Iter | Checksum: 131215cb1
  366 +
  367 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027
  368 +Phase 6 Post Hold Fix | Checksum: 131215cb1
  369 +
  370 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027
  371 +
  372 +Phase 7 Route finalize
  373 +
  374 +Router Utilization Summary
  375 + Global Vertical Routing Utilization = 0.0058997 %
  376 + Global Horizontal Routing Utilization = 0.0158771 %
  377 + Routable Net Status*
  378 + *Does not include unroutable nets such as driverless and loadless.
  379 + Run report_route_status for detailed report.
  380 + Number of Failed Nets = 0
  381 + (Failed Nets is the sum of unrouted and partially routed nets)
  382 + Number of Unrouted Nets = 0
  383 + Number of Partially Routed Nets = 0
  384 + Number of Node Overlaps = 0
  385 +
  386 +Congestion Report
  387 +North Dir 1x1 Area, Max Cong = 9.90991%, No Congested Regions.
  388 +South Dir 1x1 Area, Max Cong = 9.00901%, No Congested Regions.
  389 +East Dir 1x1 Area, Max Cong = 23.5294%, No Congested Regions.
  390 +West Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions.
  391 +
  392 +------------------------------
  393 +Reporting congestion hotspots
  394 +------------------------------
  395 +Direction: North
  396 +----------------
  397 +Congested clusters found at Level 0
  398 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  399 +Direction: South
  400 +----------------
  401 +Congested clusters found at Level 0
  402 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  403 +Direction: East
  404 +----------------
  405 +Congested clusters found at Level 0
  406 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  407 +Direction: West
  408 +----------------
  409 +Congested clusters found at Level 0
  410 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  411 +
  412 +Phase 7 Route finalize | Checksum: 131215cb1
  413 +
  414 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027
  415 +
  416 +Phase 8 Verifying routed nets
  417 +
  418 + Verification completed successfully
  419 +Phase 8 Verifying routed nets | Checksum: 131215cb1
  420 +
  421 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1455.516 ; gain = 92.055
  422 +
  423 +Phase 9 Depositing Routes
  424 +Phase 9 Depositing Routes | Checksum: 1cda4acbc
  425 +
  426 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1455.516 ; gain = 92.055
  427 +INFO: [Route 35-16] Router Completed Successfully
  428 +
  429 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1455.516 ; gain = 92.055
  430 +
  431 +Routing Is Done.
  432 +INFO: [Common 17-83] Releasing license: Implementation
  433 +55 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
  434 +route_design completed successfully
  435 +route_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1455.516 ; gain = 103.055
  436 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1455.516 ; gain = 0.000
  437 +INFO: [Timing 38-480] Writing timing data to binary archive.
  438 +Writing placer database...
  439 +Writing XDEF routing.
  440 +Writing XDEF routing logical nets.
  441 +Writing XDEF routing special nets.
  442 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1465.422 ; gain = 9.906
  443 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_routed.dcp' has been generated.
  444 +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx
  445 +Command: report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx
  446 +INFO: [IP_Flow 19-1839] IP Catalog is up to date.
  447 +INFO: [DRC 23-27] Running DRC with 2 threads
  448 +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpt.
  449 +report_drc completed successfully
  450 +INFO: [runtcl-4] Executing : report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx
  451 +Command: report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx
  452 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  453 +INFO: [DRC 23-133] Running Methodology with 2 threads
  454 +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.rpt.
  455 +report_methodology completed successfully
  456 +INFO: [runtcl-4] Executing : report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx
  457 +Command: report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx
  458 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  459 +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
  460 +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
  461 +Running Vector-less Activity Propagation...
  462 +
  463 +Finished Running Vector-less Activity Propagation
  464 +67 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
  465 +report_power completed successfully
  466 +INFO: [runtcl-4] Executing : report_route_status -file Afficheur_7SEG_route_status.rpt -pb Afficheur_7SEG_route_status.pb
  467 +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Afficheur_7SEG_timing_summary_routed.rpt -pb Afficheur_7SEG_timing_summary_routed.pb -rpx Afficheur_7SEG_timing_summary_routed.rpx -warn_on_violation
  468 +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
  469 +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
  470 +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
  471 +INFO: [runtcl-4] Executing : report_incremental_reuse -file Afficheur_7SEG_incremental_reuse_routed.rpt
  472 +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
  473 +INFO: [runtcl-4] Executing : report_clock_utilization -file Afficheur_7SEG_clock_utilization_routed.rpt
  474 +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Afficheur_7SEG_bus_skew_routed.rpt -pb Afficheur_7SEG_bus_skew_routed.pb -rpx Afficheur_7SEG_bus_skew_routed.rpx
  475 +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
  476 +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
  477 +Command: write_bitstream -force Afficheur_7SEG.bit
  478 +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  479 +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  480 +Running DRC as a precondition to command write_bitstream
  481 +INFO: [IP_Flow 19-1839] IP Catalog is up to date.
  482 +INFO: [DRC 23-27] Running DRC with 2 threads
  483 +INFO: [Vivado 12-3199] DRC finished with 0 Errors
  484 +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
  485 +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
  486 +Loading data files...
  487 +Loading site data...
  488 +Loading route data...
  489 +Processing options...
  490 +Creating bitmap...
  491 +Creating bitstream...
  492 +Bitstream compression saved 15755616 bits.
  493 +Writing bitstream ./Afficheur_7SEG.bit...
  494 +INFO: [Vivado 12-1842] Bitgen Completed Successfully.
  495 +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
  496 +INFO: [Common 17-83] Releasing license: Implementation
  497 +86 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
  498 +write_bitstream completed successfully
  499 +write_bitstream: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1920.316 ; gain = 405.871
  500 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 4 15:36:15 2023...
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_2876.backup.vdi 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_2876.backup.vdi
@@ -0,0 +1,483 @@ @@ -0,0 +1,483 @@
  1 +#-----------------------------------------------------------
  2 +# Vivado v2019.1 (64-bit)
  3 +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
  4 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
  5 +# Start of session at: Wed Oct 4 15:26:28 2023
  6 +# Process ID: 2876
  7 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1
  8 +# Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace
  9 +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi
  10 +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou
  11 +#-----------------------------------------------------------
  12 +source Afficheur_7SEG.tcl -notrace
  13 +Command: link_design -top Afficheur_7SEG -part xc7a35tcpg236-1
  14 +Design is defaulting to srcset: sources_1
  15 +Design is defaulting to constrset: constrs_1
  16 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1
  17 +INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement
  18 +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
  19 +INFO: [Project 1-479] Netlist was created with Vivado 2019.1
  20 +INFO: [Project 1-570] Preparing netlist for logic optimization
  21 +Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc]
  22 +WARNING: [Vivado 12-584] No ports matched 'clk'. [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc:7]
  23 +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc:7]
  24 +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
  25 +WARNING: [Vivado 12-584] No ports matched 'clk'. [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc:8]
  26 +CRITICAL WARNING: [Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_ports clk]'. [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc:8]
  27 +Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
  28 +Finished Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc]
  29 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  30 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 663.098 ; gain = 0.000
  31 +INFO: [Project 1-111] Unisim Transformation Summary:
  32 +No Unisim elements were transformed.
  33 +
  34 +7 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.
  35 +link_design completed successfully
  36 +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 667.098 ; gain = 376.230
  37 +Command: opt_design
  38 +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  39 +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  40 +Running DRC as a precondition to command opt_design
  41 +
  42 +Starting DRC Task
  43 +INFO: [DRC 23-27] Running DRC with 2 threads
  44 +INFO: [Project 1-461] DRC finished with 0 Errors
  45 +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
  46 +
  47 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.637 . Memory (MB): peak = 687.031 ; gain = 19.934
  48 +
  49 +Starting Cache Timing Information Task
  50 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  51 +Ending Cache Timing Information Task | Checksum: 1a6e4ed6b
  52 +
  53 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1200.539 ; gain = 513.508
  54 +
  55 +Starting Logic Optimization Task
  56 +
  57 +Phase 1 Retarget
  58 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  59 +INFO: [Opt 31-49] Retargeted 0 cell(s).
  60 +Phase 1 Retarget | Checksum: 1a6e4ed6b
  61 +
  62 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1342.637 ; gain = 0.000
  63 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
  64 +
  65 +Phase 2 Constant propagation
  66 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  67 +Phase 2 Constant propagation | Checksum: 1a6e4ed6b
  68 +
  69 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1342.637 ; gain = 0.000
  70 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
  71 +
  72 +Phase 3 Sweep
  73 +Phase 3 Sweep | Checksum: 1b4ebe95c
  74 +
  75 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1342.637 ; gain = 0.000
  76 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
  77 +
  78 +Phase 4 BUFG optimization
  79 +Phase 4 BUFG optimization | Checksum: 1b4ebe95c
  80 +
  81 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1342.637 ; gain = 0.000
  82 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
  83 +
  84 +Phase 5 Shift Register Optimization
  85 +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
  86 +Phase 5 Shift Register Optimization | Checksum: 1b4ebe95c
  87 +
  88 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1342.637 ; gain = 0.000
  89 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
  90 +
  91 +Phase 6 Post Processing Netlist
  92 +Phase 6 Post Processing Netlist | Checksum: 1b4ebe95c
  93 +
  94 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1342.637 ; gain = 0.000
  95 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
  96 +Opt_design Change Summary
  97 +=========================
  98 +
  99 +
  100 +-------------------------------------------------------------------------------------------------------------------------
  101 +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
  102 +-------------------------------------------------------------------------------------------------------------------------
  103 +| Retarget | 0 | 0 | 0 |
  104 +| Constant propagation | 0 | 0 | 0 |
  105 +| Sweep | 0 | 0 | 0 |
  106 +| BUFG optimization | 0 | 0 | 0 |
  107 +| Shift Register Optimization | 0 | 0 | 0 |
  108 +| Post Processing Netlist | 0 | 0 | 0 |
  109 +-------------------------------------------------------------------------------------------------------------------------
  110 +
  111 +
  112 +
  113 +Starting Connectivity Check Task
  114 +
  115 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.637 ; gain = 0.000
  116 +Ending Logic Optimization Task | Checksum: 1779474dc
  117 +
  118 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1342.637 ; gain = 0.000
  119 +
  120 +Starting Power Optimization Task
  121 +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
  122 +Ending Power Optimization Task | Checksum: 1779474dc
  123 +
  124 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1342.637 ; gain = 0.000
  125 +
  126 +Starting Final Cleanup Task
  127 +Ending Final Cleanup Task | Checksum: 1779474dc
  128 +
  129 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.637 ; gain = 0.000
  130 +
  131 +Starting Netlist Obfuscation Task
  132 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.637 ; gain = 0.000
  133 +Ending Netlist Obfuscation Task | Checksum: 1779474dc
  134 +
  135 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.637 ; gain = 0.000
  136 +INFO: [Common 17-83] Releasing license: Implementation
  137 +24 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.
  138 +opt_design completed successfully
  139 +opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1342.637 ; gain = 675.539
  140 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.637 ; gain = 0.000
  141 +INFO: [Timing 38-480] Writing timing data to binary archive.
  142 +Writing placer database...
  143 +Writing XDEF routing.
  144 +Writing XDEF routing logical nets.
  145 +Writing XDEF routing special nets.
  146 +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1342.637 ; gain = 0.000
  147 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_opt.dcp' has been generated.
  148 +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx
  149 +Command: report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx
  150 +INFO: [IP_Flow 19-234] Refreshing IP repositories
  151 +INFO: [IP_Flow 19-1704] No user IP repositories specified
  152 +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'.
  153 +INFO: [DRC 23-27] Running DRC with 2 threads
  154 +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpt.
  155 +report_drc completed successfully
  156 +Command: place_design
  157 +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  158 +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  159 +INFO: [DRC 23-27] Running DRC with 2 threads
  160 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  161 +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  162 +Running DRC as a precondition to command place_design
  163 +INFO: [DRC 23-27] Running DRC with 2 threads
  164 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  165 +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  166 +
  167 +Starting Placer Task
  168 +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
  169 +
  170 +Phase 1 Placer Initialization
  171 +
  172 +Phase 1.1 Placer Initialization Netlist Sorting
  173 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.637 ; gain = 0.000
  174 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 166f00538
  175 +
  176 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1342.637 ; gain = 0.000
  177 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.637 ; gain = 0.000
  178 +
  179 +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
  180 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  181 +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1780aa8b2
  182 +
  183 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.822 . Memory (MB): peak = 1342.637 ; gain = 0.000
  184 +
  185 +Phase 1.3 Build Placer Netlist Model
  186 +Phase 1.3 Build Placer Netlist Model | Checksum: 24b03694f
  187 +
  188 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.834 . Memory (MB): peak = 1342.637 ; gain = 0.000
  189 +
  190 +Phase 1.4 Constrain Clocks/Macros
  191 +Phase 1.4 Constrain Clocks/Macros | Checksum: 24b03694f
  192 +
  193 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.836 . Memory (MB): peak = 1342.637 ; gain = 0.000
  194 +Phase 1 Placer Initialization | Checksum: 24b03694f
  195 +
  196 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.837 . Memory (MB): peak = 1342.637 ; gain = 0.000
  197 +
  198 +Phase 2 Global Placement
  199 +
  200 +Phase 2.1 Floorplanning
  201 +Phase 2.1 Floorplanning | Checksum: 24b03694f
  202 +
  203 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.839 . Memory (MB): peak = 1342.637 ; gain = 0.000
  204 +
  205 +Phase 2.2 Global Placement Core
  206 +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
  207 +Phase 2.2 Global Placement Core | Checksum: 21360a59b
  208 +
  209 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000
  210 +Phase 2 Global Placement | Checksum: 21360a59b
  211 +
  212 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000
  213 +
  214 +Phase 3 Detail Placement
  215 +
  216 +Phase 3.1 Commit Multi Column Macros
  217 +Phase 3.1 Commit Multi Column Macros | Checksum: 21360a59b
  218 +
  219 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000
  220 +
  221 +Phase 3.2 Commit Most Macros & LUTRAMs
  222 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 252e7eb40
  223 +
  224 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000
  225 +
  226 +Phase 3.3 Area Swap Optimization
  227 +Phase 3.3 Area Swap Optimization | Checksum: 1e0afcabc
  228 +
  229 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000
  230 +
  231 +Phase 3.4 Pipeline Register Optimization
  232 +Phase 3.4 Pipeline Register Optimization | Checksum: 1e0afcabc
  233 +
  234 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000
  235 +
  236 +Phase 3.5 Small Shape Detail Placement
  237 +Phase 3.5 Small Shape Detail Placement | Checksum: 241014ff4
  238 +
  239 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000
  240 +
  241 +Phase 3.6 Re-assign LUT pins
  242 +Phase 3.6 Re-assign LUT pins | Checksum: 241014ff4
  243 +
  244 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000
  245 +
  246 +Phase 3.7 Pipeline Register Optimization
  247 +Phase 3.7 Pipeline Register Optimization | Checksum: 241014ff4
  248 +
  249 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000
  250 +Phase 3 Detail Placement | Checksum: 241014ff4
  251 +
  252 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000
  253 +
  254 +Phase 4 Post Placement Optimization and Clean-Up
  255 +
  256 +Phase 4.1 Post Commit Optimization
  257 +Phase 4.1 Post Commit Optimization | Checksum: 241014ff4
  258 +
  259 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000
  260 +
  261 +Phase 4.2 Post Placement Cleanup
  262 +Phase 4.2 Post Placement Cleanup | Checksum: 241014ff4
  263 +
  264 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000
  265 +
  266 +Phase 4.3 Placer Reporting
  267 +Phase 4.3 Placer Reporting | Checksum: 241014ff4
  268 +
  269 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000
  270 +
  271 +Phase 4.4 Final Placement Cleanup
  272 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.637 ; gain = 0.000
  273 +Phase 4.4 Final Placement Cleanup | Checksum: 241014ff4
  274 +
  275 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000
  276 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 241014ff4
  277 +
  278 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000
  279 +Ending Placer Task | Checksum: 1619377e0
  280 +
  281 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000
  282 +INFO: [Common 17-83] Releasing license: Implementation
  283 +42 Infos, 3 Warnings, 2 Critical Warnings and 0 Errors encountered.
  284 +place_design completed successfully
  285 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.637 ; gain = 0.000
  286 +INFO: [Timing 38-480] Writing timing data to binary archive.
  287 +Writing placer database...
  288 +Writing XDEF routing.
  289 +Writing XDEF routing logical nets.
  290 +Writing XDEF routing special nets.
  291 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1352.469 ; gain = 9.832
  292 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_placed.dcp' has been generated.
  293 +INFO: [runtcl-4] Executing : report_io -file Afficheur_7SEG_io_placed.rpt
  294 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1352.469 ; gain = 0.000
  295 +INFO: [runtcl-4] Executing : report_utilization -file Afficheur_7SEG_utilization_placed.rpt -pb Afficheur_7SEG_utilization_placed.pb
  296 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file Afficheur_7SEG_control_sets_placed.rpt
  297 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1352.469 ; gain = 0.000
  298 +Command: route_design
  299 +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  300 +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  301 +Running DRC as a precondition to command route_design
  302 +INFO: [DRC 23-27] Running DRC with 2 threads
  303 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  304 +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  305 +
  306 +
  307 +Starting Routing Task
  308 +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
  309 +Checksum: PlaceDB: 8901ad1c ConstDB: 0 ShapeSum: d891cac4 RouteDB: 0
  310 +
  311 +Phase 1 Build RT Design
  312 +Phase 1 Build RT Design | Checksum: 1323cb683
  313 +
  314 +Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 1445.840 ; gain = 80.777
  315 +Post Restoration Checksum: NetGraph: 6bfd2bd0 NumContArr: c63f8ab3 Constraints: 0 Timing: 0
  316 +
  317 +Phase 2 Router Initialization
  318 +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
  319 +
  320 +Phase 2.1 Fix Topology Constraints
  321 +Phase 2.1 Fix Topology Constraints | Checksum: 1323cb683
  322 +
  323 +Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 1451.855 ; gain = 86.793
  324 +
  325 +Phase 2.2 Pre Route Cleanup
  326 +Phase 2.2 Pre Route Cleanup | Checksum: 1323cb683
  327 +
  328 +Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 1451.855 ; gain = 86.793
  329 + Number of Nodes with overlaps = 0
  330 +Phase 2 Router Initialization | Checksum: 1830f2667
  331 +
  332 +Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 1455.430 ; gain = 90.367
  333 +
  334 +Router Utilization Summary
  335 + Global Vertical Routing Utilization = 0 %
  336 + Global Horizontal Routing Utilization = 0 %
  337 + Routable Net Status*
  338 + *Does not include unroutable nets such as driverless and loadless.
  339 + Run report_route_status for detailed report.
  340 + Number of Failed Nets = 32
  341 + (Failed Nets is the sum of unrouted and partially routed nets)
  342 + Number of Unrouted Nets = 32
  343 + Number of Partially Routed Nets = 0
  344 + Number of Node Overlaps = 0
  345 +
  346 +
  347 +Phase 3 Initial Routing
  348 +Phase 3 Initial Routing | Checksum: 109c2c817
  349 +
  350 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1456.266 ; gain = 91.203
  351 +
  352 +Phase 4 Rip-up And Reroute
  353 +
  354 +Phase 4.1 Global Iteration 0
  355 + Number of Nodes with overlaps = 0
  356 +Phase 4.1 Global Iteration 0 | Checksum: 13e90e783
  357 +
  358 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1456.266 ; gain = 91.203
  359 +Phase 4 Rip-up And Reroute | Checksum: 13e90e783
  360 +
  361 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1456.266 ; gain = 91.203
  362 +
  363 +Phase 5 Delay and Skew Optimization
  364 +Phase 5 Delay and Skew Optimization | Checksum: 13e90e783
  365 +
  366 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1456.266 ; gain = 91.203
  367 +
  368 +Phase 6 Post Hold Fix
  369 +
  370 +Phase 6.1 Hold Fix Iter
  371 +Phase 6.1 Hold Fix Iter | Checksum: 13e90e783
  372 +
  373 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1456.266 ; gain = 91.203
  374 +Phase 6 Post Hold Fix | Checksum: 13e90e783
  375 +
  376 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1456.266 ; gain = 91.203
  377 +
  378 +Phase 7 Route finalize
  379 +
  380 +Router Utilization Summary
  381 + Global Vertical Routing Utilization = 0.00550108 %
  382 + Global Horizontal Routing Utilization = 0.0163977 %
  383 + Routable Net Status*
  384 + *Does not include unroutable nets such as driverless and loadless.
  385 + Run report_route_status for detailed report.
  386 + Number of Failed Nets = 0
  387 + (Failed Nets is the sum of unrouted and partially routed nets)
  388 + Number of Unrouted Nets = 0
  389 + Number of Partially Routed Nets = 0
  390 + Number of Node Overlaps = 0
  391 +
  392 +Congestion Report
  393 +North Dir 1x1 Area, Max Cong = 6.30631%, No Congested Regions.
  394 +South Dir 1x1 Area, Max Cong = 17.1171%, No Congested Regions.
  395 +East Dir 1x1 Area, Max Cong = 23.5294%, No Congested Regions.
  396 +West Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions.
  397 +
  398 +------------------------------
  399 +Reporting congestion hotspots
  400 +------------------------------
  401 +Direction: North
  402 +----------------
  403 +Congested clusters found at Level 0
  404 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  405 +Direction: South
  406 +----------------
  407 +Congested clusters found at Level 0
  408 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  409 +Direction: East
  410 +----------------
  411 +Congested clusters found at Level 0
  412 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  413 +Direction: West
  414 +----------------
  415 +Congested clusters found at Level 0
  416 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  417 +
  418 +Phase 7 Route finalize | Checksum: 13e90e783
  419 +
  420 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1456.266 ; gain = 91.203
  421 +
  422 +Phase 8 Verifying routed nets
  423 +
  424 + Verification completed successfully
  425 +Phase 8 Verifying routed nets | Checksum: 13e90e783
  426 +
  427 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.332 ; gain = 93.270
  428 +
  429 +Phase 9 Depositing Routes
  430 +Phase 9 Depositing Routes | Checksum: 7d951ad6
  431 +
  432 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.332 ; gain = 93.270
  433 +INFO: [Route 35-16] Router Completed Successfully
  434 +
  435 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.332 ; gain = 93.270
  436 +
  437 +Routing Is Done.
  438 +INFO: [Common 17-83] Releasing license: Implementation
  439 +55 Infos, 3 Warnings, 2 Critical Warnings and 0 Errors encountered.
  440 +route_design completed successfully
  441 +route_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1458.332 ; gain = 105.863
  442 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1458.332 ; gain = 0.000
  443 +INFO: [Timing 38-480] Writing timing data to binary archive.
  444 +Writing placer database...
  445 +Writing XDEF routing.
  446 +Writing XDEF routing logical nets.
  447 +Writing XDEF routing special nets.
  448 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1468.191 ; gain = 9.859
  449 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_routed.dcp' has been generated.
  450 +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx
  451 +Command: report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx
  452 +INFO: [IP_Flow 19-1839] IP Catalog is up to date.
  453 +INFO: [DRC 23-27] Running DRC with 2 threads
  454 +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpt.
  455 +report_drc completed successfully
  456 +INFO: [runtcl-4] Executing : report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx
  457 +Command: report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx
  458 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  459 +INFO: [DRC 23-133] Running Methodology with 2 threads
  460 +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.rpt.
  461 +report_methodology completed successfully
  462 +INFO: [runtcl-4] Executing : report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx
  463 +Command: report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx
  464 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  465 +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
  466 +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
  467 +Running Vector-less Activity Propagation...
  468 +
  469 +Finished Running Vector-less Activity Propagation
  470 +67 Infos, 4 Warnings, 2 Critical Warnings and 0 Errors encountered.
  471 +report_power completed successfully
  472 +INFO: [runtcl-4] Executing : report_route_status -file Afficheur_7SEG_route_status.rpt -pb Afficheur_7SEG_route_status.pb
  473 +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Afficheur_7SEG_timing_summary_routed.rpt -pb Afficheur_7SEG_timing_summary_routed.pb -rpx Afficheur_7SEG_timing_summary_routed.rpx -warn_on_violation
  474 +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
  475 +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
  476 +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
  477 +INFO: [runtcl-4] Executing : report_incremental_reuse -file Afficheur_7SEG_incremental_reuse_routed.rpt
  478 +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
  479 +INFO: [runtcl-4] Executing : report_clock_utilization -file Afficheur_7SEG_clock_utilization_routed.rpt
  480 +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Afficheur_7SEG_bus_skew_routed.rpt -pb Afficheur_7SEG_bus_skew_routed.pb -rpx Afficheur_7SEG_bus_skew_routed.rpx
  481 +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
  482 +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
  483 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 4 15:27:17 2023...
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_3012.backup.vdi 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_3012.backup.vdi
@@ -0,0 +1,485 @@ @@ -0,0 +1,485 @@
  1 +#-----------------------------------------------------------
  2 +# Vivado v2019.1 (64-bit)
  3 +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
  4 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
  5 +# Start of session at: Wed Oct 4 14:25:17 2023
  6 +# Process ID: 3012
  7 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1
  8 +# Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace
  9 +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi
  10 +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou
  11 +#-----------------------------------------------------------
  12 +source Afficheur_7SEG.tcl -notrace
  13 +Command: link_design -top Afficheur_7SEG -part xc7a35tcpg236-1
  14 +Design is defaulting to srcset: sources_1
  15 +Design is defaulting to constrset: constrs_1
  16 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1
  17 +INFO: [Project 1-479] Netlist was created with Vivado 2019.1
  18 +INFO: [Project 1-570] Preparing netlist for logic optimization
  19 +Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc]
  20 +Finished Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc]
  21 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  22 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 662.062 ; gain = 0.000
  23 +INFO: [Project 1-111] Unisim Transformation Summary:
  24 +No Unisim elements were transformed.
  25 +
  26 +5 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  27 +link_design completed successfully
  28 +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 666.074 ; gain = 366.730
  29 +Command: opt_design
  30 +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  31 +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  32 +Running DRC as a precondition to command opt_design
  33 +
  34 +Starting DRC Task
  35 +INFO: [DRC 23-27] Running DRC with 2 threads
  36 +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[0] expects both input and output buffering but the buffers are incomplete.
  37 +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[1] expects both input and output buffering but the buffers are incomplete.
  38 +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[2] expects both input and output buffering but the buffers are incomplete.
  39 +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[3] expects both input and output buffering but the buffers are incomplete.
  40 +INFO: [Project 1-461] DRC finished with 0 Errors, 4 Warnings
  41 +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
  42 +
  43 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.701 . Memory (MB): peak = 685.441 ; gain = 19.367
  44 +
  45 +Starting Cache Timing Information Task
  46 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  47 +Ending Cache Timing Information Task | Checksum: 19ae0d74a
  48 +
  49 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1219.293 ; gain = 533.852
  50 +
  51 +Starting Logic Optimization Task
  52 +
  53 +Phase 1 Retarget
  54 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  55 +INFO: [Opt 31-49] Retargeted 0 cell(s).
  56 +Phase 1 Retarget | Checksum: 19ae0d74a
  57 +
  58 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1362.355 ; gain = 0.000
  59 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
  60 +
  61 +Phase 2 Constant propagation
  62 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  63 +Phase 2 Constant propagation | Checksum: 19ae0d74a
  64 +
  65 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1362.355 ; gain = 0.000
  66 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
  67 +
  68 +Phase 3 Sweep
  69 +Phase 3 Sweep | Checksum: 121b90616
  70 +
  71 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1362.355 ; gain = 0.000
  72 +INFO: [Opt 31-389] Phase Sweep created 2 cells and removed 0 cells
  73 +
  74 +Phase 4 BUFG optimization
  75 +Phase 4 BUFG optimization | Checksum: 121b90616
  76 +
  77 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1362.355 ; gain = 0.000
  78 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
  79 +
  80 +Phase 5 Shift Register Optimization
  81 +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
  82 +Phase 5 Shift Register Optimization | Checksum: 121b90616
  83 +
  84 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.046 . Memory (MB): peak = 1362.355 ; gain = 0.000
  85 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
  86 +
  87 +Phase 6 Post Processing Netlist
  88 +Phase 6 Post Processing Netlist | Checksum: 121b90616
  89 +
  90 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1362.355 ; gain = 0.000
  91 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
  92 +Opt_design Change Summary
  93 +=========================
  94 +
  95 +
  96 +-------------------------------------------------------------------------------------------------------------------------
  97 +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
  98 +-------------------------------------------------------------------------------------------------------------------------
  99 +| Retarget | 0 | 0 | 0 |
  100 +| Constant propagation | 0 | 0 | 0 |
  101 +| Sweep | 2 | 0 | 0 |
  102 +| BUFG optimization | 0 | 0 | 0 |
  103 +| Shift Register Optimization | 0 | 0 | 0 |
  104 +| Post Processing Netlist | 0 | 0 | 0 |
  105 +-------------------------------------------------------------------------------------------------------------------------
  106 +
  107 +
  108 +
  109 +Starting Connectivity Check Task
  110 +
  111 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1362.355 ; gain = 0.000
  112 +Ending Logic Optimization Task | Checksum: dcf35d24
  113 +
  114 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1362.355 ; gain = 0.000
  115 +
  116 +Starting Power Optimization Task
  117 +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
  118 +Ending Power Optimization Task | Checksum: dcf35d24
  119 +
  120 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1362.355 ; gain = 0.000
  121 +
  122 +Starting Final Cleanup Task
  123 +Ending Final Cleanup Task | Checksum: dcf35d24
  124 +
  125 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1362.355 ; gain = 0.000
  126 +
  127 +Starting Netlist Obfuscation Task
  128 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.355 ; gain = 0.000
  129 +Ending Netlist Obfuscation Task | Checksum: dcf35d24
  130 +
  131 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.355 ; gain = 0.000
  132 +INFO: [Common 17-83] Releasing license: Implementation
  133 +22 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
  134 +opt_design completed successfully
  135 +opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1362.355 ; gain = 696.281
  136 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.355 ; gain = 0.000
  137 +INFO: [Timing 38-480] Writing timing data to binary archive.
  138 +Writing placer database...
  139 +Writing XDEF routing.
  140 +Writing XDEF routing logical nets.
  141 +Writing XDEF routing special nets.
  142 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1362.355 ; gain = 0.000
  143 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_opt.dcp' has been generated.
  144 +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx
  145 +Command: report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx
  146 +INFO: [IP_Flow 19-234] Refreshing IP repositories
  147 +INFO: [IP_Flow 19-1704] No user IP repositories specified
  148 +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'.
  149 +INFO: [DRC 23-27] Running DRC with 2 threads
  150 +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpt.
  151 +report_drc completed successfully
  152 +Command: place_design
  153 +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  154 +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  155 +INFO: [DRC 23-27] Running DRC with 2 threads
  156 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  157 +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  158 +Running DRC as a precondition to command place_design
  159 +INFO: [DRC 23-27] Running DRC with 2 threads
  160 +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[0] expects both input and output buffering but the buffers are incomplete.
  161 +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[1] expects both input and output buffering but the buffers are incomplete.
  162 +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[2] expects both input and output buffering but the buffers are incomplete.
  163 +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[3] expects both input and output buffering but the buffers are incomplete.
  164 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 4 Warnings
  165 +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  166 +
  167 +Starting Placer Task
  168 +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
  169 +
  170 +Phase 1 Placer Initialization
  171 +
  172 +Phase 1.1 Placer Initialization Netlist Sorting
  173 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.355 ; gain = 0.000
  174 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d81a4771
  175 +
  176 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1362.355 ; gain = 0.000
  177 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.355 ; gain = 0.000
  178 +
  179 +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
  180 +WARNING: [Place 30-87] Partially locked IO Bus is found. Following components of the IO Bus AFF are not locked: 'AFF[7]'
  181 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  182 +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 157f6087d
  183 +
  184 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.692 . Memory (MB): peak = 1362.355 ; gain = 0.000
  185 +
  186 +Phase 1.3 Build Placer Netlist Model
  187 +Phase 1.3 Build Placer Netlist Model | Checksum: 23548b804
  188 +
  189 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.729 . Memory (MB): peak = 1362.355 ; gain = 0.000
  190 +
  191 +Phase 1.4 Constrain Clocks/Macros
  192 +Phase 1.4 Constrain Clocks/Macros | Checksum: 23548b804
  193 +
  194 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.733 . Memory (MB): peak = 1362.355 ; gain = 0.000
  195 +Phase 1 Placer Initialization | Checksum: 23548b804
  196 +
  197 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.738 . Memory (MB): peak = 1362.355 ; gain = 0.000
  198 +
  199 +Phase 2 Global Placement
  200 +
  201 +Phase 2.1 Floorplanning
  202 +Phase 2.1 Floorplanning | Checksum: 23548b804
  203 +
  204 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1362.355 ; gain = 0.000
  205 +
  206 +Phase 2.2 Global Placement Core
  207 +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
  208 +Phase 2.2 Global Placement Core | Checksum: 166e98314
  209 +
  210 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000
  211 +Phase 2 Global Placement | Checksum: 166e98314
  212 +
  213 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000
  214 +
  215 +Phase 3 Detail Placement
  216 +
  217 +Phase 3.1 Commit Multi Column Macros
  218 +Phase 3.1 Commit Multi Column Macros | Checksum: 166e98314
  219 +
  220 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000
  221 +
  222 +Phase 3.2 Commit Most Macros & LUTRAMs
  223 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1ab7c764c
  224 +
  225 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000
  226 +
  227 +Phase 3.3 Area Swap Optimization
  228 +Phase 3.3 Area Swap Optimization | Checksum: 1b13b62f3
  229 +
  230 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000
  231 +
  232 +Phase 3.4 Pipeline Register Optimization
  233 +Phase 3.4 Pipeline Register Optimization | Checksum: 1b13b62f3
  234 +
  235 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000
  236 +
  237 +Phase 3.5 Small Shape Detail Placement
  238 +Phase 3.5 Small Shape Detail Placement | Checksum: 2063d6819
  239 +
  240 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000
  241 +
  242 +Phase 3.6 Re-assign LUT pins
  243 +Phase 3.6 Re-assign LUT pins | Checksum: 2063d6819
  244 +
  245 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000
  246 +
  247 +Phase 3.7 Pipeline Register Optimization
  248 +Phase 3.7 Pipeline Register Optimization | Checksum: 2063d6819
  249 +
  250 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000
  251 +Phase 3 Detail Placement | Checksum: 2063d6819
  252 +
  253 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000
  254 +
  255 +Phase 4 Post Placement Optimization and Clean-Up
  256 +
  257 +Phase 4.1 Post Commit Optimization
  258 +Phase 4.1 Post Commit Optimization | Checksum: 2063d6819
  259 +
  260 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000
  261 +
  262 +Phase 4.2 Post Placement Cleanup
  263 +Phase 4.2 Post Placement Cleanup | Checksum: 2063d6819
  264 +
  265 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000
  266 +
  267 +Phase 4.3 Placer Reporting
  268 +Phase 4.3 Placer Reporting | Checksum: 2063d6819
  269 +
  270 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000
  271 +
  272 +Phase 4.4 Final Placement Cleanup
  273 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.355 ; gain = 0.000
  274 +Phase 4.4 Final Placement Cleanup | Checksum: 2063d6819
  275 +
  276 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000
  277 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2063d6819
  278 +
  279 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000
  280 +Ending Placer Task | Checksum: 15bec1324
  281 +
  282 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000
  283 +INFO: [Common 17-83] Releasing license: Implementation
  284 +40 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered.
  285 +place_design completed successfully
  286 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.355 ; gain = 0.000
  287 +INFO: [Timing 38-480] Writing timing data to binary archive.
  288 +Writing placer database...
  289 +Writing XDEF routing.
  290 +Writing XDEF routing logical nets.
  291 +Writing XDEF routing special nets.
  292 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1370.227 ; gain = 7.871
  293 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_placed.dcp' has been generated.
  294 +INFO: [runtcl-4] Executing : report_io -file Afficheur_7SEG_io_placed.rpt
  295 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1370.227 ; gain = 0.000
  296 +INFO: [runtcl-4] Executing : report_utilization -file Afficheur_7SEG_utilization_placed.rpt -pb Afficheur_7SEG_utilization_placed.pb
  297 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file Afficheur_7SEG_control_sets_placed.rpt
  298 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1370.227 ; gain = 0.000
  299 +Command: route_design
  300 +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  301 +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  302 +Running DRC as a precondition to command route_design
  303 +INFO: [DRC 23-27] Running DRC with 2 threads
  304 +WARNING: [DRC PLIO-3] Placement Constraints Check for IO constraints: Partially locked IO Bus is found. Following components of the IO Bus AFF[7:0] are not locked: AFF[7]
  305 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings
  306 +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  307 +
  308 +
  309 +Starting Routing Task
  310 +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
  311 +Checksum: PlaceDB: 9cac4467 ConstDB: 0 ShapeSum: bf3fcebd RouteDB: 0
  312 +
  313 +Phase 1 Build RT Design
  314 +Phase 1 Build RT Design | Checksum: 157fc0746
  315 +
  316 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1464.305 ; gain = 83.031
  317 +Post Restoration Checksum: NetGraph: 81a272f1 NumContArr: d6599455 Constraints: 0 Timing: 0
  318 +
  319 +Phase 2 Router Initialization
  320 +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
  321 +
  322 +Phase 2.1 Fix Topology Constraints
  323 +Phase 2.1 Fix Topology Constraints | Checksum: 157fc0746
  324 +
  325 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1470.320 ; gain = 89.047
  326 +
  327 +Phase 2.2 Pre Route Cleanup
  328 +Phase 2.2 Pre Route Cleanup | Checksum: 157fc0746
  329 +
  330 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1470.320 ; gain = 89.047
  331 + Number of Nodes with overlaps = 0
  332 +Phase 2 Router Initialization | Checksum: 13bb64a85
  333 +
  334 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1473.793 ; gain = 92.520
  335 +
  336 +Router Utilization Summary
  337 + Global Vertical Routing Utilization = 0 %
  338 + Global Horizontal Routing Utilization = 0 %
  339 + Routable Net Status*
  340 + *Does not include unroutable nets such as driverless and loadless.
  341 + Run report_route_status for detailed report.
  342 + Number of Failed Nets = 21
  343 + (Failed Nets is the sum of unrouted and partially routed nets)
  344 + Number of Unrouted Nets = 21
  345 + Number of Partially Routed Nets = 0
  346 + Number of Node Overlaps = 0
  347 +
  348 +
  349 +Phase 3 Initial Routing
  350 +Phase 3 Initial Routing | Checksum: 105a773f9
  351 +
  352 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1473.883 ; gain = 92.609
  353 +
  354 +Phase 4 Rip-up And Reroute
  355 +
  356 +Phase 4.1 Global Iteration 0
  357 + Number of Nodes with overlaps = 0
  358 +Phase 4.1 Global Iteration 0 | Checksum: 15b772385
  359 +
  360 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1473.883 ; gain = 92.609
  361 +Phase 4 Rip-up And Reroute | Checksum: 15b772385
  362 +
  363 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1473.883 ; gain = 92.609
  364 +
  365 +Phase 5 Delay and Skew Optimization
  366 +Phase 5 Delay and Skew Optimization | Checksum: 15b772385
  367 +
  368 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1473.883 ; gain = 92.609
  369 +
  370 +Phase 6 Post Hold Fix
  371 +
  372 +Phase 6.1 Hold Fix Iter
  373 +Phase 6.1 Hold Fix Iter | Checksum: 15b772385
  374 +
  375 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1473.883 ; gain = 92.609
  376 +Phase 6 Post Hold Fix | Checksum: 15b772385
  377 +
  378 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1473.883 ; gain = 92.609
  379 +
  380 +Phase 7 Route finalize
  381 +
  382 +Router Utilization Summary
  383 + Global Vertical Routing Utilization = 0.00829148 %
  384 + Global Horizontal Routing Utilization = 0.00390422 %
  385 + Routable Net Status*
  386 + *Does not include unroutable nets such as driverless and loadless.
  387 + Run report_route_status for detailed report.
  388 + Number of Failed Nets = 0
  389 + (Failed Nets is the sum of unrouted and partially routed nets)
  390 + Number of Unrouted Nets = 0
  391 + Number of Partially Routed Nets = 0
  392 + Number of Node Overlaps = 0
  393 +
  394 +Congestion Report
  395 +North Dir 1x1 Area, Max Cong = 21.6216%, No Congested Regions.
  396 +South Dir 1x1 Area, Max Cong = 9.00901%, No Congested Regions.
  397 +East Dir 1x1 Area, Max Cong = 10.2941%, No Congested Regions.
  398 +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.
  399 +
  400 +------------------------------
  401 +Reporting congestion hotspots
  402 +------------------------------
  403 +Direction: North
  404 +----------------
  405 +Congested clusters found at Level 0
  406 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  407 +Direction: South
  408 +----------------
  409 +Congested clusters found at Level 0
  410 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  411 +Direction: East
  412 +----------------
  413 +Congested clusters found at Level 0
  414 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  415 +Direction: West
  416 +----------------
  417 +Congested clusters found at Level 0
  418 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  419 +
  420 +Phase 7 Route finalize | Checksum: 15b772385
  421 +
  422 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1473.883 ; gain = 92.609
  423 +
  424 +Phase 8 Verifying routed nets
  425 +
  426 + Verification completed successfully
  427 +Phase 8 Verifying routed nets | Checksum: 15b772385
  428 +
  429 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1475.930 ; gain = 94.656
  430 +
  431 +Phase 9 Depositing Routes
  432 +Phase 9 Depositing Routes | Checksum: 144a3b6e0
  433 +
  434 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1475.930 ; gain = 94.656
  435 +INFO: [Route 35-16] Router Completed Successfully
  436 +
  437 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1475.930 ; gain = 94.656
  438 +
  439 +Routing Is Done.
  440 +INFO: [Common 17-83] Releasing license: Implementation
  441 +53 Infos, 11 Warnings, 0 Critical Warnings and 0 Errors encountered.
  442 +route_design completed successfully
  443 +route_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1475.930 ; gain = 105.703
  444 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1475.930 ; gain = 0.000
  445 +INFO: [Timing 38-480] Writing timing data to binary archive.
  446 +Writing placer database...
  447 +Writing XDEF routing.
  448 +Writing XDEF routing logical nets.
  449 +Writing XDEF routing special nets.
  450 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1485.762 ; gain = 9.832
  451 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_routed.dcp' has been generated.
  452 +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx
  453 +Command: report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx
  454 +INFO: [IP_Flow 19-1839] IP Catalog is up to date.
  455 +INFO: [DRC 23-27] Running DRC with 2 threads
  456 +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpt.
  457 +report_drc completed successfully
  458 +INFO: [runtcl-4] Executing : report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx
  459 +Command: report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx
  460 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  461 +INFO: [DRC 23-133] Running Methodology with 2 threads
  462 +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.rpt.
  463 +report_methodology completed successfully
  464 +INFO: [runtcl-4] Executing : report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx
  465 +Command: report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx
  466 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  467 +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
  468 +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
  469 +Running Vector-less Activity Propagation...
  470 +
  471 +Finished Running Vector-less Activity Propagation
  472 +65 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered.
  473 +report_power completed successfully
  474 +INFO: [runtcl-4] Executing : report_route_status -file Afficheur_7SEG_route_status.rpt -pb Afficheur_7SEG_route_status.pb
  475 +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Afficheur_7SEG_timing_summary_routed.rpt -pb Afficheur_7SEG_timing_summary_routed.pb -rpx Afficheur_7SEG_timing_summary_routed.rpx -warn_on_violation
  476 +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
  477 +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
  478 +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
  479 +INFO: [runtcl-4] Executing : report_incremental_reuse -file Afficheur_7SEG_incremental_reuse_routed.rpt
  480 +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
  481 +INFO: [runtcl-4] Executing : report_clock_utilization -file Afficheur_7SEG_clock_utilization_routed.rpt
  482 +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Afficheur_7SEG_bus_skew_routed.rpt -pb Afficheur_7SEG_bus_skew_routed.pb -rpx Afficheur_7SEG_bus_skew_routed.rpx
  483 +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
  484 +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
  485 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 4 14:26:14 2023...
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_5200.backup.vdi 0 → 100755
  Show/Hide comments   View file @231d00d
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  1 +#-----------------------------------------------------------
  2 +# Vivado v2019.1 (64-bit)
  3 +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
  4 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
  5 +# Start of session at: Wed Oct 4 15:11:40 2023
  6 +# Process ID: 5200
  7 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1
  8 +# Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace
  9 +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi
  10 +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou
  11 +#-----------------------------------------------------------
  12 +source Afficheur_7SEG.tcl -notrace
  13 +Command: link_design -top Afficheur_7SEG -part xc7a35tcpg236-1
  14 +Design is defaulting to srcset: sources_1
  15 +Design is defaulting to constrset: constrs_1
  16 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1
  17 +INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement
  18 +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
  19 +INFO: [Project 1-479] Netlist was created with Vivado 2019.1
  20 +INFO: [Project 1-570] Preparing netlist for logic optimization
  21 +Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc]
  22 +Finished Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc]
  23 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  24 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 664.383 ; gain = 0.000
  25 +INFO: [Project 1-111] Unisim Transformation Summary:
  26 +No Unisim elements were transformed.
  27 +
  28 +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  29 +link_design completed successfully
  30 +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 668.453 ; gain = 377.566
  31 +Command: opt_design
  32 +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  33 +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  34 +Running DRC as a precondition to command opt_design
  35 +
  36 +Starting DRC Task
  37 +INFO: [DRC 23-27] Running DRC with 2 threads
  38 +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[0] expects both input and output buffering but the buffers are incomplete.
  39 +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[1] expects both input and output buffering but the buffers are incomplete.
  40 +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[2] expects both input and output buffering but the buffers are incomplete.
  41 +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[3] expects both input and output buffering but the buffers are incomplete.
  42 +INFO: [Project 1-461] DRC finished with 0 Errors, 4 Warnings
  43 +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
  44 +
  45 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.647 . Memory (MB): peak = 685.898 ; gain = 17.445
  46 +
  47 +Starting Cache Timing Information Task
  48 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  49 +Ending Cache Timing Information Task | Checksum: 1725a160a
  50 +
  51 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1199.828 ; gain = 513.930
  52 +
  53 +Starting Logic Optimization Task
  54 +
  55 +Phase 1 Retarget
  56 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  57 +INFO: [Opt 31-49] Retargeted 0 cell(s).
  58 +Phase 1 Retarget | Checksum: 1725a160a
  59 +
  60 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1342.863 ; gain = 0.000
  61 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
  62 +
  63 +Phase 2 Constant propagation
  64 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  65 +Phase 2 Constant propagation | Checksum: 1725a160a
  66 +
  67 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1342.863 ; gain = 0.000
  68 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
  69 +
  70 +Phase 3 Sweep
  71 +Phase 3 Sweep | Checksum: 16697666f
  72 +
  73 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1342.863 ; gain = 0.000
  74 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
  75 +
  76 +Phase 4 BUFG optimization
  77 +Phase 4 BUFG optimization | Checksum: 16697666f
  78 +
  79 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1342.863 ; gain = 0.000
  80 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
  81 +
  82 +Phase 5 Shift Register Optimization
  83 +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
  84 +Phase 5 Shift Register Optimization | Checksum: 16697666f
  85 +
  86 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1342.863 ; gain = 0.000
  87 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
  88 +
  89 +Phase 6 Post Processing Netlist
  90 +Phase 6 Post Processing Netlist | Checksum: 16697666f
  91 +
  92 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1342.863 ; gain = 0.000
  93 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
  94 +Opt_design Change Summary
  95 +=========================
  96 +
  97 +
  98 +-------------------------------------------------------------------------------------------------------------------------
  99 +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
  100 +-------------------------------------------------------------------------------------------------------------------------
  101 +| Retarget | 0 | 0 | 0 |
  102 +| Constant propagation | 0 | 0 | 0 |
  103 +| Sweep | 0 | 0 | 0 |
  104 +| BUFG optimization | 0 | 0 | 0 |
  105 +| Shift Register Optimization | 0 | 0 | 0 |
  106 +| Post Processing Netlist | 0 | 0 | 0 |
  107 +-------------------------------------------------------------------------------------------------------------------------
  108 +
  109 +
  110 +
  111 +Starting Connectivity Check Task
  112 +
  113 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1342.863 ; gain = 0.000
  114 +Ending Logic Optimization Task | Checksum: 13278e9b1
  115 +
  116 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1342.863 ; gain = 0.000
  117 +
  118 +Starting Power Optimization Task
  119 +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
  120 +Ending Power Optimization Task | Checksum: 13278e9b1
  121 +
  122 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1342.863 ; gain = 0.000
  123 +
  124 +Starting Final Cleanup Task
  125 +Ending Final Cleanup Task | Checksum: 13278e9b1
  126 +
  127 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.863 ; gain = 0.000
  128 +
  129 +Starting Netlist Obfuscation Task
  130 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1342.863 ; gain = 0.000
  131 +Ending Netlist Obfuscation Task | Checksum: 13278e9b1
  132 +
  133 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1342.863 ; gain = 0.000
  134 +INFO: [Common 17-83] Releasing license: Implementation
  135 +24 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
  136 +opt_design completed successfully
  137 +opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1342.863 ; gain = 674.410
  138 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.863 ; gain = 0.000
  139 +INFO: [Timing 38-480] Writing timing data to binary archive.
  140 +Writing placer database...
  141 +Writing XDEF routing.
  142 +Writing XDEF routing logical nets.
  143 +Writing XDEF routing special nets.
  144 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1342.863 ; gain = 0.000
  145 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_opt.dcp' has been generated.
  146 +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx
  147 +Command: report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx
  148 +INFO: [IP_Flow 19-234] Refreshing IP repositories
  149 +INFO: [IP_Flow 19-1704] No user IP repositories specified
  150 +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'.
  151 +INFO: [DRC 23-27] Running DRC with 2 threads
  152 +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpt.
  153 +report_drc completed successfully
  154 +Command: place_design
  155 +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  156 +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  157 +INFO: [DRC 23-27] Running DRC with 2 threads
  158 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  159 +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  160 +Running DRC as a precondition to command place_design
  161 +INFO: [DRC 23-27] Running DRC with 2 threads
  162 +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[0] expects both input and output buffering but the buffers are incomplete.
  163 +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[1] expects both input and output buffering but the buffers are incomplete.
  164 +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[2] expects both input and output buffering but the buffers are incomplete.
  165 +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[3] expects both input and output buffering but the buffers are incomplete.
  166 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 4 Warnings
  167 +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  168 +
  169 +Starting Placer Task
  170 +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
  171 +
  172 +Phase 1 Placer Initialization
  173 +
  174 +Phase 1.1 Placer Initialization Netlist Sorting
  175 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.863 ; gain = 0.000
  176 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: ecbe64bb
  177 +
  178 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1342.863 ; gain = 0.000
  179 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.863 ; gain = 0.000
  180 +
  181 +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
  182 +WARNING: [Place 30-87] Partially locked IO Bus is found. Following components of the IO Bus AFF are not locked: 'AFF[7]'
  183 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  184 +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 16c9a25c7
  185 +
  186 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.576 . Memory (MB): peak = 1342.863 ; gain = 0.000
  187 +
  188 +Phase 1.3 Build Placer Netlist Model
  189 +Phase 1.3 Build Placer Netlist Model | Checksum: 1d613607f
  190 +
  191 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.588 . Memory (MB): peak = 1342.863 ; gain = 0.000
  192 +
  193 +Phase 1.4 Constrain Clocks/Macros
  194 +Phase 1.4 Constrain Clocks/Macros | Checksum: 1d613607f
  195 +
  196 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.589 . Memory (MB): peak = 1342.863 ; gain = 0.000
  197 +Phase 1 Placer Initialization | Checksum: 1d613607f
  198 +
  199 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.590 . Memory (MB): peak = 1342.863 ; gain = 0.000
  200 +
  201 +Phase 2 Global Placement
  202 +
  203 +Phase 2.1 Floorplanning
  204 +Phase 2.1 Floorplanning | Checksum: 1d613607f
  205 +
  206 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.592 . Memory (MB): peak = 1342.863 ; gain = 0.000
  207 +
  208 +Phase 2.2 Global Placement Core
  209 +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
  210 +Phase 2.2 Global Placement Core | Checksum: 1ba501753
  211 +
  212 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000
  213 +Phase 2 Global Placement | Checksum: 1ba501753
  214 +
  215 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000
  216 +
  217 +Phase 3 Detail Placement
  218 +
  219 +Phase 3.1 Commit Multi Column Macros
  220 +Phase 3.1 Commit Multi Column Macros | Checksum: 1ba501753
  221 +
  222 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000
  223 +
  224 +Phase 3.2 Commit Most Macros & LUTRAMs
  225 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1e51ebdea
  226 +
  227 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000
  228 +
  229 +Phase 3.3 Area Swap Optimization
  230 +Phase 3.3 Area Swap Optimization | Checksum: 1f2e580a4
  231 +
  232 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000
  233 +
  234 +Phase 3.4 Pipeline Register Optimization
  235 +Phase 3.4 Pipeline Register Optimization | Checksum: 1f2e580a4
  236 +
  237 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000
  238 +
  239 +Phase 3.5 Small Shape Detail Placement
  240 +Phase 3.5 Small Shape Detail Placement | Checksum: 1b679a68b
  241 +
  242 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000
  243 +
  244 +Phase 3.6 Re-assign LUT pins
  245 +Phase 3.6 Re-assign LUT pins | Checksum: 1b679a68b
  246 +
  247 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000
  248 +
  249 +Phase 3.7 Pipeline Register Optimization
  250 +Phase 3.7 Pipeline Register Optimization | Checksum: 1b679a68b
  251 +
  252 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000
  253 +Phase 3 Detail Placement | Checksum: 1b679a68b
  254 +
  255 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000
  256 +
  257 +Phase 4 Post Placement Optimization and Clean-Up
  258 +
  259 +Phase 4.1 Post Commit Optimization
  260 +Phase 4.1 Post Commit Optimization | Checksum: 1b679a68b
  261 +
  262 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000
  263 +
  264 +Phase 4.2 Post Placement Cleanup
  265 +Phase 4.2 Post Placement Cleanup | Checksum: 1b679a68b
  266 +
  267 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000
  268 +
  269 +Phase 4.3 Placer Reporting
  270 +Phase 4.3 Placer Reporting | Checksum: 1b679a68b
  271 +
  272 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000
  273 +
  274 +Phase 4.4 Final Placement Cleanup
  275 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.863 ; gain = 0.000
  276 +Phase 4.4 Final Placement Cleanup | Checksum: 1b679a68b
  277 +
  278 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000
  279 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1b679a68b
  280 +
  281 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000
  282 +Ending Placer Task | Checksum: 1383cb817
  283 +
  284 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000
  285 +INFO: [Common 17-83] Releasing license: Implementation
  286 +42 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered.
  287 +place_design completed successfully
  288 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.863 ; gain = 0.000
  289 +INFO: [Timing 38-480] Writing timing data to binary archive.
  290 +Writing placer database...
  291 +Writing XDEF routing.
  292 +Writing XDEF routing logical nets.
  293 +Writing XDEF routing special nets.
  294 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1353.707 ; gain = 10.844
  295 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_placed.dcp' has been generated.
  296 +INFO: [runtcl-4] Executing : report_io -file Afficheur_7SEG_io_placed.rpt
  297 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1353.707 ; gain = 0.000
  298 +INFO: [runtcl-4] Executing : report_utilization -file Afficheur_7SEG_utilization_placed.rpt -pb Afficheur_7SEG_utilization_placed.pb
  299 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file Afficheur_7SEG_control_sets_placed.rpt
  300 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1353.707 ; gain = 0.000
  301 +Command: route_design
  302 +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  303 +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  304 +Running DRC as a precondition to command route_design
  305 +INFO: [DRC 23-27] Running DRC with 2 threads
  306 +WARNING: [DRC PLIO-3] Placement Constraints Check for IO constraints: Partially locked IO Bus is found. Following components of the IO Bus AFF[7:0] are not locked: AFF[7]
  307 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings
  308 +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  309 +
  310 +
  311 +Starting Routing Task
  312 +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
  313 +Checksum: PlaceDB: 6458cc10 ConstDB: 0 ShapeSum: d3e3ec07 RouteDB: 0
  314 +
  315 +Phase 1 Build RT Design
  316 +Phase 1 Build RT Design | Checksum: c1d7b88d
  317 +
  318 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1446.727 ; gain = 79.938
  319 +Post Restoration Checksum: NetGraph: 57081e63 NumContArr: 6acf9a2a Constraints: 0 Timing: 0
  320 +
  321 +Phase 2 Router Initialization
  322 +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
  323 +
  324 +Phase 2.1 Fix Topology Constraints
  325 +Phase 2.1 Fix Topology Constraints | Checksum: c1d7b88d
  326 +
  327 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1452.738 ; gain = 85.949
  328 +
  329 +Phase 2.2 Pre Route Cleanup
  330 +Phase 2.2 Pre Route Cleanup | Checksum: c1d7b88d
  331 +
  332 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1452.738 ; gain = 85.949
  333 + Number of Nodes with overlaps = 0
  334 +Phase 2 Router Initialization | Checksum: 16c8cce5e
  335 +
  336 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1456.137 ; gain = 89.348
  337 +
  338 +Router Utilization Summary
  339 + Global Vertical Routing Utilization = 0 %
  340 + Global Horizontal Routing Utilization = 0 %
  341 + Routable Net Status*
  342 + *Does not include unroutable nets such as driverless and loadless.
  343 + Run report_route_status for detailed report.
  344 + Number of Failed Nets = 32
  345 + (Failed Nets is the sum of unrouted and partially routed nets)
  346 + Number of Unrouted Nets = 32
  347 + Number of Partially Routed Nets = 0
  348 + Number of Node Overlaps = 0
  349 +
  350 +
  351 +Phase 3 Initial Routing
  352 + Number of Nodes with overlaps = 0
  353 +Phase 3 Initial Routing | Checksum: 1bf565ff7
  354 +
  355 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.086 ; gain = 91.297
  356 +
  357 +Phase 4 Rip-up And Reroute
  358 +
  359 +Phase 4.1 Global Iteration 0
  360 +Phase 4.1 Global Iteration 0 | Checksum: 1bf565ff7
  361 +
  362 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.086 ; gain = 91.297
  363 +Phase 4 Rip-up And Reroute | Checksum: 1bf565ff7
  364 +
  365 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.086 ; gain = 91.297
  366 +
  367 +Phase 5 Delay and Skew Optimization
  368 +Phase 5 Delay and Skew Optimization | Checksum: 1bf565ff7
  369 +
  370 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.086 ; gain = 91.297
  371 +
  372 +Phase 6 Post Hold Fix
  373 +
  374 +Phase 6.1 Hold Fix Iter
  375 +Phase 6.1 Hold Fix Iter | Checksum: 1bf565ff7
  376 +
  377 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.086 ; gain = 91.297
  378 +Phase 6 Post Hold Fix | Checksum: 1bf565ff7
  379 +
  380 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.086 ; gain = 91.297
  381 +
  382 +Phase 7 Route finalize
  383 +
  384 +Router Utilization Summary
  385 + Global Vertical Routing Utilization = 0.0126764 %
  386 + Global Horizontal Routing Utilization = 0.00221239 %
  387 + Routable Net Status*
  388 + *Does not include unroutable nets such as driverless and loadless.
  389 + Run report_route_status for detailed report.
  390 + Number of Failed Nets = 0
  391 + (Failed Nets is the sum of unrouted and partially routed nets)
  392 + Number of Unrouted Nets = 0
  393 + Number of Partially Routed Nets = 0
  394 + Number of Node Overlaps = 0
  395 +
  396 +Congestion Report
  397 +North Dir 1x1 Area, Max Cong = 12.6126%, No Congested Regions.
  398 +South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions.
  399 +East Dir 1x1 Area, Max Cong = 5.88235%, No Congested Regions.
  400 +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.
  401 +
  402 +------------------------------
  403 +Reporting congestion hotspots
  404 +------------------------------
  405 +Direction: North
  406 +----------------
  407 +Congested clusters found at Level 0
  408 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  409 +Direction: South
  410 +----------------
  411 +Congested clusters found at Level 0
  412 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  413 +Direction: East
  414 +----------------
  415 +Congested clusters found at Level 0
  416 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  417 +Direction: West
  418 +----------------
  419 +Congested clusters found at Level 0
  420 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  421 +
  422 +Phase 7 Route finalize | Checksum: 1bf565ff7
  423 +
  424 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.086 ; gain = 91.297
  425 +
  426 +Phase 8 Verifying routed nets
  427 +
  428 + Verification completed successfully
  429 +Phase 8 Verifying routed nets | Checksum: 1bf565ff7
  430 +
  431 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1460.137 ; gain = 93.348
  432 +
  433 +Phase 9 Depositing Routes
  434 +Phase 9 Depositing Routes | Checksum: 14c66ac04
  435 +
  436 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1460.137 ; gain = 93.348
  437 +INFO: [Route 35-16] Router Completed Successfully
  438 +
  439 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1460.137 ; gain = 93.348
  440 +
  441 +Routing Is Done.
  442 +INFO: [Common 17-83] Releasing license: Implementation
  443 +55 Infos, 11 Warnings, 0 Critical Warnings and 0 Errors encountered.
  444 +route_design completed successfully
  445 +route_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1460.137 ; gain = 106.430
  446 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.137 ; gain = 0.000
  447 +INFO: [Timing 38-480] Writing timing data to binary archive.
  448 +Writing placer database...
  449 +Writing XDEF routing.
  450 +Writing XDEF routing logical nets.
  451 +Writing XDEF routing special nets.
  452 +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1469.973 ; gain = 9.836
  453 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_routed.dcp' has been generated.
  454 +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx
  455 +Command: report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx
  456 +INFO: [IP_Flow 19-1839] IP Catalog is up to date.
  457 +INFO: [DRC 23-27] Running DRC with 2 threads
  458 +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpt.
  459 +report_drc completed successfully
  460 +INFO: [runtcl-4] Executing : report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx
  461 +Command: report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx
  462 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  463 +INFO: [DRC 23-133] Running Methodology with 2 threads
  464 +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.rpt.
  465 +report_methodology completed successfully
  466 +INFO: [runtcl-4] Executing : report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx
  467 +Command: report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx
  468 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  469 +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
  470 +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
  471 +Running Vector-less Activity Propagation...
  472 +
  473 +Finished Running Vector-less Activity Propagation
  474 +67 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered.
  475 +report_power completed successfully
  476 +INFO: [runtcl-4] Executing : report_route_status -file Afficheur_7SEG_route_status.rpt -pb Afficheur_7SEG_route_status.pb
  477 +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Afficheur_7SEG_timing_summary_routed.rpt -pb Afficheur_7SEG_timing_summary_routed.pb -rpx Afficheur_7SEG_timing_summary_routed.rpx -warn_on_violation
  478 +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
  479 +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
  480 +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
  481 +INFO: [runtcl-4] Executing : report_incremental_reuse -file Afficheur_7SEG_incremental_reuse_routed.rpt
  482 +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
  483 +INFO: [runtcl-4] Executing : report_clock_utilization -file Afficheur_7SEG_clock_utilization_routed.rpt
  484 +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Afficheur_7SEG_bus_skew_routed.rpt -pb Afficheur_7SEG_bus_skew_routed.pb -rpx Afficheur_7SEG_bus_skew_routed.rpx
  485 +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
  486 +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
  487 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 4 15:12:29 2023...
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_bus_skew_routed.pb 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_bus_skew_routed.rpt
@@ -0,0 +1,15 @@ @@ -0,0 +1,15 @@
  1 +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  2 +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  3 +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
  4 +| Date : Wed Oct 4 15:36:05 2023
  5 +| Host : WIN10-TP running 64-bit major release (build 9200)
  6 +| Command : report_bus_skew -warn_on_violation -file Afficheur_7SEG_bus_skew_routed.rpt -pb Afficheur_7SEG_bus_skew_routed.pb -rpx Afficheur_7SEG_bus_skew_routed.rpx
  7 +| Design : Afficheur_7SEG
  8 +| Device : 7a35t-cpg236
  9 +| Speed File : -1 PRODUCTION 1.23 2018-06-13
  10 +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  11 +
  12 +Bus Skew Report
  13 +
  14 +No bus skew constraints
  15 +
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_bus_skew_routed.rpx 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_clock_utilization_routed.rpt
@@ -0,0 +1,146 @@ @@ -0,0 +1,146 @@
  1 +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  2 +--------------------------------------------------------------------------------------------
  3 +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
  4 +| Date : Wed Oct 4 15:36:05 2023
  5 +| Host : WIN10-TP running 64-bit major release (build 9200)
  6 +| Command : report_clock_utilization -file Afficheur_7SEG_clock_utilization_routed.rpt
  7 +| Design : Afficheur_7SEG
  8 +| Device : 7a35t-cpg236
  9 +| Speed File : -1 PRODUCTION 1.23 2018-06-13
  10 +| Design State : Routed
  11 +--------------------------------------------------------------------------------------------
  12 +
  13 +Clock Utilization Report
  14 +
  15 +Table of Contents
  16 +-----------------
  17 +1. Clock Primitive Utilization
  18 +2. Global Clock Resources
  19 +3. Global Clock Source Details
  20 +4. Clock Regions: Key Resource Utilization
  21 +5. Clock Regions : Global Clock Summary
  22 +6. Device Cell Placement Summary for Global Clock g0
  23 +7. Clock Region Cell Placement per Global Clock: Region X0Y0
  24 +
  25 +1. Clock Primitive Utilization
  26 +------------------------------
  27 +
  28 ++----------+------+-----------+-----+--------------+--------+
  29 +| Type | Used | Available | LOC | Clock Region | Pblock |
  30 ++----------+------+-----------+-----+--------------+--------+
  31 +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 |
  32 +| BUFH | 0 | 72 | 0 | 0 | 0 |
  33 +| BUFIO | 0 | 20 | 0 | 0 | 0 |
  34 +| BUFMR | 0 | 10 | 0 | 0 | 0 |
  35 +| BUFR | 0 | 20 | 0 | 0 | 0 |
  36 +| MMCM | 0 | 5 | 0 | 0 | 0 |
  37 +| PLL | 0 | 5 | 0 | 0 | 0 |
  38 ++----------+------+-----------+-----+--------------+--------+
  39 +
  40 +
  41 +2. Global Clock Resources
  42 +-------------------------
  43 +
  44 ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+--------------------------+-------------------+
  45 +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
  46 ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+--------------------------+-------------------+
  47 +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 20 | 0 | | | Clk_sys_IBUF_BUFG_inst/O | Clk_sys_IBUF_BUFG |
  48 ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+--------------------------+-------------------+
  49 +* Clock Loads column represents the clock pin loads (pin count)
  50 +** Non-Clock Loads column represents the non-clock pin loads (pin count)
  51 +
  52 +
  53 +3. Global Clock Source Details
  54 +------------------------------
  55 +
  56 ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+---------------------+--------------+
  57 +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
  58 ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+---------------------+--------------+
  59 +| src0 | g0 | IBUF/O | IOB_X1Y26 | IOB_X1Y26 | X1Y0 | 1 | 0 | | | Clk_sys_IBUF_inst/O | Clk_sys_IBUF |
  60 ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+---------------------+--------------+
  61 +* Clock Loads column represents the clock pin loads (pin count)
  62 +** Non-Clock Loads column represents the non-clock pin loads (pin count)
  63 +
  64 +
  65 +4. Clock Regions: Key Resource Utilization
  66 +------------------------------------------
  67 +
  68 ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
  69 +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
  70 ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
  71 +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
  72 ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
  73 +| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 20 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
  74 +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
  75 +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
  76 +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
  77 +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
  78 +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 |
  79 ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
  80 +* Global Clock column represents track count; while other columns represents cell counts
  81 +
  82 +
  83 +5. Clock Regions : Global Clock Summary
  84 +---------------------------------------
  85 +
  86 +All Modules
  87 ++----+----+----+
  88 +| | X0 | X1 |
  89 ++----+----+----+
  90 +| Y2 | 0 | 0 |
  91 +| Y1 | 0 | 0 |
  92 +| Y0 | 1 | 0 |
  93 ++----+----+----+
  94 +
  95 +
  96 +6. Device Cell Placement Summary for Global Clock g0
  97 +----------------------------------------------------
  98 +
  99 ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------+
  100 +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
  101 ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------+
  102 +| g0 | BUFG/O | n/a | | | | 20 | 0 | 0 | 0 | Clk_sys_IBUF_BUFG |
  103 ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------+
  104 +* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
  105 +** IO Loads column represents load cell count of IO types
  106 +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
  107 +**** GT Loads column represents load cell count of GT types
  108 +
  109 +
  110 ++----+-----+----+
  111 +| | X0 | X1 |
  112 ++----+-----+----+
  113 +| Y2 | 0 | 0 |
  114 +| Y1 | 0 | 0 |
  115 +| Y0 | 20 | 0 |
  116 ++----+-----+----+
  117 +
  118 +
  119 +7. Clock Region Cell Placement per Global Clock: Region X0Y0
  120 +------------------------------------------------------------
  121 +
  122 ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+
  123 +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
  124 ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+
  125 +| g0 | n/a | BUFG/O | None | 20 | 0 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Clk_sys_IBUF_BUFG |
  126 ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+
  127 +* Clock Loads column represents the clock pin loads (pin count)
  128 +** Non-Clock Loads column represents the non-clock pin loads (pin count)
  129 +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
  130 +
  131 +
  132 +
  133 +# Location of BUFG Primitives
  134 +set_property LOC BUFGCTRL_X0Y0 [get_cells Clk_sys_IBUF_BUFG_inst]
  135 +
  136 +# Location of IO Primitives which is load of clock spine
  137 +
  138 +# Location of clock ports
  139 +set_property LOC IOB_X1Y26 [get_ports Clk_sys]
  140 +
  141 +# Clock net "Clk_sys_IBUF_BUFG" driven by instance "Clk_sys_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0"
  142 +#startgroup
  143 +create_pblock {CLKAG_Clk_sys_IBUF_BUFG}
  144 +add_cells_to_pblock [get_pblocks {CLKAG_Clk_sys_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="Clk_sys_IBUF_BUFG"}]]]
  145 +resize_pblock [get_pblocks {CLKAG_Clk_sys_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0}
  146 +#endgroup
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_control_sets_placed.rpt 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_control_sets_placed.rpt
@@ -0,0 +1,79 @@ @@ -0,0 +1,79 @@
  1 +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  2 +-------------------------------------------------------------------------------------------
  3 +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
  4 +| Date : Wed Oct 4 15:35:41 2023
  5 +| Host : WIN10-TP running 64-bit major release (build 9200)
  6 +| Command : report_control_sets -verbose -file Afficheur_7SEG_control_sets_placed.rpt
  7 +| Design : Afficheur_7SEG
  8 +| Device : xc7a35t
  9 +-------------------------------------------------------------------------------------------
  10 +
  11 +Control Set Information
  12 +
  13 +Table of Contents
  14 +-----------------
  15 +1. Summary
  16 +2. Histogram
  17 +3. Flip-Flop Distribution
  18 +4. Detailed Control Set Information
  19 +
  20 +1. Summary
  21 +----------
  22 +
  23 ++----------------------------------------------------------+-------+
  24 +| Status | Count |
  25 ++----------------------------------------------------------+-------+
  26 +| Total control sets | 1 |
  27 +| Minimum number of control sets | 1 |
  28 +| Addition due to synthesis replication | 0 |
  29 +| Addition due to physical synthesis replication | 0 |
  30 +| Unused register locations in slices containing registers | 4 |
  31 ++----------------------------------------------------------+-------+
  32 +* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
  33 +** Run report_qor_suggestions for automated merging and remapping suggestions
  34 +
  35 +
  36 +2. Histogram
  37 +------------
  38 +
  39 ++--------------------+-------+
  40 +| Fanout | Count |
  41 ++--------------------+-------+
  42 +| Total control sets | 1 |
  43 +| >= 0 to < 4 | 0 |
  44 +| >= 4 to < 6 | 0 |
  45 +| >= 6 to < 8 | 0 |
  46 +| >= 8 to < 10 | 0 |
  47 +| >= 10 to < 12 | 0 |
  48 +| >= 12 to < 14 | 0 |
  49 +| >= 14 to < 16 | 0 |
  50 +| >= 16 | 1 |
  51 ++--------------------+-------+
  52 +* Control sets can be remapped at either synth_design or opt_design
  53 +
  54 +
  55 +3. Flip-Flop Distribution
  56 +-------------------------
  57 +
  58 ++--------------+-----------------------+------------------------+-----------------+--------------+
  59 +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
  60 ++--------------+-----------------------+------------------------+-----------------+--------------+
  61 +| No | No | No | 0 | 0 |
  62 +| No | No | Yes | 20 | 5 |
  63 +| No | Yes | No | 0 | 0 |
  64 +| Yes | No | No | 0 | 0 |
  65 +| Yes | No | Yes | 0 | 0 |
  66 +| Yes | Yes | No | 0 | 0 |
  67 ++--------------+-----------------------+------------------------+-----------------+--------------+
  68 +
  69 +
  70 +4. Detailed Control Set Information
  71 +-----------------------------------
  72 +
  73 ++--------------------+---------------+------------------+------------------+----------------+
  74 +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
  75 ++--------------------+---------------+------------------+------------------+----------------+
  76 +| Clk_sys_IBUF_BUFG | | reset_IBUF | 5 | 20 |
  77 ++--------------------+---------------+------------------+------------------+----------------+
  78 +
  79 +
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.pb 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpt
@@ -0,0 +1,35 @@ @@ -0,0 +1,35 @@
  1 +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  2 +---------------------------------------------------------------------------------------------------------------------------------
  3 +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
  4 +| Date : Wed Oct 4 15:35:39 2023
  5 +| Host : WIN10-TP running 64-bit major release (build 9200)
  6 +| Command : report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx
  7 +| Design : Afficheur_7SEG
  8 +| Device : xc7a35tcpg236-1
  9 +| Speed File : -1
  10 +| Design State : Synthesized
  11 +---------------------------------------------------------------------------------------------------------------------------------
  12 +
  13 +Report DRC
  14 +
  15 +Table of Contents
  16 +-----------------
  17 +1. REPORT SUMMARY
  18 +2. REPORT DETAILS
  19 +
  20 +1. REPORT SUMMARY
  21 +-----------------
  22 + Netlist: netlist
  23 + Floorplan: design_1
  24 + Design limits: <entire design considered>
  25 + Ruledeck: default
  26 + Max violations: <unlimited>
  27 + Violations found: 0
  28 ++------+----------+-------------+------------+
  29 +| Rule | Severity | Description | Violations |
  30 ++------+----------+-------------+------------+
  31 ++------+----------+-------------+------------+
  32 +
  33 +2. REPORT DETAILS
  34 +-----------------
  35 +
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpx 0 → 100755
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Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.pb 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpt
@@ -0,0 +1,35 @@ @@ -0,0 +1,35 @@
  1 +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  2 +------------------------------------------------------------------------------------------------------------------------------------
  3 +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
  4 +| Date : Wed Oct 4 15:36:04 2023
  5 +| Host : WIN10-TP running 64-bit major release (build 9200)
  6 +| Command : report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx
  7 +| Design : Afficheur_7SEG
  8 +| Device : xc7a35tcpg236-1
  9 +| Speed File : -1
  10 +| Design State : Fully Routed
  11 +------------------------------------------------------------------------------------------------------------------------------------
  12 +
  13 +Report DRC
  14 +
  15 +Table of Contents
  16 +-----------------
  17 +1. REPORT SUMMARY
  18 +2. REPORT DETAILS
  19 +
  20 +1. REPORT SUMMARY
  21 +-----------------
  22 + Netlist: netlist
  23 + Floorplan: design_1
  24 + Design limits: <entire design considered>
  25 + Ruledeck: default
  26 + Max violations: <unlimited>
  27 + Violations found: 0
  28 ++------+----------+-------------+------------+
  29 +| Rule | Severity | Description | Violations |
  30 ++------+----------+-------------+------------+
  31 ++------+----------+-------------+------------+
  32 +
  33 +2. REPORT DETAILS
  34 +-----------------
  35 +
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpx 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_io_placed.rpt
@@ -0,0 +1,280 @@ @@ -0,0 +1,280 @@
  1 +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  2 +-------------------------------------------------------------------------------------------------
  3 +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
  4 +| Date : Wed Oct 4 15:35:41 2023
  5 +| Host : WIN10-TP running 64-bit major release (build 9200)
  6 +| Command : report_io -file Afficheur_7SEG_io_placed.rpt
  7 +| Design : Afficheur_7SEG
  8 +| Device : xc7a35t
  9 +| Speed File : -1
  10 +| Package : cpg236
  11 +| Package Version : FINAL 2014-02-19
  12 +| Package Pin Delay Version : VERS. 2.0 2014-02-19
  13 +-------------------------------------------------------------------------------------------------
  14 +
  15 +IO Information
  16 +
  17 +Table of Contents
  18 +-----------------
  19 +1. Summary
  20 +2. IO Assignments by Package Pin
  21 +
  22 +1. Summary
  23 +----------
  24 +
  25 ++---------------+
  26 +| Total User IO |
  27 ++---------------+
  28 +| 13 |
  29 ++---------------+
  30 +
  31 +
  32 +2. IO Assignments by Package Pin
  33 +--------------------------------
  34 +
  35 ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
  36 +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
  37 ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
  38 +| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  39 +| A2 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | |
  40 +| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  41 +| A4 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | |
  42 +| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  43 +| A6 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | |
  44 +| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  45 +| A8 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | |
  46 +| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  47 +| A10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | |
  48 +| A11 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
  49 +| A12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
  50 +| A13 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
  51 +| A14 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
  52 +| A15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
  53 +| A16 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
  54 +| A17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
  55 +| A18 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
  56 +| A19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  57 +| B1 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
  58 +| B2 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | |
  59 +| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  60 +| B4 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | |
  61 +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  62 +| B6 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | |
  63 +| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  64 +| B8 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | |
  65 +| B9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  66 +| B10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | |
  67 +| B11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
  68 +| B12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
  69 +| B13 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
  70 +| B14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  71 +| B15 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
  72 +| B16 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
  73 +| B17 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
  74 +| B18 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
  75 +| B19 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
  76 +| C1 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
  77 +| C2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  78 +| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  79 +| C4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  80 +| C5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
  81 +| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  82 +| C7 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | |
  83 +| C8 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
  84 +| C9 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
  85 +| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  86 +| C11 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
  87 +| C12 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
  88 +| C13 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
  89 +| C14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
  90 +| C15 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
  91 +| C16 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
  92 +| C17 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
  93 +| C18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
  94 +| C19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  95 +| D1 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | |
  96 +| D2 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | |
  97 +| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  98 +| D17 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
  99 +| D18 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
  100 +| D19 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
  101 +| E1 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
  102 +| E2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
  103 +| E3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  104 +| E17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  105 +| E18 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
  106 +| E19 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
  107 +| F1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  108 +| F2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  109 +| F3 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
  110 +| F17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
  111 +| F18 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
  112 +| F19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  113 +| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  114 +| G2 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | |
  115 +| G3 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | |
  116 +| G7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
  117 +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  118 +| G9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
  119 +| G10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
  120 +| G11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  121 +| G12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | |
  122 +| G13 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
  123 +| G17 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
  124 +| G18 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
  125 +| G19 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
  126 +| H1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
  127 +| H2 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
  128 +| H3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
  129 +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  130 +| H8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  131 +| H9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
  132 +| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
  133 +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  134 +| H12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  135 +| H13 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
  136 +| H17 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
  137 +| H18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  138 +| H19 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
  139 +| J1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
  140 +| J2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
  141 +| J3 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
  142 +| J7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
  143 +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  144 +| J9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  145 +| J10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
  146 +| J11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  147 +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  148 +| J13 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
  149 +| J17 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | |
  150 +| J18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
  151 +| J19 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
  152 +| K1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
  153 +| K2 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
  154 +| K3 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
  155 +| K7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
  156 +| K8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  157 +| K12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
  158 +| K13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
  159 +| K17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
  160 +| K18 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
  161 +| K19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
  162 +| L1 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
  163 +| L2 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
  164 +| L3 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
  165 +| L7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
  166 +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  167 +| L9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  168 +| L10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
  169 +| L11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  170 +| L12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
  171 +| L13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
  172 +| L17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
  173 +| L18 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | |
  174 +| L19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  175 +| M1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
  176 +| M2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
  177 +| M3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
  178 +| M7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
  179 +| M8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
  180 +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  181 +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
  182 +| M11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
  183 +| M12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
  184 +| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  185 +| M17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
  186 +| M18 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
  187 +| M19 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
  188 +| N1 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
  189 +| N2 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
  190 +| N3 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
  191 +| N7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
  192 +| N8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
  193 +| N9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  194 +| N10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
  195 +| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
  196 +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  197 +| N13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  198 +| N17 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
  199 +| N18 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
  200 +| N19 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
  201 +| P1 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
  202 +| P2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  203 +| P3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
  204 +| P17 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
  205 +| P18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
  206 +| P19 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
  207 +| R1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
  208 +| R2 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
  209 +| R3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
  210 +| R17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
  211 +| R18 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
  212 +| R19 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | |
  213 +| T1 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
  214 +| T2 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
  215 +| T3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
  216 +| T17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | |
  217 +| T18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | |
  218 +| T19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  219 +| U1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
  220 +| U2 | AN[0] | High Range | IO_L9N_T1_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
  221 +| U3 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
  222 +| U4 | AN[1] | High Range | IO_L11P_T1_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
  223 +| U5 | AFF[4] | High Range | IO_L16P_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
  224 +| U6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  225 +| U7 | AFF[6] | High Range | IO_L19P_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
  226 +| U8 | AFF[2] | High Range | IO_L14P_T2_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
  227 +| U9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  228 +| U10 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
  229 +| U11 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
  230 +| U12 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
  231 +| U13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
  232 +| U14 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
  233 +| U15 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | |
  234 +| U16 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | |
  235 +| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
  236 +| U18 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | |
  237 +| U19 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | |
  238 +| V1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
  239 +| V2 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
  240 +| V3 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
  241 +| V4 | AN[2] | High Range | IO_L11N_T1_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
  242 +| V5 | AFF[5] | High Range | IO_L16N_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
  243 +| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
  244 +| V7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
  245 +| V8 | AFF[3] | High Range | IO_L14N_T2_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
  246 +| V9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | |
  247 +| V10 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
  248 +| V11 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | | | |
  249 +| V12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
  250 +| V13 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | |
  251 +| V14 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | |
  252 +| V15 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
  253 +| V16 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
  254 +| V17 | reset | High Range | IO_L19N_T3_A09_D25_VREF_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
  255 +| V18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  256 +| V19 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | |
  257 +| W1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  258 +| W2 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
  259 +| W3 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
  260 +| W4 | AN[3] | High Range | IO_L12N_T1_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
  261 +| W5 | Clk_sys | High Range | IO_L12P_T1_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
  262 +| W6 | AFF[1] | High Range | IO_L13N_T2_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
  263 +| W7 | AFF[0] | High Range | IO_L13P_T2_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
  264 +| W8 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
  265 +| W9 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
  266 +| W10 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
  267 +| W11 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
  268 +| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
  269 +| W13 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | |
  270 +| W14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | |
  271 +| W15 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
  272 +| W16 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | |
  273 +| W17 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | |
  274 +| W18 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | |
  275 +| W19 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
  276 ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
  277 +* Default value
  278 +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
  279 +
  280 +
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.rpt
@@ -0,0 +1,135 @@ @@ -0,0 +1,135 @@
  1 +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  2 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  3 +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
  4 +| Date : Wed Oct 4 15:36:04 2023
  5 +| Host : WIN10-TP running 64-bit major release (build 9200)
  6 +| Command : report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx
  7 +| Design : Afficheur_7SEG
  8 +| Device : xc7a35tcpg236-1
  9 +| Speed File : -1
  10 +| Design State : Fully Routed
  11 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  12 +
  13 +Report Methodology
  14 +
  15 +Table of Contents
  16 +-----------------
  17 +1. REPORT SUMMARY
  18 +2. REPORT DETAILS
  19 +
  20 +1. REPORT SUMMARY
  21 +-----------------
  22 + Netlist: netlist
  23 + Floorplan: design_1
  24 + Design limits: <entire design considered>
  25 + Max violations: <unlimited>
  26 + Violations found: 20
  27 ++-----------+------------------+-----------------------------+------------+
  28 +| Rule | Severity | Description | Violations |
  29 ++-----------+------------------+-----------------------------+------------+
  30 +| TIMING-17 | Critical Warning | Non-clocked sequential cell | 20 |
  31 ++-----------+------------------+-----------------------------+------------+
  32 +
  33 +2. REPORT DETAILS
  34 +-----------------
  35 +TIMING-17#1 Critical Warning
  36 +Non-clocked sequential cell
  37 +The clock pin refresh_counter_reg[0]/C is not reached by a timing clock
  38 +Related violations: <none>
  39 +
  40 +TIMING-17#2 Critical Warning
  41 +Non-clocked sequential cell
  42 +The clock pin refresh_counter_reg[10]/C is not reached by a timing clock
  43 +Related violations: <none>
  44 +
  45 +TIMING-17#3 Critical Warning
  46 +Non-clocked sequential cell
  47 +The clock pin refresh_counter_reg[11]/C is not reached by a timing clock
  48 +Related violations: <none>
  49 +
  50 +TIMING-17#4 Critical Warning
  51 +Non-clocked sequential cell
  52 +The clock pin refresh_counter_reg[12]/C is not reached by a timing clock
  53 +Related violations: <none>
  54 +
  55 +TIMING-17#5 Critical Warning
  56 +Non-clocked sequential cell
  57 +The clock pin refresh_counter_reg[13]/C is not reached by a timing clock
  58 +Related violations: <none>
  59 +
  60 +TIMING-17#6 Critical Warning
  61 +Non-clocked sequential cell
  62 +The clock pin refresh_counter_reg[14]/C is not reached by a timing clock
  63 +Related violations: <none>
  64 +
  65 +TIMING-17#7 Critical Warning
  66 +Non-clocked sequential cell
  67 +The clock pin refresh_counter_reg[15]/C is not reached by a timing clock
  68 +Related violations: <none>
  69 +
  70 +TIMING-17#8 Critical Warning
  71 +Non-clocked sequential cell
  72 +The clock pin refresh_counter_reg[16]/C is not reached by a timing clock
  73 +Related violations: <none>
  74 +
  75 +TIMING-17#9 Critical Warning
  76 +Non-clocked sequential cell
  77 +The clock pin refresh_counter_reg[17]/C is not reached by a timing clock
  78 +Related violations: <none>
  79 +
  80 +TIMING-17#10 Critical Warning
  81 +Non-clocked sequential cell
  82 +The clock pin refresh_counter_reg[18]/C is not reached by a timing clock
  83 +Related violations: <none>
  84 +
  85 +TIMING-17#11 Critical Warning
  86 +Non-clocked sequential cell
  87 +The clock pin refresh_counter_reg[19]/C is not reached by a timing clock
  88 +Related violations: <none>
  89 +
  90 +TIMING-17#12 Critical Warning
  91 +Non-clocked sequential cell
  92 +The clock pin refresh_counter_reg[1]/C is not reached by a timing clock
  93 +Related violations: <none>
  94 +
  95 +TIMING-17#13 Critical Warning
  96 +Non-clocked sequential cell
  97 +The clock pin refresh_counter_reg[2]/C is not reached by a timing clock
  98 +Related violations: <none>
  99 +
  100 +TIMING-17#14 Critical Warning
  101 +Non-clocked sequential cell
  102 +The clock pin refresh_counter_reg[3]/C is not reached by a timing clock
  103 +Related violations: <none>
  104 +
  105 +TIMING-17#15 Critical Warning
  106 +Non-clocked sequential cell
  107 +The clock pin refresh_counter_reg[4]/C is not reached by a timing clock
  108 +Related violations: <none>
  109 +
  110 +TIMING-17#16 Critical Warning
  111 +Non-clocked sequential cell
  112 +The clock pin refresh_counter_reg[5]/C is not reached by a timing clock
  113 +Related violations: <none>
  114 +
  115 +TIMING-17#17 Critical Warning
  116 +Non-clocked sequential cell
  117 +The clock pin refresh_counter_reg[6]/C is not reached by a timing clock
  118 +Related violations: <none>
  119 +
  120 +TIMING-17#18 Critical Warning
  121 +Non-clocked sequential cell
  122 +The clock pin refresh_counter_reg[7]/C is not reached by a timing clock
  123 +Related violations: <none>
  124 +
  125 +TIMING-17#19 Critical Warning
  126 +Non-clocked sequential cell
  127 +The clock pin refresh_counter_reg[8]/C is not reached by a timing clock
  128 +Related violations: <none>
  129 +
  130 +TIMING-17#20 Critical Warning
  131 +Non-clocked sequential cell
  132 +The clock pin refresh_counter_reg[9]/C is not reached by a timing clock
  133 +Related violations: <none>
  134 +
  135 +
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_power_routed.rpt
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  1 +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  2 +----------------------------------------------------------------------------------------------------------------------------------------------------------------
  3 +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
  4 +| Date : Wed Oct 4 15:36:05 2023
  5 +| Host : WIN10-TP running 64-bit major release (build 9200)
  6 +| Command : report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx
  7 +| Design : Afficheur_7SEG
  8 +| Device : xc7a35tcpg236-1
  9 +| Design State : routed
  10 +| Grade : commercial
  11 +| Process : typical
  12 +| Characterization : Production
  13 +----------------------------------------------------------------------------------------------------------------------------------------------------------------
  14 +
  15 +Power Report
  16 +
  17 +Table of Contents
  18 +-----------------
  19 +1. Summary
  20 +1.1 On-Chip Components
  21 +1.2 Power Supply Summary
  22 +1.3 Confidence Level
  23 +2. Settings
  24 +2.1 Environment
  25 +2.2 Clock Constraints
  26 +3. Detailed Reports
  27 +3.1 By Hierarchy
  28 +
  29 +1. Summary
  30 +----------
  31 +
  32 ++--------------------------+--------------+
  33 +| Total On-Chip Power (W) | 8.293 |
  34 +| Design Power Budget (W) | Unspecified* |
  35 +| Power Budget Margin (W) | NA |
  36 +| Dynamic (W) | 8.176 |
  37 +| Device Static (W) | 0.117 |
  38 +| Effective TJA (C/W) | 5.0 |
  39 +| Max Ambient (C) | 43.5 |
  40 +| Junction Temperature (C) | 66.5 |
  41 +| Confidence Level | Low |
  42 +| Setting File | --- |
  43 +| Simulation Activity File | --- |
  44 +| Design Nets Matched | NA |
  45 ++--------------------------+--------------+
  46 +* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
  47 +
  48 +
  49 +1.1 On-Chip Components
  50 +----------------------
  51 +
  52 ++----------------+-----------+----------+-----------+-----------------+
  53 +| On-Chip | Power (W) | Used | Available | Utilization (%) |
  54 ++----------------+-----------+----------+-----------+-----------------+
  55 +| Slice Logic | 0.041 | 36 | --- | --- |
  56 +| LUT as Logic | 0.013 | 5 | 20800 | 0.02 |
  57 +| CARRY4 | 0.013 | 5 | 8150 | 0.06 |
  58 +| Register | 0.009 | 20 | 41600 | 0.05 |
  59 +| BUFG | 0.006 | 1 | 32 | 3.13 |
  60 +| Others | 0.000 | 2 | --- | --- |
  61 +| Signals | 0.114 | 34 | --- | --- |
  62 +| I/O | 8.021 | 13 | 106 | 12.26 |
  63 +| Static Power | 0.117 | | | |
  64 +| Total | 8.293 | | | |
  65 ++----------------+-----------+----------+-----------+-----------------+
  66 +
  67 +
  68 +1.2 Power Supply Summary
  69 +------------------------
  70 +
  71 ++-----------+-------------+-----------+-------------+------------+
  72 +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
  73 ++-----------+-------------+-----------+-------------+------------+
  74 +| Vccint | 1.000 | 0.206 | 0.159 | 0.047 |
  75 +| Vccaux | 1.800 | 0.310 | 0.294 | 0.017 |
  76 +| Vcco33 | 3.300 | 2.270 | 2.269 | 0.001 |
  77 +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
  78 +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
  79 +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
  80 +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
  81 +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
  82 +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
  83 +| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 |
  84 +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
  85 +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
  86 +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
  87 ++-----------+-------------+-----------+-------------+------------+
  88 +
  89 +
  90 +1.3 Confidence Level
  91 +--------------------
  92 +
  93 ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
  94 +| User Input Data | Confidence | Details | Action |
  95 ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
  96 +| Design implementation state | High | Design is routed | |
  97 +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
  98 +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
  99 +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
  100 +| Device models | High | Device models are Production | |
  101 +| | | | |
  102 +| Overall confidence level | Low | | |
  103 ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
  104 +
  105 +
  106 +2. Settings
  107 +-----------
  108 +
  109 +2.1 Environment
  110 +---------------
  111 +
  112 ++-----------------------+--------------------------+
  113 +| Ambient Temp (C) | 25.0 |
  114 +| ThetaJA (C/W) | 5.0 |
  115 +| Airflow (LFM) | 250 |
  116 +| Heat Sink | medium (Medium Profile) |
  117 +| ThetaSA (C/W) | 4.6 |
  118 +| Board Selection | medium (10"x10") |
  119 +| # of Board Layers | 12to15 (12 to 15 Layers) |
  120 +| Board Temperature (C) | 25.0 |
  121 ++-----------------------+--------------------------+
  122 +
  123 +
  124 +2.2 Clock Constraints
  125 +---------------------
  126 +
  127 ++-------+--------+-----------------+
  128 +| Clock | Domain | Constraint (ns) |
  129 ++-------+--------+-----------------+
  130 +
  131 +
  132 +3. Detailed Reports
  133 +-------------------
  134 +
  135 +3.1 By Hierarchy
  136 +----------------
  137 +
  138 ++----------------+-----------+
  139 +| Name | Power (W) |
  140 ++----------------+-----------+
  141 +| Afficheur_7SEG | 8.176 |
  142 ++----------------+-----------+
  143 +
  144 +
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  1 +Design Route Status
  2 + : # nets :
  3 + ------------------------------------------- : ----------- :
  4 + # of logical nets.......................... : 70 :
  5 + # of nets not needing routing.......... : 34 :
  6 + # of internally routed nets........ : 34 :
  7 + # of routable nets..................... : 36 :
  8 + # of fully routed nets............. : 36 :
  9 + # of nets with routing errors.......... : 0 :
  10 + ------------------------------------------- : ----------- :
  11 +
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_routed.dcp 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_timing_summary_routed.rpt
@@ -0,0 +1,174 @@ @@ -0,0 +1,174 @@
  1 +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  2 +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  3 +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
  4 +| Date : Wed Oct 4 15:36:05 2023
  5 +| Host : WIN10-TP running 64-bit major release (build 9200)
  6 +| Command : report_timing_summary -max_paths 10 -file Afficheur_7SEG_timing_summary_routed.rpt -pb Afficheur_7SEG_timing_summary_routed.pb -rpx Afficheur_7SEG_timing_summary_routed.rpx -warn_on_violation
  7 +| Design : Afficheur_7SEG
  8 +| Device : 7a35t-cpg236
  9 +| Speed File : -1 PRODUCTION 1.23 2018-06-13
  10 +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  11 +
  12 +Timing Summary Report
  13 +
  14 +------------------------------------------------------------------------------------------------
  15 +| Timer Settings
  16 +| --------------
  17 +------------------------------------------------------------------------------------------------
  18 +
  19 + Enable Multi Corner Analysis : Yes
  20 + Enable Pessimism Removal : Yes
  21 + Pessimism Removal Resolution : Nearest Common Node
  22 + Enable Input Delay Default Clock : No
  23 + Enable Preset / Clear Arcs : No
  24 + Disable Flight Delays : No
  25 + Ignore I/O Paths : No
  26 + Timing Early Launch at Borrowing Latches : No
  27 + Borrow Time for Max Delay Exceptions : Yes
  28 +
  29 + Corner Analyze Analyze
  30 + Name Max Paths Min Paths
  31 + ------ --------- ---------
  32 + Slow Yes Yes
  33 + Fast Yes Yes
  34 +
  35 +
  36 +
  37 +check_timing report
  38 +
  39 +Table of Contents
  40 +-----------------
  41 +1. checking no_clock
  42 +2. checking constant_clock
  43 +3. checking pulse_width_clock
  44 +4. checking unconstrained_internal_endpoints
  45 +5. checking no_input_delay
  46 +6. checking no_output_delay
  47 +7. checking multiple_clock
  48 +8. checking generated_clocks
  49 +9. checking loops
  50 +10. checking partial_input_delay
  51 +11. checking partial_output_delay
  52 +12. checking latch_loops
  53 +
  54 +1. checking no_clock
  55 +--------------------
  56 + There are 20 register/latch pins with no clock driven by root clock pin: Clk_sys (HIGH)
  57 +
  58 +
  59 +2. checking constant_clock
  60 +--------------------------
  61 + There are 0 register/latch pins with constant_clock.
  62 +
  63 +
  64 +3. checking pulse_width_clock
  65 +-----------------------------
  66 + There are 0 register/latch pins which need pulse_width check
  67 +
  68 +
  69 +4. checking unconstrained_internal_endpoints
  70 +--------------------------------------------
  71 + There are 40 pins that are not constrained for maximum delay. (HIGH)
  72 +
  73 + There are 0 pins that are not constrained for maximum delay due to constant clock.
  74 +
  75 +
  76 +5. checking no_input_delay
  77 +--------------------------
  78 + There is 1 input port with no input delay specified. (HIGH)
  79 +
  80 + There are 0 input ports with no input delay but user has a false path constraint.
  81 +
  82 +
  83 +6. checking no_output_delay
  84 +---------------------------
  85 + There are 10 ports with no output delay specified. (HIGH)
  86 +
  87 + There are 0 ports with no output delay but user has a false path constraint
  88 +
  89 + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
  90 +
  91 +
  92 +7. checking multiple_clock
  93 +--------------------------
  94 + There are 0 register/latch pins with multiple clocks.
  95 +
  96 +
  97 +8. checking generated_clocks
  98 +----------------------------
  99 + There are 0 generated clocks that are not connected to a clock source.
  100 +
  101 +
  102 +9. checking loops
  103 +-----------------
  104 + There are 0 combinational loops in the design.
  105 +
  106 +
  107 +10. checking partial_input_delay
  108 +--------------------------------
  109 + There are 0 input ports with partial input delay specified.
  110 +
  111 +
  112 +11. checking partial_output_delay
  113 +---------------------------------
  114 + There are 0 ports with partial output delay specified.
  115 +
  116 +
  117 +12. checking latch_loops
  118 +------------------------
  119 + There are 0 combinational latch loops in the design through latch input
  120 +
  121 +
  122 +
  123 +------------------------------------------------------------------------------------------------
  124 +| Design Timing Summary
  125 +| ---------------------
  126 +------------------------------------------------------------------------------------------------
  127 +
  128 + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
  129 + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
  130 + NA NA NA NA NA NA NA NA NA NA NA NA
  131 +
  132 +
  133 +There are no user specified timing constraints.
  134 +
  135 +
  136 +------------------------------------------------------------------------------------------------
  137 +| Clock Summary
  138 +| -------------
  139 +------------------------------------------------------------------------------------------------
  140 +
  141 +
  142 +------------------------------------------------------------------------------------------------
  143 +| Intra Clock Table
  144 +| -----------------
  145 +------------------------------------------------------------------------------------------------
  146 +
  147 +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
  148 +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
  149 +
  150 +
  151 +------------------------------------------------------------------------------------------------
  152 +| Inter Clock Table
  153 +| -----------------
  154 +------------------------------------------------------------------------------------------------
  155 +
  156 +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
  157 +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
  158 +
  159 +
  160 +------------------------------------------------------------------------------------------------
  161 +| Other Path Groups Table
  162 +| -----------------------
  163 +------------------------------------------------------------------------------------------------
  164 +
  165 +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
  166 +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
  167 +
  168 +
  169 +------------------------------------------------------------------------------------------------
  170 +| Timing Details
  171 +| --------------
  172 +------------------------------------------------------------------------------------------------
  173 +
  174 +
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_timing_summary_routed.rpx 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_utilization_placed.rpt
@@ -0,0 +1,203 @@ @@ -0,0 +1,203 @@
  1 +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  2 +-------------------------------------------------------------------------------------------------------------------------
  3 +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
  4 +| Date : Wed Oct 4 15:35:41 2023
  5 +| Host : WIN10-TP running 64-bit major release (build 9200)
  6 +| Command : report_utilization -file Afficheur_7SEG_utilization_placed.rpt -pb Afficheur_7SEG_utilization_placed.pb
  7 +| Design : Afficheur_7SEG
  8 +| Device : 7a35tcpg236-1
  9 +| Design State : Fully Placed
  10 +-------------------------------------------------------------------------------------------------------------------------
  11 +
  12 +Utilization Design Information
  13 +
  14 +Table of Contents
  15 +-----------------
  16 +1. Slice Logic
  17 +1.1 Summary of Registers by Type
  18 +2. Slice Logic Distribution
  19 +3. Memory
  20 +4. DSP
  21 +5. IO and GT Specific
  22 +6. Clocking
  23 +7. Specific Feature
  24 +8. Primitives
  25 +9. Black Boxes
  26 +10. Instantiated Netlists
  27 +
  28 +1. Slice Logic
  29 +--------------
  30 +
  31 ++-------------------------+------+-------+-----------+-------+
  32 +| Site Type | Used | Fixed | Available | Util% |
  33 ++-------------------------+------+-------+-----------+-------+
  34 +| Slice LUTs | 5 | 0 | 20800 | 0.02 |
  35 +| LUT as Logic | 5 | 0 | 20800 | 0.02 |
  36 +| LUT as Memory | 0 | 0 | 9600 | 0.00 |
  37 +| Slice Registers | 20 | 0 | 41600 | 0.05 |
  38 +| Register as Flip Flop | 20 | 0 | 41600 | 0.05 |
  39 +| Register as Latch | 0 | 0 | 41600 | 0.00 |
  40 +| F7 Muxes | 0 | 0 | 16300 | 0.00 |
  41 +| F8 Muxes | 0 | 0 | 8150 | 0.00 |
  42 ++-------------------------+------+-------+-----------+-------+
  43 +
  44 +
  45 +1.1 Summary of Registers by Type
  46 +--------------------------------
  47 +
  48 ++-------+--------------+-------------+--------------+
  49 +| Total | Clock Enable | Synchronous | Asynchronous |
  50 ++-------+--------------+-------------+--------------+
  51 +| 0 | _ | - | - |
  52 +| 0 | _ | - | Set |
  53 +| 0 | _ | - | Reset |
  54 +| 0 | _ | Set | - |
  55 +| 0 | _ | Reset | - |
  56 +| 0 | Yes | - | - |
  57 +| 0 | Yes | - | Set |
  58 +| 20 | Yes | - | Reset |
  59 +| 0 | Yes | Set | - |
  60 +| 0 | Yes | Reset | - |
  61 ++-------+--------------+-------------+--------------+
  62 +
  63 +
  64 +2. Slice Logic Distribution
  65 +---------------------------
  66 +
  67 ++------------------------------------------+------+-------+-----------+-------+
  68 +| Site Type | Used | Fixed | Available | Util% |
  69 ++------------------------------------------+------+-------+-----------+-------+
  70 +| Slice | 6 | 0 | 8150 | 0.07 |
  71 +| SLICEL | 6 | 0 | | |
  72 +| SLICEM | 0 | 0 | | |
  73 +| LUT as Logic | 5 | 0 | 20800 | 0.02 |
  74 +| using O5 output only | 0 | | | |
  75 +| using O6 output only | 2 | | | |
  76 +| using O5 and O6 | 3 | | | |
  77 +| LUT as Memory | 0 | 0 | 9600 | 0.00 |
  78 +| LUT as Distributed RAM | 0 | 0 | | |
  79 +| LUT as Shift Register | 0 | 0 | | |
  80 +| Slice Registers | 20 | 0 | 41600 | 0.05 |
  81 +| Register driven from within the Slice | 20 | | | |
  82 +| Register driven from outside the Slice | 0 | | | |
  83 +| Unique Control Sets | 1 | | 8150 | 0.01 |
  84 ++------------------------------------------+------+-------+-----------+-------+
  85 +* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
  86 +
  87 +
  88 +3. Memory
  89 +---------
  90 +
  91 ++----------------+------+-------+-----------+-------+
  92 +| Site Type | Used | Fixed | Available | Util% |
  93 ++----------------+------+-------+-----------+-------+
  94 +| Block RAM Tile | 0 | 0 | 50 | 0.00 |
  95 +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
  96 +| RAMB18 | 0 | 0 | 100 | 0.00 |
  97 ++----------------+------+-------+-----------+-------+
  98 +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
  99 +
  100 +
  101 +4. DSP
  102 +------
  103 +
  104 ++-----------+------+-------+-----------+-------+
  105 +| Site Type | Used | Fixed | Available | Util% |
  106 ++-----------+------+-------+-----------+-------+
  107 +| DSPs | 0 | 0 | 90 | 0.00 |
  108 ++-----------+------+-------+-----------+-------+
  109 +
  110 +
  111 +5. IO and GT Specific
  112 +---------------------
  113 +
  114 ++-----------------------------+------+-------+-----------+-------+
  115 +| Site Type | Used | Fixed | Available | Util% |
  116 ++-----------------------------+------+-------+-----------+-------+
  117 +| Bonded IOB | 13 | 13 | 106 | 12.26 |
  118 +| IOB Master Pads | 6 | | | |
  119 +| IOB Slave Pads | 7 | | | |
  120 +| Bonded IPADs | 0 | 0 | 10 | 0.00 |
  121 +| Bonded OPADs | 0 | 0 | 4 | 0.00 |
  122 +| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
  123 +| PHASER_REF | 0 | 0 | 5 | 0.00 |
  124 +| OUT_FIFO | 0 | 0 | 20 | 0.00 |
  125 +| IN_FIFO | 0 | 0 | 20 | 0.00 |
  126 +| IDELAYCTRL | 0 | 0 | 5 | 0.00 |
  127 +| IBUFDS | 0 | 0 | 104 | 0.00 |
  128 +| GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 |
  129 +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
  130 +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
  131 +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
  132 +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
  133 +| ILOGIC | 0 | 0 | 106 | 0.00 |
  134 +| OLOGIC | 0 | 0 | 106 | 0.00 |
  135 ++-----------------------------+------+-------+-----------+-------+
  136 +
  137 +
  138 +6. Clocking
  139 +-----------
  140 +
  141 ++------------+------+-------+-----------+-------+
  142 +| Site Type | Used | Fixed | Available | Util% |
  143 ++------------+------+-------+-----------+-------+
  144 +| BUFGCTRL | 1 | 0 | 32 | 3.13 |
  145 +| BUFIO | 0 | 0 | 20 | 0.00 |
  146 +| MMCME2_ADV | 0 | 0 | 5 | 0.00 |
  147 +| PLLE2_ADV | 0 | 0 | 5 | 0.00 |
  148 +| BUFMRCE | 0 | 0 | 10 | 0.00 |
  149 +| BUFHCE | 0 | 0 | 72 | 0.00 |
  150 +| BUFR | 0 | 0 | 20 | 0.00 |
  151 ++------------+------+-------+-----------+-------+
  152 +
  153 +
  154 +7. Specific Feature
  155 +-------------------
  156 +
  157 ++-------------+------+-------+-----------+-------+
  158 +| Site Type | Used | Fixed | Available | Util% |
  159 ++-------------+------+-------+-----------+-------+
  160 +| BSCANE2 | 0 | 0 | 4 | 0.00 |
  161 +| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
  162 +| DNA_PORT | 0 | 0 | 1 | 0.00 |
  163 +| EFUSE_USR | 0 | 0 | 1 | 0.00 |
  164 +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
  165 +| ICAPE2 | 0 | 0 | 2 | 0.00 |
  166 +| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
  167 +| STARTUPE2 | 0 | 0 | 1 | 0.00 |
  168 +| XADC | 0 | 0 | 1 | 0.00 |
  169 ++-------------+------+-------+-----------+-------+
  170 +
  171 +
  172 +8. Primitives
  173 +-------------
  174 +
  175 ++----------+------+---------------------+
  176 +| Ref Name | Used | Functional Category |
  177 ++----------+------+---------------------+
  178 +| FDCE | 20 | Flop & Latch |
  179 +| OBUF | 11 | IO |
  180 +| LUT2 | 7 | LUT |
  181 +| CARRY4 | 5 | CarryLogic |
  182 +| IBUF | 2 | IO |
  183 +| LUT1 | 1 | LUT |
  184 +| BUFG | 1 | Clock |
  185 ++----------+------+---------------------+
  186 +
  187 +
  188 +9. Black Boxes
  189 +--------------
  190 +
  191 ++----------+------+
  192 +| Ref Name | Used |
  193 ++----------+------+
  194 +
  195 +
  196 +10. Instantiated Netlists
  197 +-------------------------
  198 +
  199 ++----------+------+
  200 +| Ref Name | Used |
  201 ++----------+------+
  202 +
  203 +
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/ISEWrap.js 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/ISEWrap.js
@@ -0,0 +1,270 @@ @@ -0,0 +1,270 @@
  1 +//
  2 +// Vivado(TM)
  3 +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
  4 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
  5 +//
  6 +
  7 +// GLOBAL VARIABLES
  8 +var ISEShell = new ActiveXObject( "WScript.Shell" );
  9 +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
  10 +var ISERunDir = "";
  11 +var ISELogFile = "runme.log";
  12 +var ISELogFileStr = null;
  13 +var ISELogEcho = true;
  14 +var ISEOldVersionWSH = false;
  15 +
  16 +
  17 +
  18 +// BOOTSTRAP
  19 +ISEInit();
  20 +
  21 +
  22 +
  23 +//
  24 +// ISE FUNCTIONS
  25 +//
  26 +function ISEInit() {
  27 +
  28 + // 1. RUN DIR setup
  29 + var ISEScrFP = WScript.ScriptFullName;
  30 + var ISEScrN = WScript.ScriptName;
  31 + ISERunDir =
  32 + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
  33 +
  34 + // 2. LOG file setup
  35 + ISELogFileStr = ISEOpenFile( ISELogFile );
  36 +
  37 + // 3. LOG echo?
  38 + var ISEScriptArgs = WScript.Arguments;
  39 + for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
  40 + if ( ISEScriptArgs(loopi) == "-quiet" ) {
  41 + ISELogEcho = false;
  42 + break;
  43 + }
  44 + }
  45 +
  46 + // 4. WSH version check
  47 + var ISEOptimalVersionWSH = 5.6;
  48 + var ISECurrentVersionWSH = WScript.Version;
  49 + if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
  50 +
  51 + ISEStdErr( "" );
  52 + ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
  53 + ISEOptimalVersionWSH + " or higher. Downloads" );
  54 + ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
  55 + ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
  56 + ISEStdErr( "" );
  57 +
  58 + ISEOldVersionWSH = true;
  59 + }
  60 +
  61 +}
  62 +
  63 +function ISEStep( ISEProg, ISEArgs ) {
  64 +
  65 + // CHECK for a STOP FILE
  66 + if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
  67 + ISEStdErr( "" );
  68 + ISEStdErr( "*** Halting run - EA reset detected ***" );
  69 + ISEStdErr( "" );
  70 + WScript.Quit( 1 );
  71 + }
  72 +
  73 + // WRITE STEP HEADER to LOG
  74 + ISEStdOut( "" );
  75 + ISEStdOut( "*** Running " + ISEProg );
  76 + ISEStdOut( " with args " + ISEArgs );
  77 + ISEStdOut( "" );
  78 +
  79 + // LAUNCH!
  80 + var ISEExitCode = ISEExec( ISEProg, ISEArgs );
  81 + if ( ISEExitCode != 0 ) {
  82 + WScript.Quit( ISEExitCode );
  83 + }
  84 +
  85 +}
  86 +
  87 +function ISEExec( ISEProg, ISEArgs ) {
  88 +
  89 + var ISEStep = ISEProg;
  90 + if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
  91 + ISEProg += ".bat";
  92 + }
  93 +
  94 + var ISECmdLine = ISEProg + " " + ISEArgs;
  95 + var ISEExitCode = 1;
  96 +
  97 + if ( ISEOldVersionWSH ) { // WSH 5.1
  98 +
  99 + // BEGIN file creation
  100 + ISETouchFile( ISEStep, "begin" );
  101 +
  102 + // LAUNCH!
  103 + ISELogFileStr.Close();
  104 + ISECmdLine =
  105 + "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
  106 + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
  107 + ISELogFileStr = ISEOpenFile( ISELogFile );
  108 +
  109 + } else { // WSH 5.6
  110 +
  111 + // LAUNCH!
  112 + ISEShell.CurrentDirectory = ISERunDir;
  113 +
  114 + // Redirect STDERR to STDOUT
  115 + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
  116 + var ISEProcess = ISEShell.Exec( ISECmdLine );
  117 +
  118 + // BEGIN file creation
  119 + var wbemFlagReturnImmediately = 0x10;
  120 + var wbemFlagForwardOnly = 0x20;
  121 + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
  122 + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
  123 + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
  124 + var NOC = 0;
  125 + var NOLP = 0;
  126 + var TPM = 0;
  127 +
  128 + var cpuInfos = new Enumerator(processor);
  129 + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
  130 + var cpuInfo = cpuInfos.item();
  131 + NOC += cpuInfo.NumberOfCores;
  132 + NOLP += cpuInfo.NumberOfLogicalProcessors;
  133 + }
  134 + var csInfos = new Enumerator(computerSystem);
  135 + for(;!csInfos.atEnd(); csInfos.moveNext()) {
  136 + var csInfo = csInfos.item();
  137 + TPM += csInfo.TotalPhysicalMemory;
  138 + }
  139 +
  140 + var ISEHOSTCORE = NOLP
  141 + var ISEMEMTOTAL = TPM
  142 +
  143 + var ISENetwork = WScript.CreateObject( "WScript.Network" );
  144 + var ISEHost = ISENetwork.ComputerName;
  145 + var ISEUser = ISENetwork.UserName;
  146 + var ISEPid = ISEProcess.ProcessID;
  147 + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
  148 + ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
  149 + ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
  150 + ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
  151 + "\" Owner=\"" + ISEUser +
  152 + "\" Host=\"" + ISEHost +
  153 + "\" Pid=\"" + ISEPid +
  154 + "\" HostCore=\"" + ISEHOSTCORE +
  155 + "\" HostMemory=\"" + ISEMEMTOTAL +
  156 + "\">" );
  157 + ISEBeginFile.WriteLine( " </Process>" );
  158 + ISEBeginFile.WriteLine( "</ProcessHandle>" );
  159 + ISEBeginFile.Close();
  160 +
  161 + var ISEOutStr = ISEProcess.StdOut;
  162 + var ISEErrStr = ISEProcess.StdErr;
  163 +
  164 + // WAIT for ISEStep to finish
  165 + while ( ISEProcess.Status == 0 ) {
  166 +
  167 + // dump stdout then stderr - feels a little arbitrary
  168 + while ( !ISEOutStr.AtEndOfStream ) {
  169 + ISEStdOut( ISEOutStr.ReadLine() );
  170 + }
  171 +
  172 + WScript.Sleep( 100 );
  173 + }
  174 +
  175 + ISEExitCode = ISEProcess.ExitCode;
  176 + }
  177 +
  178 + ISELogFileStr.Close();
  179 +
  180 + // END/ERROR file creation
  181 + if ( ISEExitCode != 0 ) {
  182 + ISETouchFile( ISEStep, "error" );
  183 +
  184 + } else {
  185 + ISETouchFile( ISEStep, "end" );
  186 + }
  187 +
  188 + return ISEExitCode;
  189 +}
  190 +
  191 +
  192 +//
  193 +// UTILITIES
  194 +//
  195 +function ISEStdOut( ISELine ) {
  196 +
  197 + ISELogFileStr.WriteLine( ISELine );
  198 +
  199 + if ( ISELogEcho ) {
  200 + WScript.StdOut.WriteLine( ISELine );
  201 + }
  202 +}
  203 +
  204 +function ISEStdErr( ISELine ) {
  205 +
  206 + ISELogFileStr.WriteLine( ISELine );
  207 +
  208 + if ( ISELogEcho ) {
  209 + WScript.StdErr.WriteLine( ISELine );
  210 + }
  211 +}
  212 +
  213 +function ISETouchFile( ISERoot, ISEStatus ) {
  214 +
  215 + var ISETFile =
  216 + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
  217 + ISETFile.Close();
  218 +}
  219 +
  220 +function ISEOpenFile( ISEFilename ) {
  221 +
  222 + // This function has been updated to deal with a problem seen in CR #870871.
  223 + // In that case the user runs a script that runs impl_1, and then turns around
  224 + // and runs impl_1 -to_step write_bitstream. That second run takes place in
  225 + // the same directory, which means we may hit some of the same files, and in
  226 + // particular, we will open the runme.log file. Even though this script closes
  227 + // the file (now), we see cases where a subsequent attempt to open the file
  228 + // fails. Perhaps the OS is slow to release the lock, or the disk comes into
  229 + // play? In any case, we try to work around this by first waiting if the file
  230 + // is already there for an arbitrary 5 seconds. Then we use a try-catch block
  231 + // and try to open the file 10 times with a one second delay after each attempt.
  232 + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
  233 + // If there is an unrecognized exception when trying to open the file, we output
  234 + // an error message and write details to an exception.log file.
  235 + var ISEFullPath = ISERunDir + "/" + ISEFilename;
  236 + if (ISEFileSys.FileExists(ISEFullPath)) {
  237 + // File is already there. This could be a problem. Wait in case it is still in use.
  238 + WScript.Sleep(5000);
  239 + }
  240 + var i;
  241 + for (i = 0; i < 10; ++i) {
  242 + try {
  243 + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
  244 + } catch (exception) {
  245 + var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
  246 + if (error_code == 52) { // 52 is bad file name or number.
  247 + // Wait a second and try again.
  248 + WScript.Sleep(1000);
  249 + continue;
  250 + } else {
  251 + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
  252 + var exceptionFilePath = ISERunDir + "/exception.log";
  253 + if (!ISEFileSys.FileExists(exceptionFilePath)) {
  254 + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
  255 + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
  256 + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
  257 + exceptionFile.WriteLine("\tException name: " + exception.name);
  258 + exceptionFile.WriteLine("\tException error code: " + error_code);
  259 + exceptionFile.WriteLine("\tException message: " + exception.message);
  260 + exceptionFile.Close();
  261 + }
  262 + throw exception;
  263 + }
  264 + }
  265 + }
  266 + // If we reached this point, we failed to open the file after 10 attempts.
  267 + // We need to error out.
  268 + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
  269 + WScript.Quit(1);
  270 +}
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/ISEWrap.sh 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/ISEWrap.sh
@@ -0,0 +1,67 @@ @@ -0,0 +1,67 @@
  1 +#!/bin/sh
  2 +
  3 +#
  4 +# Vivado(TM)
  5 +# ISEWrap.sh: Vivado Runs Script for UNIX
  6 +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
  7 +#
  8 +
  9 +HD_LOG=$1
  10 +shift
  11 +
  12 +# CHECK for a STOP FILE
  13 +if [ -f .stop.rst ]
  14 +then
  15 +echo "" >> $HD_LOG
  16 +echo "*** Halting run - EA reset detected ***" >> $HD_LOG
  17 +echo "" >> $HD_LOG
  18 +exit 1
  19 +fi
  20 +
  21 +ISE_STEP=$1
  22 +shift
  23 +
  24 +# WRITE STEP HEADER to LOG
  25 +echo "" >> $HD_LOG
  26 +echo "*** Running $ISE_STEP" >> $HD_LOG
  27 +echo " with args $@" >> $HD_LOG
  28 +echo "" >> $HD_LOG
  29 +
  30 +# LAUNCH!
  31 +$ISE_STEP "$@" >> $HD_LOG 2>&1 &
  32 +
  33 +# BEGIN file creation
  34 +ISE_PID=$!
  35 +if [ X != X$HOSTNAME ]
  36 +then
  37 +ISE_HOST=$HOSTNAME #bash
  38 +else
  39 +ISE_HOST=$HOST #csh
  40 +fi
  41 +ISE_USER=$USER
  42 +
  43 +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
  44 +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
  45 +
  46 +ISE_BEGINFILE=.$ISE_STEP.begin.rst
  47 +/bin/touch $ISE_BEGINFILE
  48 +echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
  49 +echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
  50 +echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
  51 +echo " </Process>" >> $ISE_BEGINFILE
  52 +echo "</ProcessHandle>" >> $ISE_BEGINFILE
  53 +
  54 +# WAIT for ISEStep to finish
  55 +wait $ISE_PID
  56 +
  57 +# END/ERROR file creation
  58 +RETVAL=$?
  59 +if [ $RETVAL -eq 0 ]
  60 +then
  61 + /bin/touch .$ISE_STEP.end.rst
  62 +else
  63 + /bin/touch .$ISE_STEP.error.rst
  64 +fi
  65 +
  66 +exit $RETVAL
  67 +
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/gen_run.xml 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/gen_run.xml
@@ -0,0 +1,118 @@ @@ -0,0 +1,118 @@
  1 +<?xml version="1.0" encoding="UTF-8"?>
  2 +<GenRun Id="impl_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1696426474">
  3 + <File Type="BITSTR-BMM" Name="Afficheur_7SEG_bd.bmm"/>
  4 + <File Type="OPT-METHODOLOGY-DRC" Name="Afficheur_7SEG_methodology_drc_opted.rpt"/>
  5 + <File Type="INIT-TIMING" Name="Afficheur_7SEG_timing_summary_init.rpt"/>
  6 + <File Type="ROUTE-PWR" Name="Afficheur_7SEG_power_routed.rpt"/>
  7 + <File Type="PA-TCL" Name="Afficheur_7SEG.tcl"/>
  8 + <File Type="OPT-TIMING" Name="Afficheur_7SEG_timing_summary_opted.rpt"/>
  9 + <File Type="OPT-DCP" Name="Afficheur_7SEG_opt.dcp"/>
  10 + <File Type="ROUTE-PWR-SUM" Name="Afficheur_7SEG_power_summary_routed.pb"/>
  11 + <File Type="REPORTS-TCL" Name="Afficheur_7SEG_reports.tcl"/>
  12 + <File Type="OPT-DRC" Name="Afficheur_7SEG_drc_opted.rpt"/>
  13 + <File Type="OPT-HWDEF" Name="Afficheur_7SEG.hwdef"/>
  14 + <File Type="PWROPT-DCP" Name="Afficheur_7SEG_pwropt.dcp"/>
  15 + <File Type="PWROPT-DRC" Name="Afficheur_7SEG_drc_pwropted.rpt"/>
  16 + <File Type="PWROPT-TIMING" Name="Afficheur_7SEG_timing_summary_pwropted.rpt"/>
  17 + <File Type="PLACE-DCP" Name="Afficheur_7SEG_placed.dcp"/>
  18 + <File Type="PLACE-IO" Name="Afficheur_7SEG_io_placed.rpt"/>
  19 + <File Type="PLACE-CLK" Name="Afficheur_7SEG_clock_utilization_placed.rpt"/>
  20 + <File Type="PLACE-UTIL" Name="Afficheur_7SEG_utilization_placed.rpt"/>
  21 + <File Type="PLACE-UTIL-PB" Name="Afficheur_7SEG_utilization_placed.pb"/>
  22 + <File Type="PLACE-CTRL" Name="Afficheur_7SEG_control_sets_placed.rpt"/>
  23 + <File Type="PLACE-SIMILARITY" Name="Afficheur_7SEG_incremental_reuse_placed.rpt"/>
  24 + <File Type="PLACE-PRE-SIMILARITY" Name="Afficheur_7SEG_incremental_reuse_pre_placed.rpt"/>
  25 + <File Type="BG-BGN" Name="Afficheur_7SEG.bgn"/>
  26 + <File Type="PLACE-TIMING" Name="Afficheur_7SEG_timing_summary_placed.rpt"/>
  27 + <File Type="POSTPLACE-PWROPT-DCP" Name="Afficheur_7SEG_postplace_pwropt.dcp"/>
  28 + <File Type="BG-BIN" Name="Afficheur_7SEG.bin"/>
  29 + <File Type="POSTPLACE-PWROPT-TIMING" Name="Afficheur_7SEG_timing_summary_postplace_pwropted.rpt"/>
  30 + <File Type="PHYSOPT-DCP" Name="Afficheur_7SEG_physopt.dcp"/>
  31 + <File Type="PHYSOPT-DRC" Name="Afficheur_7SEG_drc_physopted.rpt"/>
  32 + <File Type="BITSTR-MSK" Name="Afficheur_7SEG.msk"/>
  33 + <File Type="PHYSOPT-TIMING" Name="Afficheur_7SEG_timing_summary_physopted.rpt"/>
  34 + <File Type="ROUTE-ERROR-DCP" Name="Afficheur_7SEG_routed_error.dcp"/>
  35 + <File Type="ROUTE-DCP" Name="Afficheur_7SEG_routed.dcp"/>
  36 + <File Type="ROUTE-BLACKBOX-DCP" Name="Afficheur_7SEG_routed_bb.dcp"/>
  37 + <File Type="ROUTE-DRC" Name="Afficheur_7SEG_drc_routed.rpt"/>
  38 + <File Type="ROUTE-DRC-PB" Name="Afficheur_7SEG_drc_routed.pb"/>
  39 + <File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
  40 + <File Type="BITSTR-LTX" Name="Afficheur_7SEG.ltx"/>
  41 + <File Type="ROUTE-DRC-RPX" Name="Afficheur_7SEG_drc_routed.rpx"/>
  42 + <File Type="BITSTR-MMI" Name="Afficheur_7SEG.mmi"/>
  43 + <File Type="ROUTE-METHODOLOGY-DRC" Name="Afficheur_7SEG_methodology_drc_routed.rpt"/>
  44 + <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="Afficheur_7SEG_methodology_drc_routed.rpx"/>
  45 + <File Type="BITSTR-SYSDEF" Name="Afficheur_7SEG.sysdef"/>
  46 + <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="Afficheur_7SEG_methodology_drc_routed.pb"/>
  47 + <File Type="ROUTE-PWR-RPX" Name="Afficheur_7SEG_power_routed.rpx"/>
  48 + <File Type="ROUTE-STATUS" Name="Afficheur_7SEG_route_status.rpt"/>
  49 + <File Type="ROUTE-STATUS-PB" Name="Afficheur_7SEG_route_status.pb"/>
  50 + <File Type="ROUTE-TIMINGSUMMARY" Name="Afficheur_7SEG_timing_summary_routed.rpt"/>
  51 + <File Type="ROUTE-TIMING-PB" Name="Afficheur_7SEG_timing_summary_routed.pb"/>
  52 + <File Type="ROUTE-TIMING-RPX" Name="Afficheur_7SEG_timing_summary_routed.rpx"/>
  53 + <File Type="ROUTE-SIMILARITY" Name="Afficheur_7SEG_incremental_reuse_routed.rpt"/>
  54 + <File Type="ROUTE-CLK" Name="Afficheur_7SEG_clock_utilization_routed.rpt"/>
  55 + <File Type="ROUTE-BUS-SKEW" Name="Afficheur_7SEG_bus_skew_routed.rpt"/>
  56 + <File Type="ROUTE-BUS-SKEW-PB" Name="Afficheur_7SEG_bus_skew_routed.pb"/>
  57 + <File Type="ROUTE-BUS-SKEW-RPX" Name="Afficheur_7SEG_bus_skew_routed.rpx"/>
  58 + <File Type="POSTROUTE-PHYSOPT-DCP" Name="Afficheur_7SEG_postroute_physopt.dcp"/>
  59 + <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="Afficheur_7SEG_postroute_physopt_bb.dcp"/>
  60 + <File Type="POSTROUTE-PHYSOPT-TIMING" Name="Afficheur_7SEG_timing_summary_postroute_physopted.rpt"/>
  61 + <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="Afficheur_7SEG_timing_summary_postroute_physopted.pb"/>
  62 + <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="Afficheur_7SEG_timing_summary_postroute_physopted.rpx"/>
  63 + <File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="Afficheur_7SEG_bus_skew_postroute_physopted.rpt"/>
  64 + <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="Afficheur_7SEG_bus_skew_postroute_physopted.pb"/>
  65 + <File Type="BG-BIT" Name="Afficheur_7SEG.bit"/>
  66 + <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="Afficheur_7SEG_bus_skew_postroute_physopted.rpx"/>
  67 + <File Type="BITSTR-RBT" Name="Afficheur_7SEG.rbt"/>
  68 + <File Type="BITSTR-NKY" Name="Afficheur_7SEG.nky"/>
  69 + <File Type="BG-DRC" Name="Afficheur_7SEG.drc"/>
  70 + <File Type="RDI-RDI" Name="Afficheur_7SEG.vdi"/>
  71 + <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
  72 + <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
  73 + <Filter Type="Srcs"/>
  74 + <File Path="$PSRCDIR/sources_1/new/Afficheur_7SEG.vhd">
  75 + <FileInfo>
  76 + <Attr Name="UsedIn" Val="synthesis"/>
  77 + <Attr Name="UsedIn" Val="simulation"/>
  78 + </FileInfo>
  79 + </File>
  80 + <Config>
  81 + <Option Name="DesignMode" Val="RTL"/>
  82 + <Option Name="TopModule" Val="Afficheur_7SEG"/>
  83 + <Option Name="TopAutoSet" Val="TRUE"/>
  84 + </Config>
  85 + </FileSet>
  86 + <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
  87 + <Filter Type="Constrs"/>
  88 + <File Path="$PSRCDIR/constrs_1/imports/TP1/Basys-3-Master.xdc">
  89 + <FileInfo>
  90 + <Attr Name="ImportPath" Val="$PPRDIR/../TP1/Basys-3-Master.xdc"/>
  91 + <Attr Name="ImportTime" Val="1695796577"/>
  92 + <Attr Name="UsedIn" Val="synthesis"/>
  93 + <Attr Name="UsedIn" Val="implementation"/>
  94 + </FileInfo>
  95 + </File>
  96 + <Config>
  97 + <Option Name="ConstrsType" Val="XDC"/>
  98 + </Config>
  99 + </FileSet>
  100 + <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
  101 + <Filter Type="Utils"/>
  102 + <Config>
  103 + <Option Name="TopAutoSet" Val="TRUE"/>
  104 + </Config>
  105 + </FileSet>
  106 + <Strategy Version="1" Minor="2">
  107 + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
  108 + <Step Id="init_design"/>
  109 + <Step Id="opt_design"/>
  110 + <Step Id="power_opt_design"/>
  111 + <Step Id="place_design"/>
  112 + <Step Id="post_place_power_opt_design"/>
  113 + <Step Id="phys_opt_design"/>
  114 + <Step Id="route_design"/>
  115 + <Step Id="post_route_phys_opt_design"/>
  116 + <Step Id="write_bitstream"/>
  117 + </Strategy>
  118 +</GenRun>
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/htr.txt 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/htr.txt
@@ -0,0 +1,9 @@ @@ -0,0 +1,9 @@
  1 +REM
  2 +REM Vivado(TM)
  3 +REM htr.txt: a Vivado-generated description of how-to-repeat the
  4 +REM the basic steps of a run. Note that runme.bat/sh needs
  5 +REM to be invoked for Vivado to track run status.
  6 +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  7 +REM
  8 +
  9 +vivado -log Afficheur_7SEG.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/init_design.pb 0 → 100755
View file @231d00d
No preview for this file type
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/opt_design.pb 0 → 100755
View file @231d00d
No preview for this file type
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/place_design.pb 0 → 100755
View file @231d00d
No preview for this file type
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/project.wdf 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/project.wdf
@@ -0,0 +1,31 @@ @@ -0,0 +1,31 @@
  1 +version:1
  2 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00
  3 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
  4 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
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  6 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
  7 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
  8 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
  9 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
  10 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
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  15 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
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  17 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
  18 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
  19 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
  20 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
  21 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
  22 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
  23 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
  24 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
  25 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
  26 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
  27 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
  28 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
  29 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
  30 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6333633239656530336164323430373839623861306364656562396331663962:506172656e742050412070726f6a656374204944:00
  31 +eof:3020042384
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/route_design.pb 0 → 100755
View file @231d00d
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Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/rundef.js 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/rundef.js
@@ -0,0 +1,40 @@ @@ -0,0 +1,40 @@
  1 +//
  2 +// Vivado(TM)
  3 +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
  4 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  5 +//
  6 +
  7 +var WshShell = new ActiveXObject( "WScript.Shell" );
  8 +var ProcEnv = WshShell.Environment( "Process" );
  9 +var PathVal = ProcEnv("PATH");
  10 +if ( PathVal.length == 0 ) {
  11 + PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;";
  12 +} else {
  13 + PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal;
  14 +}
  15 +
  16 +ProcEnv("PATH") = PathVal;
  17 +
  18 +var RDScrFP = WScript.ScriptFullName;
  19 +var RDScrN = WScript.ScriptName;
  20 +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
  21 +var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
  22 +eval( EAInclude(ISEJScriptLib) );
  23 +
  24 +
  25 +// pre-commands:
  26 +ISETouchFile( "init_design", "begin" );
  27 +ISEStep( "vivado",
  28 + "-log Afficheur_7SEG.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace" );
  29 +
  30 +
  31 +
  32 +
  33 +
  34 +function EAInclude( EAInclFilename ) {
  35 + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
  36 + var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
  37 + var EAIFContents = EAInclFile.ReadAll();
  38 + EAInclFile.Close();
  39 + return EAIFContents;
  40 +}
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/runme.bat 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/runme.bat
@@ -0,0 +1,10 @@ @@ -0,0 +1,10 @@
  1 +@echo off
  2 +
  3 +rem Vivado (TM)
  4 +rem runme.bat: a Vivado-generated Script
  5 +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  6 +
  7 +
  8 +set HD_SDIR=%~dp0
  9 +cd /d "%HD_SDIR%"
  10 +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/runme.log 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/runme.log
@@ -0,0 +1,499 @@ @@ -0,0 +1,499 @@
  1 +
  2 +*** Running vivado
  3 + with args -log Afficheur_7SEG.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace
  4 +
  5 +
  6 +****** Vivado v2019.1 (64-bit)
  7 + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
  8 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
  9 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  10 +
  11 +source Afficheur_7SEG.tcl -notrace
  12 +Command: link_design -top Afficheur_7SEG -part xc7a35tcpg236-1
  13 +Design is defaulting to srcset: sources_1
  14 +Design is defaulting to constrset: constrs_1
  15 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1
  16 +INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement
  17 +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
  18 +INFO: [Project 1-479] Netlist was created with Vivado 2019.1
  19 +INFO: [Project 1-570] Preparing netlist for logic optimization
  20 +Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc]
  21 +Finished Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc]
  22 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  23 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 662.551 ; gain = 0.000
  24 +INFO: [Project 1-111] Unisim Transformation Summary:
  25 +No Unisim elements were transformed.
  26 +
  27 +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  28 +link_design completed successfully
  29 +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 666.586 ; gain = 375.434
  30 +Command: opt_design
  31 +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  32 +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  33 +Running DRC as a precondition to command opt_design
  34 +
  35 +Starting DRC Task
  36 +INFO: [DRC 23-27] Running DRC with 2 threads
  37 +INFO: [Project 1-461] DRC finished with 0 Errors
  38 +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
  39 +
  40 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.643 . Memory (MB): peak = 686.492 ; gain = 19.906
  41 +
  42 +Starting Cache Timing Information Task
  43 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  44 +Ending Cache Timing Information Task | Checksum: 1b472ca95
  45 +
  46 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1200.875 ; gain = 514.383
  47 +
  48 +Starting Logic Optimization Task
  49 +
  50 +Phase 1 Retarget
  51 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  52 +INFO: [Opt 31-49] Retargeted 0 cell(s).
  53 +Phase 1 Retarget | Checksum: 1b472ca95
  54 +
  55 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1341.555 ; gain = 0.000
  56 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
  57 +
  58 +Phase 2 Constant propagation
  59 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  60 +Phase 2 Constant propagation | Checksum: 1b472ca95
  61 +
  62 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1341.555 ; gain = 0.000
  63 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
  64 +
  65 +Phase 3 Sweep
  66 +Phase 3 Sweep | Checksum: 1f526e7c3
  67 +
  68 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1341.555 ; gain = 0.000
  69 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
  70 +
  71 +Phase 4 BUFG optimization
  72 +Phase 4 BUFG optimization | Checksum: 1f526e7c3
  73 +
  74 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1341.555 ; gain = 0.000
  75 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
  76 +
  77 +Phase 5 Shift Register Optimization
  78 +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
  79 +Phase 5 Shift Register Optimization | Checksum: 1f526e7c3
  80 +
  81 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1341.555 ; gain = 0.000
  82 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
  83 +
  84 +Phase 6 Post Processing Netlist
  85 +Phase 6 Post Processing Netlist | Checksum: 1f526e7c3
  86 +
  87 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1341.555 ; gain = 0.000
  88 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
  89 +Opt_design Change Summary
  90 +=========================
  91 +
  92 +
  93 +-------------------------------------------------------------------------------------------------------------------------
  94 +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
  95 +-------------------------------------------------------------------------------------------------------------------------
  96 +| Retarget | 0 | 0 | 0 |
  97 +| Constant propagation | 0 | 0 | 0 |
  98 +| Sweep | 0 | 0 | 0 |
  99 +| BUFG optimization | 0 | 0 | 0 |
  100 +| Shift Register Optimization | 0 | 0 | 0 |
  101 +| Post Processing Netlist | 0 | 0 | 0 |
  102 +-------------------------------------------------------------------------------------------------------------------------
  103 +
  104 +
  105 +
  106 +Starting Connectivity Check Task
  107 +
  108 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1341.555 ; gain = 0.000
  109 +Ending Logic Optimization Task | Checksum: 260393764
  110 +
  111 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1341.555 ; gain = 0.000
  112 +
  113 +Starting Power Optimization Task
  114 +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
  115 +Ending Power Optimization Task | Checksum: 260393764
  116 +
  117 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1341.555 ; gain = 0.000
  118 +
  119 +Starting Final Cleanup Task
  120 +Ending Final Cleanup Task | Checksum: 260393764
  121 +
  122 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000
  123 +
  124 +Starting Netlist Obfuscation Task
  125 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000
  126 +Ending Netlist Obfuscation Task | Checksum: 260393764
  127 +
  128 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000
  129 +INFO: [Common 17-83] Releasing license: Implementation
  130 +24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  131 +opt_design completed successfully
  132 +opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1341.555 ; gain = 674.969
  133 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000
  134 +INFO: [Timing 38-480] Writing timing data to binary archive.
  135 +Writing placer database...
  136 +Writing XDEF routing.
  137 +Writing XDEF routing logical nets.
  138 +Writing XDEF routing special nets.
  139 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1341.555 ; gain = 0.000
  140 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_opt.dcp' has been generated.
  141 +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx
  142 +Command: report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx
  143 +INFO: [IP_Flow 19-234] Refreshing IP repositories
  144 +INFO: [IP_Flow 19-1704] No user IP repositories specified
  145 +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'.
  146 +INFO: [DRC 23-27] Running DRC with 2 threads
  147 +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpt.
  148 +report_drc completed successfully
  149 +Command: place_design
  150 +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  151 +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  152 +INFO: [DRC 23-27] Running DRC with 2 threads
  153 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  154 +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  155 +Running DRC as a precondition to command place_design
  156 +INFO: [DRC 23-27] Running DRC with 2 threads
  157 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  158 +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  159 +
  160 +Starting Placer Task
  161 +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
  162 +
  163 +Phase 1 Placer Initialization
  164 +
  165 +Phase 1.1 Placer Initialization Netlist Sorting
  166 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000
  167 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1d171f48f
  168 +
  169 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1341.555 ; gain = 0.000
  170 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1341.555 ; gain = 0.000
  171 +
  172 +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
  173 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  174 +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1b8f8806f
  175 +
  176 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.835 . Memory (MB): peak = 1341.555 ; gain = 0.000
  177 +
  178 +Phase 1.3 Build Placer Netlist Model
  179 +Phase 1.3 Build Placer Netlist Model | Checksum: 2ac1244c8
  180 +
  181 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.847 . Memory (MB): peak = 1341.555 ; gain = 0.000
  182 +
  183 +Phase 1.4 Constrain Clocks/Macros
  184 +Phase 1.4 Constrain Clocks/Macros | Checksum: 2ac1244c8
  185 +
  186 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.849 . Memory (MB): peak = 1341.555 ; gain = 0.000
  187 +Phase 1 Placer Initialization | Checksum: 2ac1244c8
  188 +
  189 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.850 . Memory (MB): peak = 1341.555 ; gain = 0.000
  190 +
  191 +Phase 2 Global Placement
  192 +
  193 +Phase 2.1 Floorplanning
  194 +Phase 2.1 Floorplanning | Checksum: 2ac1244c8
  195 +
  196 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.852 . Memory (MB): peak = 1341.555 ; gain = 0.000
  197 +
  198 +Phase 2.2 Global Placement Core
  199 +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
  200 +Phase 2.2 Global Placement Core | Checksum: 21c4ed49b
  201 +
  202 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  203 +Phase 2 Global Placement | Checksum: 21c4ed49b
  204 +
  205 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  206 +
  207 +Phase 3 Detail Placement
  208 +
  209 +Phase 3.1 Commit Multi Column Macros
  210 +Phase 3.1 Commit Multi Column Macros | Checksum: 21c4ed49b
  211 +
  212 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  213 +
  214 +Phase 3.2 Commit Most Macros & LUTRAMs
  215 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18a378908
  216 +
  217 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  218 +
  219 +Phase 3.3 Area Swap Optimization
  220 +Phase 3.3 Area Swap Optimization | Checksum: 216e3a3c1
  221 +
  222 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  223 +
  224 +Phase 3.4 Pipeline Register Optimization
  225 +Phase 3.4 Pipeline Register Optimization | Checksum: 216e3a3c1
  226 +
  227 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  228 +
  229 +Phase 3.5 Small Shape Detail Placement
  230 +Phase 3.5 Small Shape Detail Placement | Checksum: 19592b163
  231 +
  232 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  233 +
  234 +Phase 3.6 Re-assign LUT pins
  235 +Phase 3.6 Re-assign LUT pins | Checksum: 19592b163
  236 +
  237 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  238 +
  239 +Phase 3.7 Pipeline Register Optimization
  240 +Phase 3.7 Pipeline Register Optimization | Checksum: 19592b163
  241 +
  242 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  243 +Phase 3 Detail Placement | Checksum: 19592b163
  244 +
  245 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  246 +
  247 +Phase 4 Post Placement Optimization and Clean-Up
  248 +
  249 +Phase 4.1 Post Commit Optimization
  250 +Phase 4.1 Post Commit Optimization | Checksum: 19592b163
  251 +
  252 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  253 +
  254 +Phase 4.2 Post Placement Cleanup
  255 +Phase 4.2 Post Placement Cleanup | Checksum: 19592b163
  256 +
  257 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  258 +
  259 +Phase 4.3 Placer Reporting
  260 +Phase 4.3 Placer Reporting | Checksum: 19592b163
  261 +
  262 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  263 +
  264 +Phase 4.4 Final Placement Cleanup
  265 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1341.555 ; gain = 0.000
  266 +Phase 4.4 Final Placement Cleanup | Checksum: 19592b163
  267 +
  268 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  269 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 19592b163
  270 +
  271 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  272 +Ending Placer Task | Checksum: 16b3cb9b6
  273 +
  274 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000
  275 +INFO: [Common 17-83] Releasing license: Implementation
  276 +42 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
  277 +place_design completed successfully
  278 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000
  279 +INFO: [Timing 38-480] Writing timing data to binary archive.
  280 +Writing placer database...
  281 +Writing XDEF routing.
  282 +Writing XDEF routing logical nets.
  283 +Writing XDEF routing special nets.
  284 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1352.461 ; gain = 10.906
  285 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_placed.dcp' has been generated.
  286 +INFO: [runtcl-4] Executing : report_io -file Afficheur_7SEG_io_placed.rpt
  287 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1352.461 ; gain = 0.000
  288 +INFO: [runtcl-4] Executing : report_utilization -file Afficheur_7SEG_utilization_placed.rpt -pb Afficheur_7SEG_utilization_placed.pb
  289 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file Afficheur_7SEG_control_sets_placed.rpt
  290 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1352.461 ; gain = 0.000
  291 +Command: route_design
  292 +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  293 +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  294 +Running DRC as a precondition to command route_design
  295 +INFO: [DRC 23-27] Running DRC with 2 threads
  296 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  297 +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  298 +
  299 +
  300 +Starting Routing Task
  301 +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
  302 +Checksum: PlaceDB: 92aaeef2 ConstDB: 0 ShapeSum: d891cac4 RouteDB: 0
  303 +
  304 +Phase 1 Build RT Design
  305 +Phase 1 Build RT Design | Checksum: 9fc16879
  306 +
  307 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1442.992 ; gain = 79.531
  308 +Post Restoration Checksum: NetGraph: 769cd3b9 NumContArr: 292494c0 Constraints: 0 Timing: 0
  309 +
  310 +Phase 2 Router Initialization
  311 +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
  312 +
  313 +Phase 2.1 Fix Topology Constraints
  314 +Phase 2.1 Fix Topology Constraints | Checksum: 9fc16879
  315 +
  316 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1449.000 ; gain = 85.539
  317 +
  318 +Phase 2.2 Pre Route Cleanup
  319 +Phase 2.2 Pre Route Cleanup | Checksum: 9fc16879
  320 +
  321 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1449.000 ; gain = 85.539
  322 + Number of Nodes with overlaps = 0
  323 +Phase 2 Router Initialization | Checksum: 16939516a
  324 +
  325 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1452.375 ; gain = 88.914
  326 +
  327 +Router Utilization Summary
  328 + Global Vertical Routing Utilization = 0 %
  329 + Global Horizontal Routing Utilization = 0 %
  330 + Routable Net Status*
  331 + *Does not include unroutable nets such as driverless and loadless.
  332 + Run report_route_status for detailed report.
  333 + Number of Failed Nets = 32
  334 + (Failed Nets is the sum of unrouted and partially routed nets)
  335 + Number of Unrouted Nets = 32
  336 + Number of Partially Routed Nets = 0
  337 + Number of Node Overlaps = 0
  338 +
  339 +
  340 +Phase 3 Initial Routing
  341 +Phase 3 Initial Routing | Checksum: 106a7763c
  342 +
  343 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027
  344 +
  345 +Phase 4 Rip-up And Reroute
  346 +
  347 +Phase 4.1 Global Iteration 0
  348 + Number of Nodes with overlaps = 0
  349 +Phase 4.1 Global Iteration 0 | Checksum: 131215cb1
  350 +
  351 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027
  352 +Phase 4 Rip-up And Reroute | Checksum: 131215cb1
  353 +
  354 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027
  355 +
  356 +Phase 5 Delay and Skew Optimization
  357 +Phase 5 Delay and Skew Optimization | Checksum: 131215cb1
  358 +
  359 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027
  360 +
  361 +Phase 6 Post Hold Fix
  362 +
  363 +Phase 6.1 Hold Fix Iter
  364 +Phase 6.1 Hold Fix Iter | Checksum: 131215cb1
  365 +
  366 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027
  367 +Phase 6 Post Hold Fix | Checksum: 131215cb1
  368 +
  369 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027
  370 +
  371 +Phase 7 Route finalize
  372 +
  373 +Router Utilization Summary
  374 + Global Vertical Routing Utilization = 0.0058997 %
  375 + Global Horizontal Routing Utilization = 0.0158771 %
  376 + Routable Net Status*
  377 + *Does not include unroutable nets such as driverless and loadless.
  378 + Run report_route_status for detailed report.
  379 + Number of Failed Nets = 0
  380 + (Failed Nets is the sum of unrouted and partially routed nets)
  381 + Number of Unrouted Nets = 0
  382 + Number of Partially Routed Nets = 0
  383 + Number of Node Overlaps = 0
  384 +
  385 +Congestion Report
  386 +North Dir 1x1 Area, Max Cong = 9.90991%, No Congested Regions.
  387 +South Dir 1x1 Area, Max Cong = 9.00901%, No Congested Regions.
  388 +East Dir 1x1 Area, Max Cong = 23.5294%, No Congested Regions.
  389 +West Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions.
  390 +
  391 +------------------------------
  392 +Reporting congestion hotspots
  393 +------------------------------
  394 +Direction: North
  395 +----------------
  396 +Congested clusters found at Level 0
  397 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  398 +Direction: South
  399 +----------------
  400 +Congested clusters found at Level 0
  401 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  402 +Direction: East
  403 +----------------
  404 +Congested clusters found at Level 0
  405 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  406 +Direction: West
  407 +----------------
  408 +Congested clusters found at Level 0
  409 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  410 +
  411 +Phase 7 Route finalize | Checksum: 131215cb1
  412 +
  413 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027
  414 +
  415 +Phase 8 Verifying routed nets
  416 +
  417 + Verification completed successfully
  418 +Phase 8 Verifying routed nets | Checksum: 131215cb1
  419 +
  420 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1455.516 ; gain = 92.055
  421 +
  422 +Phase 9 Depositing Routes
  423 +Phase 9 Depositing Routes | Checksum: 1cda4acbc
  424 +
  425 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1455.516 ; gain = 92.055
  426 +INFO: [Route 35-16] Router Completed Successfully
  427 +
  428 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1455.516 ; gain = 92.055
  429 +
  430 +Routing Is Done.
  431 +INFO: [Common 17-83] Releasing license: Implementation
  432 +55 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
  433 +route_design completed successfully
  434 +route_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1455.516 ; gain = 103.055
  435 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1455.516 ; gain = 0.000
  436 +INFO: [Timing 38-480] Writing timing data to binary archive.
  437 +Writing placer database...
  438 +Writing XDEF routing.
  439 +Writing XDEF routing logical nets.
  440 +Writing XDEF routing special nets.
  441 +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1465.422 ; gain = 9.906
  442 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_routed.dcp' has been generated.
  443 +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx
  444 +Command: report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx
  445 +INFO: [IP_Flow 19-1839] IP Catalog is up to date.
  446 +INFO: [DRC 23-27] Running DRC with 2 threads
  447 +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpt.
  448 +report_drc completed successfully
  449 +INFO: [runtcl-4] Executing : report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx
  450 +Command: report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx
  451 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  452 +INFO: [DRC 23-133] Running Methodology with 2 threads
  453 +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.rpt.
  454 +report_methodology completed successfully
  455 +INFO: [runtcl-4] Executing : report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx
  456 +Command: report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx
  457 +INFO: [Timing 38-35] Done setting XDC timing constraints.
  458 +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
  459 +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
  460 +Running Vector-less Activity Propagation...
  461 +
  462 +Finished Running Vector-less Activity Propagation
  463 +67 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
  464 +report_power completed successfully
  465 +INFO: [runtcl-4] Executing : report_route_status -file Afficheur_7SEG_route_status.rpt -pb Afficheur_7SEG_route_status.pb
  466 +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Afficheur_7SEG_timing_summary_routed.rpt -pb Afficheur_7SEG_timing_summary_routed.pb -rpx Afficheur_7SEG_timing_summary_routed.rpx -warn_on_violation
  467 +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
  468 +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
  469 +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
  470 +INFO: [runtcl-4] Executing : report_incremental_reuse -file Afficheur_7SEG_incremental_reuse_routed.rpt
  471 +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
  472 +INFO: [runtcl-4] Executing : report_clock_utilization -file Afficheur_7SEG_clock_utilization_routed.rpt
  473 +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Afficheur_7SEG_bus_skew_routed.rpt -pb Afficheur_7SEG_bus_skew_routed.pb -rpx Afficheur_7SEG_bus_skew_routed.rpx
  474 +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
  475 +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
  476 +Command: write_bitstream -force Afficheur_7SEG.bit
  477 +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
  478 +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
  479 +Running DRC as a precondition to command write_bitstream
  480 +INFO: [IP_Flow 19-1839] IP Catalog is up to date.
  481 +INFO: [DRC 23-27] Running DRC with 2 threads
  482 +INFO: [Vivado 12-3199] DRC finished with 0 Errors
  483 +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
  484 +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
  485 +Loading data files...
  486 +Loading site data...
  487 +Loading route data...
  488 +Processing options...
  489 +Creating bitmap...
  490 +Creating bitstream...
  491 +Bitstream compression saved 15755616 bits.
  492 +Writing bitstream ./Afficheur_7SEG.bit...
  493 +INFO: [Vivado 12-1842] Bitgen Completed Successfully.
  494 +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
  495 +INFO: [Common 17-83] Releasing license: Implementation
  496 +86 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
  497 +write_bitstream completed successfully
  498 +write_bitstream: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1920.316 ; gain = 405.871
  499 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 4 15:36:15 2023...
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/runme.sh 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/runme.sh
@@ -0,0 +1,47 @@ @@ -0,0 +1,47 @@
  1 +#!/bin/sh
  2 +
  3 +#
  4 +# Vivado(TM)
  5 +# runme.sh: a Vivado-generated Runs Script for UNIX
  6 +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  7 +#
  8 +
  9 +echo "This script was generated under a different operating system."
  10 +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
  11 +exit
  12 +
  13 +if [ -z "$PATH" ]; then
  14 + PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin
  15 +else
  16 + PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH
  17 +fi
  18 +export PATH
  19 +
  20 +if [ -z "$LD_LIBRARY_PATH" ]; then
  21 + LD_LIBRARY_PATH=
  22 +else
  23 + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
  24 +fi
  25 +export LD_LIBRARY_PATH
  26 +
  27 +HD_PWD='C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1'
  28 +cd "$HD_PWD"
  29 +
  30 +HD_LOG=runme.log
  31 +/bin/touch $HD_LOG
  32 +
  33 +ISEStep="./ISEWrap.sh"
  34 +EAStep()
  35 +{
  36 + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
  37 + if [ $? -ne 0 ]
  38 + then
  39 + exit
  40 + fi
  41 +}
  42 +
  43 +# pre-commands:
  44 +/bin/touch .init_design.begin.rst
  45 +EAStep vivado -log Afficheur_7SEG.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace
  46 +
  47 +
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/usage_statistics_webtalk.html 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/usage_statistics_webtalk.html
@@ -0,0 +1,616 @@ @@ -0,0 +1,616 @@
  1 +<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
  2 +<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
  3 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  4 + <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
  5 +<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
  6 + <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2552052</TD>
  7 +</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Wed Oct 4 15:36:14 2023</TD>
  8 + <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
  9 +</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2019.1 (64-bit)</TD>
  10 + <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>c3c29ee03ad240789b8a0cdeeb9c1f9b</TD>
  11 +</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>2</TD>
  12 + <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>6cd05f76f4a55b4793934a9f19deaa2b</TD>
  13 +</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>6cd05f76f4a55b4793934a9f19deaa2b</TD>
  14 + <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
  15 +</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7a35t</TD>
  16 + <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>artix7</TD>
  17 +</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>cpg236</TD>
  18 + <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
  19 +</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
  20 +</TR> </TABLE><BR>
  21 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  22 + <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
  23 +<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i5-8500 CPU @ 3.00GHz</TD>
  24 + <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>3000 MHz</TD>
  25 +</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Windows Server 2016 or Windows 10</TD>
  26 + <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release (build 9200)</TD>
  27 +</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>12.000 GB</TD>
  28 + <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
  29 +</TR> </TABLE><BR>
  30 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  31 + <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
  32 +<TR ALIGN='LEFT'> <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  33 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_handlers</B></TD></TR>
  34 +<TR ALIGN='LEFT'> <TD>basedialog_cancel=1</TD>
  35 + <TD>basedialog_ok=11</TD>
  36 + <TD>basedialog_yes=3</TD>
  37 + <TD>filesetpanel_file_set_panel_tree=6</TD>
  38 +</TR><TR ALIGN='LEFT'> <TD>filtertoolbar_hide_all=1</TD>
  39 + <TD>filtertoolbar_show_all=2</TD>
  40 + <TD>flownavigatortreepanel_flow_navigator_tree=17</TD>
  41 + <TD>gettingstartedview_open_project=2</TD>
  42 +</TR><TR ALIGN='LEFT'> <TD>launchpanel_dont_show_this_dialog_again=1</TD>
  43 + <TD>logmonitor_monitor=12</TD>
  44 + <TD>maintoolbarmgr_run=9</TD>
  45 + <TD>messagewithoptiondialog_dont_show_this_dialog_again=6</TD>
  46 +</TR><TR ALIGN='LEFT'> <TD>msgtreepanel_message_view_tree=4</TD>
  47 + <TD>msgview_clear_messages_resulting_from_user_executed=5</TD>
  48 + <TD>msgview_information_messages=1</TD>
  49 + <TD>numjobschooser_number_of_jobs=1</TD>
  50 +</TR><TR ALIGN='LEFT'> <TD>pacommandnames_auto_connect_target=1</TD>
  51 + <TD>pacommandnames_run_bitgen=2</TD>
  52 + <TD>pacommandnames_run_implementation=3</TD>
  53 + <TD>pacommandnames_run_synthesis=6</TD>
  54 +</TR><TR ALIGN='LEFT'> <TD>paviews_project_summary=1</TD>
  55 + <TD>paviews_schematic=2</TD>
  56 + <TD>programdebugtab_program_device=1</TD>
  57 + <TD>programfpgadialog_program=1</TD>
  58 +</TR><TR ALIGN='LEFT'> <TD>projecttab_reload=1</TD>
  59 + <TD>rdicommands_line_comment=3</TD>
  60 + <TD>saveprojectutils_save=3</TD>
  61 +</TR> </TABLE>
  62 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  63 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
  64 +<TR ALIGN='LEFT'> <TD>autoconnecttarget=1</TD>
  65 + <TD>launchprogramfpga=1</TD>
  66 + <TD>openhardwaremanager=1</TD>
  67 + <TD>openproject=2</TD>
  68 +</TR><TR ALIGN='LEFT'> <TD>openrecenttarget=1</TD>
  69 + <TD>runbitgen=8</TD>
  70 + <TD>runimplementation=5</TD>
  71 + <TD>runschematic=2</TD>
  72 +</TR><TR ALIGN='LEFT'> <TD>runsynthesis=7</TD>
  73 + <TD>showview=3</TD>
  74 +</TR> </TABLE>
  75 +</TR><TR ALIGN='LEFT'> <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  76 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
  77 +<TR ALIGN='LEFT'> <TD>guimode=2</TD>
  78 +</TR> </TABLE>
  79 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  80 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
  81 +<TR ALIGN='LEFT'> <TD>constraintsetcount=1</TD>
  82 + <TD>core_container=false</TD>
  83 + <TD>currentimplrun=impl_1</TD>
  84 + <TD>currentsynthesisrun=synth_1</TD>
  85 +</TR><TR ALIGN='LEFT'> <TD>default_library=xil_defaultlib</TD>
  86 + <TD>designmode=RTL</TD>
  87 + <TD>export_simulation_activehdl=0</TD>
  88 + <TD>export_simulation_ies=0</TD>
  89 +</TR><TR ALIGN='LEFT'> <TD>export_simulation_modelsim=0</TD>
  90 + <TD>export_simulation_questa=0</TD>
  91 + <TD>export_simulation_riviera=0</TD>
  92 + <TD>export_simulation_vcs=0</TD>
  93 +</TR><TR ALIGN='LEFT'> <TD>export_simulation_xsim=0</TD>
  94 + <TD>implstrategy=Vivado Implementation Defaults</TD>
  95 + <TD>launch_simulation_activehdl=0</TD>
  96 + <TD>launch_simulation_ies=0</TD>
  97 +</TR><TR ALIGN='LEFT'> <TD>launch_simulation_modelsim=0</TD>
  98 + <TD>launch_simulation_questa=0</TD>
  99 + <TD>launch_simulation_riviera=0</TD>
  100 + <TD>launch_simulation_vcs=0</TD>
  101 +</TR><TR ALIGN='LEFT'> <TD>launch_simulation_xsim=0</TD>
  102 + <TD>simulator_language=Mixed</TD>
  103 + <TD>srcsetcount=1</TD>
  104 + <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
  105 +</TR><TR ALIGN='LEFT'> <TD>target_language=VHDL</TD>
  106 + <TD>target_simulator=XSim</TD>
  107 + <TD>totalimplruns=1</TD>
  108 + <TD>totalsynthesisruns=1</TD>
  109 +</TR> </TABLE>
  110 +</TR> </TABLE><BR>
  111 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  112 + <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
  113 + <TR><TD>
  114 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  115 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
  116 +<TR ALIGN='LEFT'> <TD>bufg=1</TD>
  117 + <TD>carry4=5</TD>
  118 + <TD>fdce=20</TD>
  119 + <TD>gnd=1</TD>
  120 +</TR><TR ALIGN='LEFT'> <TD>ibuf=2</TD>
  121 + <TD>lut1=1</TD>
  122 + <TD>lut2=7</TD>
  123 + <TD>obuf=11</TD>
  124 +</TR><TR ALIGN='LEFT'> <TD>vcc=1</TD>
  125 +</TR> </TABLE>
  126 + </TD></TR>
  127 + <TR><TD>
  128 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  129 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
  130 +<TR ALIGN='LEFT'> <TD>bufg=1</TD>
  131 + <TD>carry4=5</TD>
  132 + <TD>fdce=20</TD>
  133 + <TD>gnd=1</TD>
  134 +</TR><TR ALIGN='LEFT'> <TD>ibuf=2</TD>
  135 + <TD>lut1=1</TD>
  136 + <TD>lut2=7</TD>
  137 + <TD>obuf=11</TD>
  138 +</TR><TR ALIGN='LEFT'> <TD>vcc=1</TD>
  139 +</TR> </TABLE>
  140 + </TD></TR>
  141 + </TABLE><BR>
  142 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  143 + <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
  144 + <TR><TD>
  145 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  146 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
  147 +<TR ALIGN='LEFT'> <TD>-append=default::[not_specified]</TD>
  148 + <TD>-checks=default::[not_specified]</TD>
  149 + <TD>-fail_on=default::[not_specified]</TD>
  150 + <TD>-force=default::[not_specified]</TD>
  151 +</TR><TR ALIGN='LEFT'> <TD>-format=default::[not_specified]</TD>
  152 + <TD>-internal=default::[not_specified]</TD>
  153 + <TD>-internal_only=default::[not_specified]</TD>
  154 + <TD>-messages=default::[not_specified]</TD>
  155 +</TR><TR ALIGN='LEFT'> <TD>-name=default::[not_specified]</TD>
  156 + <TD>-no_waivers=default::[not_specified]</TD>
  157 + <TD>-return_string=default::[not_specified]</TD>
  158 + <TD>-ruledecks=default::[not_specified]</TD>
  159 +</TR><TR ALIGN='LEFT'> <TD>-upgrade_cw=default::[not_specified]</TD>
  160 + <TD>-waived=default::[not_specified]</TD>
  161 +</TR> </TABLE>
  162 + </TD></TR>
  163 + </TABLE><BR>
  164 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  165 + <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_methodology</B></TD></TR>
  166 + <TR><TD>
  167 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  168 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
  169 +<TR ALIGN='LEFT'> <TD>-append=default::[not_specified]</TD>
  170 + <TD>-checks=default::[not_specified]</TD>
  171 + <TD>-fail_on=default::[not_specified]</TD>
  172 + <TD>-force=default::[not_specified]</TD>
  173 +</TR><TR ALIGN='LEFT'> <TD>-format=default::[not_specified]</TD>
  174 + <TD>-messages=default::[not_specified]</TD>
  175 + <TD>-name=default::[not_specified]</TD>
  176 + <TD>-return_string=default::[not_specified]</TD>
  177 +</TR><TR ALIGN='LEFT'> <TD>-slack_lesser_than=default::[not_specified]</TD>
  178 + <TD>-waived=default::[not_specified]</TD>
  179 +</TR> </TABLE>
  180 + </TD></TR>
  181 + <TR><TD>
  182 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  183 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
  184 +<TR ALIGN='LEFT'> <TD>timing-17=20</TD>
  185 +</TR> </TABLE>
  186 + </TD></TR>
  187 + </TABLE><BR>
  188 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  189 + <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_power</B></TD></TR>
  190 + <TR><TD>
  191 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  192 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
  193 +<TR ALIGN='LEFT'> <TD>-advisory=default::[not_specified]</TD>
  194 + <TD>-append=default::[not_specified]</TD>
  195 + <TD>-file=[specified]</TD>
  196 + <TD>-format=default::text</TD>
  197 +</TR><TR ALIGN='LEFT'> <TD>-hier=default::power</TD>
  198 + <TD>-hierarchical_depth=default::4</TD>
  199 + <TD>-l=default::[not_specified]</TD>
  200 + <TD>-name=default::[not_specified]</TD>
  201 +</TR><TR ALIGN='LEFT'> <TD>-no_propagation=default::[not_specified]</TD>
  202 + <TD>-return_string=default::[not_specified]</TD>
  203 + <TD>-rpx=[specified]</TD>
  204 + <TD>-verbose=default::[not_specified]</TD>
  205 +</TR><TR ALIGN='LEFT'> <TD>-vid=default::[not_specified]</TD>
  206 + <TD>-xpe=default::[not_specified]</TD>
  207 +</TR> </TABLE>
  208 + </TD></TR>
  209 + <TR><TD>
  210 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  211 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
  212 +<TR ALIGN='LEFT'> <TD>airflow=250 (LFM)</TD>
  213 + <TD>ambient_temp=25.0 (C)</TD>
  214 + <TD>bi-dir_toggle=12.500000</TD>
  215 + <TD>bidir_output_enable=1.000000</TD>
  216 +</TR><TR ALIGN='LEFT'> <TD>board_layers=12to15 (12 to 15 Layers)</TD>
  217 + <TD>board_selection=medium (10&quot;x10&quot;)</TD>
  218 + <TD>confidence_level_clock_activity=Low</TD>
  219 + <TD>confidence_level_design_state=High</TD>
  220 +</TR><TR ALIGN='LEFT'> <TD>confidence_level_device_models=High</TD>
  221 + <TD>confidence_level_internal_activity=Medium</TD>
  222 + <TD>confidence_level_io_activity=Low</TD>
  223 + <TD>confidence_level_overall=Low</TD>
  224 +</TR><TR ALIGN='LEFT'> <TD>customer=TBD</TD>
  225 + <TD>customer_class=TBD</TD>
  226 + <TD>devstatic=0.117417</TD>
  227 + <TD>die=xc7a35tcpg236-1</TD>
  228 +</TR><TR ALIGN='LEFT'> <TD>dsp_output_toggle=12.500000</TD>
  229 + <TD>dynamic=8.175883</TD>
  230 + <TD>effective_thetaja=5.0</TD>
  231 + <TD>enable_probability=0.990000</TD>
  232 +</TR><TR ALIGN='LEFT'> <TD>family=artix7</TD>
  233 + <TD>ff_toggle=12.500000</TD>
  234 + <TD>flow_state=routed</TD>
  235 + <TD>heatsink=medium (Medium Profile)</TD>
  236 +</TR><TR ALIGN='LEFT'> <TD>i/o=8.021022</TD>
  237 + <TD>input_toggle=12.500000</TD>
  238 + <TD>junction_temp=66.5 (C)</TD>
  239 + <TD>logic=0.041129</TD>
  240 +</TR><TR ALIGN='LEFT'> <TD>mgtavcc_dynamic_current=0.000000</TD>
  241 + <TD>mgtavcc_static_current=0.000000</TD>
  242 + <TD>mgtavcc_total_current=0.000000</TD>
  243 + <TD>mgtavcc_voltage=1.000000</TD>
  244 +</TR><TR ALIGN='LEFT'> <TD>mgtavtt_dynamic_current=0.000000</TD>
  245 + <TD>mgtavtt_static_current=0.000000</TD>
  246 + <TD>mgtavtt_total_current=0.000000</TD>
  247 + <TD>mgtavtt_voltage=1.200000</TD>
  248 +</TR><TR ALIGN='LEFT'> <TD>netlist_net_matched=NA</TD>
  249 + <TD>off-chip_power=0.000000</TD>
  250 + <TD>on-chip_power=8.293299</TD>
  251 + <TD>output_enable=1.000000</TD>
  252 +</TR><TR ALIGN='LEFT'> <TD>output_load=5.000000</TD>
  253 + <TD>output_toggle=12.500000</TD>
  254 + <TD>package=cpg236</TD>
  255 + <TD>pct_clock_constrained=1.000000</TD>
  256 +</TR><TR ALIGN='LEFT'> <TD>pct_inputs_defined=0</TD>
  257 + <TD>platform=nt64</TD>
  258 + <TD>process=typical</TD>
  259 + <TD>ram_enable=50.000000</TD>
  260 +</TR><TR ALIGN='LEFT'> <TD>ram_write=50.000000</TD>
  261 + <TD>read_saif=False</TD>
  262 + <TD>set/reset_probability=0.000000</TD>
  263 + <TD>signal_rate=False</TD>
  264 +</TR><TR ALIGN='LEFT'> <TD>signals=0.113732</TD>
  265 + <TD>simulation_file=None</TD>
  266 + <TD>speedgrade=-1</TD>
  267 + <TD>static_prob=False</TD>
  268 +</TR><TR ALIGN='LEFT'> <TD>temp_grade=commercial</TD>
  269 + <TD>thetajb=7.5 (C/W)</TD>
  270 + <TD>thetasa=4.6 (C/W)</TD>
  271 + <TD>toggle_rate=False</TD>
  272 +</TR><TR ALIGN='LEFT'> <TD>user_board_temp=25.0 (C)</TD>
  273 + <TD>user_effective_thetaja=5.0</TD>
  274 + <TD>user_junc_temp=66.5 (C)</TD>
  275 + <TD>user_thetajb=7.5 (C/W)</TD>
  276 +</TR><TR ALIGN='LEFT'> <TD>user_thetasa=4.6 (C/W)</TD>
  277 + <TD>vccadc_dynamic_current=0.000000</TD>
  278 + <TD>vccadc_static_current=0.020000</TD>
  279 + <TD>vccadc_total_current=0.020000</TD>
  280 +</TR><TR ALIGN='LEFT'> <TD>vccadc_voltage=1.800000</TD>
  281 + <TD>vccaux_dynamic_current=0.293778</TD>
  282 + <TD>vccaux_io_dynamic_current=0.000000</TD>
  283 + <TD>vccaux_io_static_current=0.000000</TD>
  284 +</TR><TR ALIGN='LEFT'> <TD>vccaux_io_total_current=0.000000</TD>
  285 + <TD>vccaux_io_voltage=1.800000</TD>
  286 + <TD>vccaux_static_current=0.016636</TD>
  287 + <TD>vccaux_total_current=0.310414</TD>
  288 +</TR><TR ALIGN='LEFT'> <TD>vccaux_voltage=1.800000</TD>
  289 + <TD>vccbram_dynamic_current=0.000000</TD>
  290 + <TD>vccbram_static_current=0.000967</TD>
  291 + <TD>vccbram_total_current=0.000967</TD>
  292 +</TR><TR ALIGN='LEFT'> <TD>vccbram_voltage=1.000000</TD>
  293 + <TD>vccint_dynamic_current=0.158861</TD>
  294 + <TD>vccint_static_current=0.047205</TD>
  295 + <TD>vccint_total_current=0.206066</TD>
  296 +</TR><TR ALIGN='LEFT'> <TD>vccint_voltage=1.000000</TD>
  297 + <TD>vcco12_dynamic_current=0.000000</TD>
  298 + <TD>vcco12_static_current=0.000000</TD>
  299 + <TD>vcco12_total_current=0.000000</TD>
  300 +</TR><TR ALIGN='LEFT'> <TD>vcco12_voltage=1.200000</TD>
  301 + <TD>vcco135_dynamic_current=0.000000</TD>
  302 + <TD>vcco135_static_current=0.000000</TD>
  303 + <TD>vcco135_total_current=0.000000</TD>
  304 +</TR><TR ALIGN='LEFT'> <TD>vcco135_voltage=1.350000</TD>
  305 + <TD>vcco15_dynamic_current=0.000000</TD>
  306 + <TD>vcco15_static_current=0.000000</TD>
  307 + <TD>vcco15_total_current=0.000000</TD>
  308 +</TR><TR ALIGN='LEFT'> <TD>vcco15_voltage=1.500000</TD>
  309 + <TD>vcco18_dynamic_current=0.000000</TD>
  310 + <TD>vcco18_static_current=0.000000</TD>
  311 + <TD>vcco18_total_current=0.000000</TD>
  312 +</TR><TR ALIGN='LEFT'> <TD>vcco18_voltage=1.800000</TD>
  313 + <TD>vcco25_dynamic_current=0.000000</TD>
  314 + <TD>vcco25_static_current=0.000000</TD>
  315 + <TD>vcco25_total_current=0.000000</TD>
  316 +</TR><TR ALIGN='LEFT'> <TD>vcco25_voltage=2.500000</TD>
  317 + <TD>vcco33_dynamic_current=2.269158</TD>
  318 + <TD>vcco33_static_current=0.001000</TD>
  319 + <TD>vcco33_total_current=2.270158</TD>
  320 +</TR><TR ALIGN='LEFT'> <TD>vcco33_voltage=3.300000</TD>
  321 + <TD>version=2019.1</TD>
  322 +</TR> </TABLE>
  323 + </TD></TR>
  324 + </TABLE><BR>
  325 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  326 + <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
  327 + <TR><TD>
  328 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  329 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
  330 +<TR ALIGN='LEFT'> <TD>bufgctrl_available=32</TD>
  331 + <TD>bufgctrl_fixed=0</TD>
  332 + <TD>bufgctrl_used=1</TD>
  333 + <TD>bufgctrl_util_percentage=3.13</TD>
  334 +</TR><TR ALIGN='LEFT'> <TD>bufhce_available=72</TD>
  335 + <TD>bufhce_fixed=0</TD>
  336 + <TD>bufhce_used=0</TD>
  337 + <TD>bufhce_util_percentage=0.00</TD>
  338 +</TR><TR ALIGN='LEFT'> <TD>bufio_available=20</TD>
  339 + <TD>bufio_fixed=0</TD>
  340 + <TD>bufio_used=0</TD>
  341 + <TD>bufio_util_percentage=0.00</TD>
  342 +</TR><TR ALIGN='LEFT'> <TD>bufmrce_available=10</TD>
  343 + <TD>bufmrce_fixed=0</TD>
  344 + <TD>bufmrce_used=0</TD>
  345 + <TD>bufmrce_util_percentage=0.00</TD>
  346 +</TR><TR ALIGN='LEFT'> <TD>bufr_available=20</TD>
  347 + <TD>bufr_fixed=0</TD>
  348 + <TD>bufr_used=0</TD>
  349 + <TD>bufr_util_percentage=0.00</TD>
  350 +</TR><TR ALIGN='LEFT'> <TD>mmcme2_adv_available=5</TD>
  351 + <TD>mmcme2_adv_fixed=0</TD>
  352 + <TD>mmcme2_adv_used=0</TD>
  353 + <TD>mmcme2_adv_util_percentage=0.00</TD>
  354 +</TR><TR ALIGN='LEFT'> <TD>plle2_adv_available=5</TD>
  355 + <TD>plle2_adv_fixed=0</TD>
  356 + <TD>plle2_adv_used=0</TD>
  357 + <TD>plle2_adv_util_percentage=0.00</TD>
  358 +</TR> </TABLE>
  359 + </TD></TR>
  360 + <TR><TD>
  361 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  362 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
  363 +<TR ALIGN='LEFT'> <TD>dsps_available=90</TD>
  364 + <TD>dsps_fixed=0</TD>
  365 + <TD>dsps_used=0</TD>
  366 + <TD>dsps_util_percentage=0.00</TD>
  367 +</TR> </TABLE>
  368 + </TD></TR>
  369 + <TR><TD>
  370 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  371 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
  372 +<TR ALIGN='LEFT'> <TD>blvds_25=0</TD>
  373 + <TD>diff_hstl_i=0</TD>
  374 + <TD>diff_hstl_i_18=0</TD>
  375 + <TD>diff_hstl_ii=0</TD>
  376 +</TR><TR ALIGN='LEFT'> <TD>diff_hstl_ii_18=0</TD>
  377 + <TD>diff_hsul_12=0</TD>
  378 + <TD>diff_mobile_ddr=0</TD>
  379 + <TD>diff_sstl135=0</TD>
  380 +</TR><TR ALIGN='LEFT'> <TD>diff_sstl135_r=0</TD>
  381 + <TD>diff_sstl15=0</TD>
  382 + <TD>diff_sstl15_r=0</TD>
  383 + <TD>diff_sstl18_i=0</TD>
  384 +</TR><TR ALIGN='LEFT'> <TD>diff_sstl18_ii=0</TD>
  385 + <TD>hstl_i=0</TD>
  386 + <TD>hstl_i_18=0</TD>
  387 + <TD>hstl_ii=0</TD>
  388 +</TR><TR ALIGN='LEFT'> <TD>hstl_ii_18=0</TD>
  389 + <TD>hsul_12=0</TD>
  390 + <TD>lvcmos12=0</TD>
  391 + <TD>lvcmos15=0</TD>
  392 +</TR><TR ALIGN='LEFT'> <TD>lvcmos18=0</TD>
  393 + <TD>lvcmos25=0</TD>
  394 + <TD>lvcmos33=1</TD>
  395 + <TD>lvds_25=0</TD>
  396 +</TR><TR ALIGN='LEFT'> <TD>lvttl=0</TD>
  397 + <TD>mini_lvds_25=0</TD>
  398 + <TD>mobile_ddr=0</TD>
  399 + <TD>pci33_3=0</TD>
  400 +</TR><TR ALIGN='LEFT'> <TD>ppds_25=0</TD>
  401 + <TD>rsds_25=0</TD>
  402 + <TD>sstl135=0</TD>
  403 + <TD>sstl135_r=0</TD>
  404 +</TR><TR ALIGN='LEFT'> <TD>sstl15=0</TD>
  405 + <TD>sstl15_r=0</TD>
  406 + <TD>sstl18_i=0</TD>
  407 + <TD>sstl18_ii=0</TD>
  408 +</TR><TR ALIGN='LEFT'> <TD>tmds_33=0</TD>
  409 +</TR> </TABLE>
  410 + </TD></TR>
  411 + <TR><TD>
  412 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  413 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
  414 +<TR ALIGN='LEFT'> <TD>block_ram_tile_available=50</TD>
  415 + <TD>block_ram_tile_fixed=0</TD>
  416 + <TD>block_ram_tile_used=0</TD>
  417 + <TD>block_ram_tile_util_percentage=0.00</TD>
  418 +</TR><TR ALIGN='LEFT'> <TD>ramb18_available=100</TD>
  419 + <TD>ramb18_fixed=0</TD>
  420 + <TD>ramb18_used=0</TD>
  421 + <TD>ramb18_util_percentage=0.00</TD>
  422 +</TR><TR ALIGN='LEFT'> <TD>ramb36_fifo_available=50</TD>
  423 + <TD>ramb36_fifo_fixed=0</TD>
  424 + <TD>ramb36_fifo_used=0</TD>
  425 + <TD>ramb36_fifo_util_percentage=0.00</TD>
  426 +</TR> </TABLE>
  427 + </TD></TR>
  428 + <TR><TD>
  429 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  430 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
  431 +<TR ALIGN='LEFT'> <TD>bufg_functional_category=Clock</TD>
  432 + <TD>bufg_used=1</TD>
  433 + <TD>carry4_functional_category=CarryLogic</TD>
  434 + <TD>carry4_used=5</TD>
  435 +</TR><TR ALIGN='LEFT'> <TD>fdce_functional_category=Flop &amp; Latch</TD>
  436 + <TD>fdce_used=20</TD>
  437 + <TD>ibuf_functional_category=IO</TD>
  438 + <TD>ibuf_used=2</TD>
  439 +</TR><TR ALIGN='LEFT'> <TD>lut1_functional_category=LUT</TD>
  440 + <TD>lut1_used=1</TD>
  441 + <TD>lut2_functional_category=LUT</TD>
  442 + <TD>lut2_used=7</TD>
  443 +</TR><TR ALIGN='LEFT'> <TD>obuf_functional_category=IO</TD>
  444 + <TD>obuf_used=11</TD>
  445 +</TR> </TABLE>
  446 + </TD></TR>
  447 + <TR><TD>
  448 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  449 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
  450 +<TR ALIGN='LEFT'> <TD>f7_muxes_available=16300</TD>
  451 + <TD>f7_muxes_fixed=0</TD>
  452 + <TD>f7_muxes_used=0</TD>
  453 + <TD>f7_muxes_util_percentage=0.00</TD>
  454 +</TR><TR ALIGN='LEFT'> <TD>f8_muxes_available=8150</TD>
  455 + <TD>f8_muxes_fixed=0</TD>
  456 + <TD>f8_muxes_used=0</TD>
  457 + <TD>f8_muxes_util_percentage=0.00</TD>
  458 +</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_available=20800</TD>
  459 + <TD>lut_as_logic_fixed=0</TD>
  460 + <TD>lut_as_logic_used=5</TD>
  461 + <TD>lut_as_logic_util_percentage=0.02</TD>
  462 +</TR><TR ALIGN='LEFT'> <TD>lut_as_memory_available=9600</TD>
  463 + <TD>lut_as_memory_fixed=0</TD>
  464 + <TD>lut_as_memory_used=0</TD>
  465 + <TD>lut_as_memory_util_percentage=0.00</TD>
  466 +</TR><TR ALIGN='LEFT'> <TD>register_as_flip_flop_available=41600</TD>
  467 + <TD>register_as_flip_flop_fixed=0</TD>
  468 + <TD>register_as_flip_flop_used=20</TD>
  469 + <TD>register_as_flip_flop_util_percentage=0.05</TD>
  470 +</TR><TR ALIGN='LEFT'> <TD>register_as_latch_available=41600</TD>
  471 + <TD>register_as_latch_fixed=0</TD>
  472 + <TD>register_as_latch_used=0</TD>
  473 + <TD>register_as_latch_util_percentage=0.00</TD>
  474 +</TR><TR ALIGN='LEFT'> <TD>slice_luts_available=20800</TD>
  475 + <TD>slice_luts_fixed=0</TD>
  476 + <TD>slice_luts_used=5</TD>
  477 + <TD>slice_luts_util_percentage=0.02</TD>
  478 +</TR><TR ALIGN='LEFT'> <TD>slice_registers_available=41600</TD>
  479 + <TD>slice_registers_fixed=0</TD>
  480 + <TD>slice_registers_used=20</TD>
  481 + <TD>slice_registers_util_percentage=0.05</TD>
  482 +</TR><TR ALIGN='LEFT'> <TD>lut_as_distributed_ram_fixed=0</TD>
  483 + <TD>lut_as_distributed_ram_used=0</TD>
  484 + <TD>lut_as_logic_available=20800</TD>
  485 + <TD>lut_as_logic_fixed=0</TD>
  486 +</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_used=5</TD>
  487 + <TD>lut_as_logic_util_percentage=0.02</TD>
  488 + <TD>lut_as_memory_available=9600</TD>
  489 + <TD>lut_as_memory_fixed=0</TD>
  490 +</TR><TR ALIGN='LEFT'> <TD>lut_as_memory_used=0</TD>
  491 + <TD>lut_as_memory_util_percentage=0.00</TD>
  492 + <TD>lut_as_shift_register_fixed=0</TD>
  493 + <TD>lut_as_shift_register_used=0</TD>
  494 +</TR><TR ALIGN='LEFT'> <TD>register_driven_from_outside_the_slice_fixed=0</TD>
  495 + <TD>register_driven_from_outside_the_slice_used=0</TD>
  496 + <TD>register_driven_from_within_the_slice_fixed=0</TD>
  497 + <TD>register_driven_from_within_the_slice_used=20</TD>
  498 +</TR><TR ALIGN='LEFT'> <TD>slice_available=8150</TD>
  499 + <TD>slice_fixed=0</TD>
  500 + <TD>slice_registers_available=41600</TD>
  501 + <TD>slice_registers_fixed=0</TD>
  502 +</TR><TR ALIGN='LEFT'> <TD>slice_registers_used=20</TD>
  503 + <TD>slice_registers_util_percentage=0.05</TD>
  504 + <TD>slice_used=6</TD>
  505 + <TD>slice_util_percentage=0.07</TD>
  506 +</TR><TR ALIGN='LEFT'> <TD>slicel_fixed=0</TD>
  507 + <TD>slicel_used=6</TD>
  508 + <TD>slicem_fixed=0</TD>
  509 + <TD>slicem_used=0</TD>
  510 +</TR><TR ALIGN='LEFT'> <TD>unique_control_sets_available=8150</TD>
  511 + <TD>unique_control_sets_fixed=8150</TD>
  512 + <TD>unique_control_sets_used=1</TD>
  513 + <TD>unique_control_sets_util_percentage=0.01</TD>
  514 +</TR><TR ALIGN='LEFT'> <TD>using_o5_and_o6_fixed=0.01</TD>
  515 + <TD>using_o5_and_o6_used=3</TD>
  516 + <TD>using_o5_output_only_fixed=3</TD>
  517 + <TD>using_o5_output_only_used=0</TD>
  518 +</TR><TR ALIGN='LEFT'> <TD>using_o6_output_only_fixed=0</TD>
  519 + <TD>using_o6_output_only_used=2</TD>
  520 +</TR> </TABLE>
  521 + </TD></TR>
  522 + <TR><TD>
  523 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  524 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
  525 +<TR ALIGN='LEFT'> <TD>bscane2_available=4</TD>
  526 + <TD>bscane2_fixed=0</TD>
  527 + <TD>bscane2_used=0</TD>
  528 + <TD>bscane2_util_percentage=0.00</TD>
  529 +</TR><TR ALIGN='LEFT'> <TD>capturee2_available=1</TD>
  530 + <TD>capturee2_fixed=0</TD>
  531 + <TD>capturee2_used=0</TD>
  532 + <TD>capturee2_util_percentage=0.00</TD>
  533 +</TR><TR ALIGN='LEFT'> <TD>dna_port_available=1</TD>
  534 + <TD>dna_port_fixed=0</TD>
  535 + <TD>dna_port_used=0</TD>
  536 + <TD>dna_port_util_percentage=0.00</TD>
  537 +</TR><TR ALIGN='LEFT'> <TD>efuse_usr_available=1</TD>
  538 + <TD>efuse_usr_fixed=0</TD>
  539 + <TD>efuse_usr_used=0</TD>
  540 + <TD>efuse_usr_util_percentage=0.00</TD>
  541 +</TR><TR ALIGN='LEFT'> <TD>frame_ecce2_available=1</TD>
  542 + <TD>frame_ecce2_fixed=0</TD>
  543 + <TD>frame_ecce2_used=0</TD>
  544 + <TD>frame_ecce2_util_percentage=0.00</TD>
  545 +</TR><TR ALIGN='LEFT'> <TD>icape2_available=2</TD>
  546 + <TD>icape2_fixed=0</TD>
  547 + <TD>icape2_used=0</TD>
  548 + <TD>icape2_util_percentage=0.00</TD>
  549 +</TR><TR ALIGN='LEFT'> <TD>pcie_2_1_available=1</TD>
  550 + <TD>pcie_2_1_fixed=0</TD>
  551 + <TD>pcie_2_1_used=0</TD>
  552 + <TD>pcie_2_1_util_percentage=0.00</TD>
  553 +</TR><TR ALIGN='LEFT'> <TD>startupe2_available=1</TD>
  554 + <TD>startupe2_fixed=0</TD>
  555 + <TD>startupe2_used=0</TD>
  556 + <TD>startupe2_util_percentage=0.00</TD>
  557 +</TR><TR ALIGN='LEFT'> <TD>xadc_available=1</TD>
  558 + <TD>xadc_fixed=0</TD>
  559 + <TD>xadc_used=0</TD>
  560 + <TD>xadc_util_percentage=0.00</TD>
  561 +</TR> </TABLE>
  562 + </TD></TR>
  563 + </TABLE><BR>
  564 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  565 + <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
  566 + <TR><TD>
  567 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  568 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
  569 +<TR ALIGN='LEFT'> <TD>-assert=default::[not_specified]</TD>
  570 + <TD>-bufg=default::12</TD>
  571 + <TD>-cascade_dsp=default::auto</TD>
  572 + <TD>-constrset=default::[not_specified]</TD>
  573 +</TR><TR ALIGN='LEFT'> <TD>-control_set_opt_threshold=default::auto</TD>
  574 + <TD>-directive=default::default</TD>
  575 + <TD>-fanout_limit=default::10000</TD>
  576 + <TD>-flatten_hierarchy=default::rebuilt</TD>
  577 +</TR><TR ALIGN='LEFT'> <TD>-fsm_extraction=default::auto</TD>
  578 + <TD>-gated_clock_conversion=default::off</TD>
  579 + <TD>-generic=default::[not_specified]</TD>
  580 + <TD>-include_dirs=default::[not_specified]</TD>
  581 +</TR><TR ALIGN='LEFT'> <TD>-keep_equivalent_registers=default::[not_specified]</TD>
  582 + <TD>-max_bram=default::-1</TD>
  583 + <TD>-max_bram_cascade_height=default::-1</TD>
  584 + <TD>-max_dsp=default::-1</TD>
  585 +</TR><TR ALIGN='LEFT'> <TD>-max_uram=default::-1</TD>
  586 + <TD>-max_uram_cascade_height=default::-1</TD>
  587 + <TD>-mode=default::default</TD>
  588 + <TD>-name=default::[not_specified]</TD>
  589 +</TR><TR ALIGN='LEFT'> <TD>-no_lc=default::[not_specified]</TD>
  590 + <TD>-no_srlextract=default::[not_specified]</TD>
  591 + <TD>-no_timing_driven=default::[not_specified]</TD>
  592 + <TD>-part=xc7a35tcpg236-1</TD>
  593 +</TR><TR ALIGN='LEFT'> <TD>-resource_sharing=default::auto</TD>
  594 + <TD>-retiming=default::[not_specified]</TD>
  595 + <TD>-rtl=default::[not_specified]</TD>
  596 + <TD>-rtl_skip_constraints=default::[not_specified]</TD>
  597 +</TR><TR ALIGN='LEFT'> <TD>-rtl_skip_ip=default::[not_specified]</TD>
  598 + <TD>-seu_protect=default::none</TD>
  599 + <TD>-sfcu=default::[not_specified]</TD>
  600 + <TD>-shreg_min_size=default::3</TD>
  601 +</TR><TR ALIGN='LEFT'> <TD>-top=Afficheur_7SEG</TD>
  602 + <TD>-verilog_define=default::[not_specified]</TD>
  603 +</TR> </TABLE>
  604 + </TD></TR>
  605 + <TR><TD>
  606 + <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  607 + <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
  608 +<TR ALIGN='LEFT'> <TD>elapsed=00:00:26s</TD>
  609 + <TD>hls_ip=0</TD>
  610 + <TD>memory_gain=600.383MB</TD>
  611 + <TD>memory_peak=908.391MB</TD>
  612 +</TR> </TABLE>
  613 + </TD></TR>
  614 + </TABLE><BR>
  615 +</BODY>
  616 +</HTML>
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/usage_statistics_webtalk.xml 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/usage_statistics_webtalk.xml
@@ -0,0 +1,556 @@ @@ -0,0 +1,556 @@
  1 +<?xml version="1.0" encoding="UTF-8" ?>
  2 +<webTalkData fileName='usage_statistics_webtalk.xml' majorVersion='1' minorVersion='0' timeStamp='Wed Oct 4 15:36:14 2023'>
  3 +<section name="__ROOT__" level="0" order="1" description="">
  4 + <section name="software_version_and_target_device" level="1" order="1" description="">
  5 + <keyValuePair key="beta" value="FALSE" description="" />
  6 + <keyValuePair key="build_version" value="2552052" description="" />
  7 + <keyValuePair key="date_generated" value="Wed Oct 4 15:36:14 2023" description="" />
  8 + <keyValuePair key="os_platform" value="WIN64" description="" />
  9 + <keyValuePair key="product_version" value="Vivado v2019.1 (64-bit)" description="" />
  10 + <keyValuePair key="project_id" value="c3c29ee03ad240789b8a0cdeeb9c1f9b" description="" />
  11 + <keyValuePair key="project_iteration" value="2" description="" />
  12 + <keyValuePair key="random_id" value="6cd05f76f4a55b4793934a9f19deaa2b" description="" />
  13 + <keyValuePair key="registration_id" value="6cd05f76f4a55b4793934a9f19deaa2b" description="" />
  14 + <keyValuePair key="route_design" value="TRUE" description="" />
  15 + <keyValuePair key="target_device" value="xc7a35t" description="" />
  16 + <keyValuePair key="target_family" value="artix7" description="" />
  17 + <keyValuePair key="target_package" value="cpg236" description="" />
  18 + <keyValuePair key="target_speed" value="-1" description="" />
  19 + <keyValuePair key="tool_flow" value="Vivado" description="" />
  20 + </section>
  21 + <section name="user_environment" level="1" order="2" description="">
  22 + <keyValuePair key="cpu_name" value="Intel(R) Core(TM) i5-8500 CPU @ 3.00GHz" description="" />
  23 + <keyValuePair key="cpu_speed" value="3000 MHz" description="" />
  24 + <keyValuePair key="os_name" value="Windows Server 2016 or Windows 10" description="" />
  25 + <keyValuePair key="os_release" value="major release (build 9200)" description="" />
  26 + <keyValuePair key="system_ram" value="12.000 GB" description="" />
  27 + <keyValuePair key="total_processors" value="1" description="" />
  28 + </section>
  29 + <section name="report_drc" level="1" order="3" description="">
  30 + <section name="command_line_options" level="2" order="1" description="">
  31 + <keyValuePair key="-append" value="default::[not_specified]" description="" />
  32 + <keyValuePair key="-checks" value="default::[not_specified]" description="" />
  33 + <keyValuePair key="-fail_on" value="default::[not_specified]" description="" />
  34 + <keyValuePair key="-force" value="default::[not_specified]" description="" />
  35 + <keyValuePair key="-format" value="default::[not_specified]" description="" />
  36 + <keyValuePair key="-internal" value="default::[not_specified]" description="" />
  37 + <keyValuePair key="-internal_only" value="default::[not_specified]" description="" />
  38 + <keyValuePair key="-messages" value="default::[not_specified]" description="" />
  39 + <keyValuePair key="-name" value="default::[not_specified]" description="" />
  40 + <keyValuePair key="-no_waivers" value="default::[not_specified]" description="" />
  41 + <keyValuePair key="-return_string" value="default::[not_specified]" description="" />
  42 + <keyValuePair key="-ruledecks" value="default::[not_specified]" description="" />
  43 + <keyValuePair key="-upgrade_cw" value="default::[not_specified]" description="" />
  44 + <keyValuePair key="-waived" value="default::[not_specified]" description="" />
  45 + </section>
  46 + </section>
  47 + <section name="report_methodology" level="1" order="4" description="">
  48 + <section name="command_line_options" level="2" order="1" description="">
  49 + <keyValuePair key="-append" value="default::[not_specified]" description="" />
  50 + <keyValuePair key="-checks" value="default::[not_specified]" description="" />
  51 + <keyValuePair key="-fail_on" value="default::[not_specified]" description="" />
  52 + <keyValuePair key="-force" value="default::[not_specified]" description="" />
  53 + <keyValuePair key="-format" value="default::[not_specified]" description="" />
  54 + <keyValuePair key="-messages" value="default::[not_specified]" description="" />
  55 + <keyValuePair key="-name" value="default::[not_specified]" description="" />
  56 + <keyValuePair key="-return_string" value="default::[not_specified]" description="" />
  57 + <keyValuePair key="-slack_lesser_than" value="default::[not_specified]" description="" />
  58 + <keyValuePair key="-waived" value="default::[not_specified]" description="" />
  59 + </section>
  60 + <section name="results" level="2" order="2" description="">
  61 + <keyValuePair key="timing-17" value="20" description="" />
  62 + </section>
  63 + </section>
  64 + <section name="report_power" level="1" order="5" description="">
  65 + <section name="command_line_options" level="2" order="1" description="">
  66 + <keyValuePair key="-advisory" value="default::[not_specified]" description="" />
  67 + <keyValuePair key="-append" value="default::[not_specified]" description="" />
  68 + <keyValuePair key="-file" value="[specified]" description="" />
  69 + <keyValuePair key="-format" value="default::text" description="" />
  70 + <keyValuePair key="-hier" value="default::power" description="" />
  71 + <keyValuePair key="-hierarchical_depth" value="default::4" description="" />
  72 + <keyValuePair key="-l" value="default::[not_specified]" description="" />
  73 + <keyValuePair key="-name" value="default::[not_specified]" description="" />
  74 + <keyValuePair key="-no_propagation" value="default::[not_specified]" description="" />
  75 + <keyValuePair key="-return_string" value="default::[not_specified]" description="" />
  76 + <keyValuePair key="-rpx" value="[specified]" description="" />
  77 + <keyValuePair key="-verbose" value="default::[not_specified]" description="" />
  78 + <keyValuePair key="-vid" value="default::[not_specified]" description="" />
  79 + <keyValuePair key="-xpe" value="default::[not_specified]" description="" />
  80 + </section>
  81 + <section name="usage" level="2" order="2" description="">
  82 + <keyValuePair key="airflow" value="250 (LFM)" description="" />
  83 + <keyValuePair key="ambient_temp" value="25.0 (C)" description="" />
  84 + <keyValuePair key="bi-dir_toggle" value="12.500000" description="" />
  85 + <keyValuePair key="bidir_output_enable" value="1.000000" description="" />
  86 + <keyValuePair key="board_layers" value="12to15 (12 to 15 Layers)" description="" />
  87 + <keyValuePair key="board_selection" value="medium (10&quot;x10&quot;)" description="" />
  88 + <keyValuePair key="confidence_level_clock_activity" value="Low" description="" />
  89 + <keyValuePair key="confidence_level_design_state" value="High" description="" />
  90 + <keyValuePair key="confidence_level_device_models" value="High" description="" />
  91 + <keyValuePair key="confidence_level_internal_activity" value="Medium" description="" />
  92 + <keyValuePair key="confidence_level_io_activity" value="Low" description="" />
  93 + <keyValuePair key="confidence_level_overall" value="Low" description="" />
  94 + <keyValuePair key="customer" value="TBD" description="" />
  95 + <keyValuePair key="customer_class" value="TBD" description="" />
  96 + <keyValuePair key="devstatic" value="0.117417" description="" />
  97 + <keyValuePair key="die" value="xc7a35tcpg236-1" description="" />
  98 + <keyValuePair key="dsp_output_toggle" value="12.500000" description="" />
  99 + <keyValuePair key="dynamic" value="8.175883" description="" />
  100 + <keyValuePair key="effective_thetaja" value="5.0" description="" />
  101 + <keyValuePair key="enable_probability" value="0.990000" description="" />
  102 + <keyValuePair key="family" value="artix7" description="" />
  103 + <keyValuePair key="ff_toggle" value="12.500000" description="" />
  104 + <keyValuePair key="flow_state" value="routed" description="" />
  105 + <keyValuePair key="heatsink" value="medium (Medium Profile)" description="" />
  106 + <keyValuePair key="i/o" value="8.021022" description="" />
  107 + <keyValuePair key="input_toggle" value="12.500000" description="" />
  108 + <keyValuePair key="junction_temp" value="66.5 (C)" description="" />
  109 + <keyValuePair key="logic" value="0.041129" description="" />
  110 + <keyValuePair key="mgtavcc_dynamic_current" value="0.000000" description="" />
  111 + <keyValuePair key="mgtavcc_static_current" value="0.000000" description="" />
  112 + <keyValuePair key="mgtavcc_total_current" value="0.000000" description="" />
  113 + <keyValuePair key="mgtavcc_voltage" value="1.000000" description="" />
  114 + <keyValuePair key="mgtavtt_dynamic_current" value="0.000000" description="" />
  115 + <keyValuePair key="mgtavtt_static_current" value="0.000000" description="" />
  116 + <keyValuePair key="mgtavtt_total_current" value="0.000000" description="" />
  117 + <keyValuePair key="mgtavtt_voltage" value="1.200000" description="" />
  118 + <keyValuePair key="netlist_net_matched" value="NA" description="" />
  119 + <keyValuePair key="off-chip_power" value="0.000000" description="" />
  120 + <keyValuePair key="on-chip_power" value="8.293299" description="" />
  121 + <keyValuePair key="output_enable" value="1.000000" description="" />
  122 + <keyValuePair key="output_load" value="5.000000" description="" />
  123 + <keyValuePair key="output_toggle" value="12.500000" description="" />
  124 + <keyValuePair key="package" value="cpg236" description="" />
  125 + <keyValuePair key="pct_clock_constrained" value="1.000000" description="" />
  126 + <keyValuePair key="pct_inputs_defined" value="0" description="" />
  127 + <keyValuePair key="platform" value="nt64" description="" />
  128 + <keyValuePair key="process" value="typical" description="" />
  129 + <keyValuePair key="ram_enable" value="50.000000" description="" />
  130 + <keyValuePair key="ram_write" value="50.000000" description="" />
  131 + <keyValuePair key="read_saif" value="False" description="" />
  132 + <keyValuePair key="set/reset_probability" value="0.000000" description="" />
  133 + <keyValuePair key="signal_rate" value="False" description="" />
  134 + <keyValuePair key="signals" value="0.113732" description="" />
  135 + <keyValuePair key="simulation_file" value="None" description="" />
  136 + <keyValuePair key="speedgrade" value="-1" description="" />
  137 + <keyValuePair key="static_prob" value="False" description="" />
  138 + <keyValuePair key="temp_grade" value="commercial" description="" />
  139 + <keyValuePair key="thetajb" value="7.5 (C/W)" description="" />
  140 + <keyValuePair key="thetasa" value="4.6 (C/W)" description="" />
  141 + <keyValuePair key="toggle_rate" value="False" description="" />
  142 + <keyValuePair key="user_board_temp" value="25.0 (C)" description="" />
  143 + <keyValuePair key="user_effective_thetaja" value="5.0" description="" />
  144 + <keyValuePair key="user_junc_temp" value="66.5 (C)" description="" />
  145 + <keyValuePair key="user_thetajb" value="7.5 (C/W)" description="" />
  146 + <keyValuePair key="user_thetasa" value="4.6 (C/W)" description="" />
  147 + <keyValuePair key="vccadc_dynamic_current" value="0.000000" description="" />
  148 + <keyValuePair key="vccadc_static_current" value="0.020000" description="" />
  149 + <keyValuePair key="vccadc_total_current" value="0.020000" description="" />
  150 + <keyValuePair key="vccadc_voltage" value="1.800000" description="" />
  151 + <keyValuePair key="vccaux_dynamic_current" value="0.293778" description="" />
  152 + <keyValuePair key="vccaux_io_dynamic_current" value="0.000000" description="" />
  153 + <keyValuePair key="vccaux_io_static_current" value="0.000000" description="" />
  154 + <keyValuePair key="vccaux_io_total_current" value="0.000000" description="" />
  155 + <keyValuePair key="vccaux_io_voltage" value="1.800000" description="" />
  156 + <keyValuePair key="vccaux_static_current" value="0.016636" description="" />
  157 + <keyValuePair key="vccaux_total_current" value="0.310414" description="" />
  158 + <keyValuePair key="vccaux_voltage" value="1.800000" description="" />
  159 + <keyValuePair key="vccbram_dynamic_current" value="0.000000" description="" />
  160 + <keyValuePair key="vccbram_static_current" value="0.000967" description="" />
  161 + <keyValuePair key="vccbram_total_current" value="0.000967" description="" />
  162 + <keyValuePair key="vccbram_voltage" value="1.000000" description="" />
  163 + <keyValuePair key="vccint_dynamic_current" value="0.158861" description="" />
  164 + <keyValuePair key="vccint_static_current" value="0.047205" description="" />
  165 + <keyValuePair key="vccint_total_current" value="0.206066" description="" />
  166 + <keyValuePair key="vccint_voltage" value="1.000000" description="" />
  167 + <keyValuePair key="vcco12_dynamic_current" value="0.000000" description="" />
  168 + <keyValuePair key="vcco12_static_current" value="0.000000" description="" />
  169 + <keyValuePair key="vcco12_total_current" value="0.000000" description="" />
  170 + <keyValuePair key="vcco12_voltage" value="1.200000" description="" />
  171 + <keyValuePair key="vcco135_dynamic_current" value="0.000000" description="" />
  172 + <keyValuePair key="vcco135_static_current" value="0.000000" description="" />
  173 + <keyValuePair key="vcco135_total_current" value="0.000000" description="" />
  174 + <keyValuePair key="vcco135_voltage" value="1.350000" description="" />
  175 + <keyValuePair key="vcco15_dynamic_current" value="0.000000" description="" />
  176 + <keyValuePair key="vcco15_static_current" value="0.000000" description="" />
  177 + <keyValuePair key="vcco15_total_current" value="0.000000" description="" />
  178 + <keyValuePair key="vcco15_voltage" value="1.500000" description="" />
  179 + <keyValuePair key="vcco18_dynamic_current" value="0.000000" description="" />
  180 + <keyValuePair key="vcco18_static_current" value="0.000000" description="" />
  181 + <keyValuePair key="vcco18_total_current" value="0.000000" description="" />
  182 + <keyValuePair key="vcco18_voltage" value="1.800000" description="" />
  183 + <keyValuePair key="vcco25_dynamic_current" value="0.000000" description="" />
  184 + <keyValuePair key="vcco25_static_current" value="0.000000" description="" />
  185 + <keyValuePair key="vcco25_total_current" value="0.000000" description="" />
  186 + <keyValuePair key="vcco25_voltage" value="2.500000" description="" />
  187 + <keyValuePair key="vcco33_dynamic_current" value="2.269158" description="" />
  188 + <keyValuePair key="vcco33_static_current" value="0.001000" description="" />
  189 + <keyValuePair key="vcco33_total_current" value="2.270158" description="" />
  190 + <keyValuePair key="vcco33_voltage" value="3.300000" description="" />
  191 + <keyValuePair key="version" value="2019.1" description="" />
  192 + </section>
  193 + </section>
  194 + <section name="report_utilization" level="1" order="6" description="">
  195 + <section name="clocking" level="2" order="1" description="">
  196 + <keyValuePair key="bufgctrl_available" value="32" description="" />
  197 + <keyValuePair key="bufgctrl_fixed" value="0" description="" />
  198 + <keyValuePair key="bufgctrl_used" value="1" description="" />
  199 + <keyValuePair key="bufgctrl_util_percentage" value="3.13" description="" />
  200 + <keyValuePair key="bufhce_available" value="72" description="" />
  201 + <keyValuePair key="bufhce_fixed" value="0" description="" />
  202 + <keyValuePair key="bufhce_used" value="0" description="" />
  203 + <keyValuePair key="bufhce_util_percentage" value="0.00" description="" />
  204 + <keyValuePair key="bufio_available" value="20" description="" />
  205 + <keyValuePair key="bufio_fixed" value="0" description="" />
  206 + <keyValuePair key="bufio_used" value="0" description="" />
  207 + <keyValuePair key="bufio_util_percentage" value="0.00" description="" />
  208 + <keyValuePair key="bufmrce_available" value="10" description="" />
  209 + <keyValuePair key="bufmrce_fixed" value="0" description="" />
  210 + <keyValuePair key="bufmrce_used" value="0" description="" />
  211 + <keyValuePair key="bufmrce_util_percentage" value="0.00" description="" />
  212 + <keyValuePair key="bufr_available" value="20" description="" />
  213 + <keyValuePair key="bufr_fixed" value="0" description="" />
  214 + <keyValuePair key="bufr_used" value="0" description="" />
  215 + <keyValuePair key="bufr_util_percentage" value="0.00" description="" />
  216 + <keyValuePair key="mmcme2_adv_available" value="5" description="" />
  217 + <keyValuePair key="mmcme2_adv_fixed" value="0" description="" />
  218 + <keyValuePair key="mmcme2_adv_used" value="0" description="" />
  219 + <keyValuePair key="mmcme2_adv_util_percentage" value="0.00" description="" />
  220 + <keyValuePair key="plle2_adv_available" value="5" description="" />
  221 + <keyValuePair key="plle2_adv_fixed" value="0" description="" />
  222 + <keyValuePair key="plle2_adv_used" value="0" description="" />
  223 + <keyValuePair key="plle2_adv_util_percentage" value="0.00" description="" />
  224 + </section>
  225 + <section name="dsp" level="2" order="2" description="">
  226 + <keyValuePair key="dsps_available" value="90" description="" />
  227 + <keyValuePair key="dsps_fixed" value="0" description="" />
  228 + <keyValuePair key="dsps_used" value="0" description="" />
  229 + <keyValuePair key="dsps_util_percentage" value="0.00" description="" />
  230 + </section>
  231 + <section name="io_standard" level="2" order="3" description="">
  232 + <keyValuePair key="blvds_25" value="0" description="" />
  233 + <keyValuePair key="diff_hstl_i" value="0" description="" />
  234 + <keyValuePair key="diff_hstl_i_18" value="0" description="" />
  235 + <keyValuePair key="diff_hstl_ii" value="0" description="" />
  236 + <keyValuePair key="diff_hstl_ii_18" value="0" description="" />
  237 + <keyValuePair key="diff_hsul_12" value="0" description="" />
  238 + <keyValuePair key="diff_mobile_ddr" value="0" description="" />
  239 + <keyValuePair key="diff_sstl135" value="0" description="" />
  240 + <keyValuePair key="diff_sstl135_r" value="0" description="" />
  241 + <keyValuePair key="diff_sstl15" value="0" description="" />
  242 + <keyValuePair key="diff_sstl15_r" value="0" description="" />
  243 + <keyValuePair key="diff_sstl18_i" value="0" description="" />
  244 + <keyValuePair key="diff_sstl18_ii" value="0" description="" />
  245 + <keyValuePair key="hstl_i" value="0" description="" />
  246 + <keyValuePair key="hstl_i_18" value="0" description="" />
  247 + <keyValuePair key="hstl_ii" value="0" description="" />
  248 + <keyValuePair key="hstl_ii_18" value="0" description="" />
  249 + <keyValuePair key="hsul_12" value="0" description="" />
  250 + <keyValuePair key="lvcmos12" value="0" description="" />
  251 + <keyValuePair key="lvcmos15" value="0" description="" />
  252 + <keyValuePair key="lvcmos18" value="0" description="" />
  253 + <keyValuePair key="lvcmos25" value="0" description="" />
  254 + <keyValuePair key="lvcmos33" value="1" description="" />
  255 + <keyValuePair key="lvds_25" value="0" description="" />
  256 + <keyValuePair key="lvttl" value="0" description="" />
  257 + <keyValuePair key="mini_lvds_25" value="0" description="" />
  258 + <keyValuePair key="mobile_ddr" value="0" description="" />
  259 + <keyValuePair key="pci33_3" value="0" description="" />
  260 + <keyValuePair key="ppds_25" value="0" description="" />
  261 + <keyValuePair key="rsds_25" value="0" description="" />
  262 + <keyValuePair key="sstl135" value="0" description="" />
  263 + <keyValuePair key="sstl135_r" value="0" description="" />
  264 + <keyValuePair key="sstl15" value="0" description="" />
  265 + <keyValuePair key="sstl15_r" value="0" description="" />
  266 + <keyValuePair key="sstl18_i" value="0" description="" />
  267 + <keyValuePair key="sstl18_ii" value="0" description="" />
  268 + <keyValuePair key="tmds_33" value="0" description="" />
  269 + </section>
  270 + <section name="memory" level="2" order="4" description="">
  271 + <keyValuePair key="block_ram_tile_available" value="50" description="" />
  272 + <keyValuePair key="block_ram_tile_fixed" value="0" description="" />
  273 + <keyValuePair key="block_ram_tile_used" value="0" description="" />
  274 + <keyValuePair key="block_ram_tile_util_percentage" value="0.00" description="" />
  275 + <keyValuePair key="ramb18_available" value="100" description="" />
  276 + <keyValuePair key="ramb18_fixed" value="0" description="" />
  277 + <keyValuePair key="ramb18_used" value="0" description="" />
  278 + <keyValuePair key="ramb18_util_percentage" value="0.00" description="" />
  279 + <keyValuePair key="ramb36_fifo_available" value="50" description="" />
  280 + <keyValuePair key="ramb36_fifo_fixed" value="0" description="" />
  281 + <keyValuePair key="ramb36_fifo_used" value="0" description="" />
  282 + <keyValuePair key="ramb36_fifo_util_percentage" value="0.00" description="" />
  283 + </section>
  284 + <section name="primitives" level="2" order="5" description="">
  285 + <keyValuePair key="bufg_functional_category" value="Clock" description="" />
  286 + <keyValuePair key="bufg_used" value="1" description="" />
  287 + <keyValuePair key="carry4_functional_category" value="CarryLogic" description="" />
  288 + <keyValuePair key="carry4_used" value="5" description="" />
  289 + <keyValuePair key="fdce_functional_category" value="Flop &amp; Latch" description="" />
  290 + <keyValuePair key="fdce_used" value="20" description="" />
  291 + <keyValuePair key="ibuf_functional_category" value="IO" description="" />
  292 + <keyValuePair key="ibuf_used" value="2" description="" />
  293 + <keyValuePair key="lut1_functional_category" value="LUT" description="" />
  294 + <keyValuePair key="lut1_used" value="1" description="" />
  295 + <keyValuePair key="lut2_functional_category" value="LUT" description="" />
  296 + <keyValuePair key="lut2_used" value="7" description="" />
  297 + <keyValuePair key="obuf_functional_category" value="IO" description="" />
  298 + <keyValuePair key="obuf_used" value="11" description="" />
  299 + </section>
  300 + <section name="slice_logic" level="2" order="6" description="">
  301 + <keyValuePair key="f7_muxes_available" value="16300" description="" />
  302 + <keyValuePair key="f7_muxes_fixed" value="0" description="" />
  303 + <keyValuePair key="f7_muxes_used" value="0" description="" />
  304 + <keyValuePair key="f7_muxes_util_percentage" value="0.00" description="" />
  305 + <keyValuePair key="f8_muxes_available" value="8150" description="" />
  306 + <keyValuePair key="f8_muxes_fixed" value="0" description="" />
  307 + <keyValuePair key="f8_muxes_used" value="0" description="" />
  308 + <keyValuePair key="f8_muxes_util_percentage" value="0.00" description="" />
  309 + <keyValuePair key="lut_as_distributed_ram_fixed" value="0" description="" />
  310 + <keyValuePair key="lut_as_distributed_ram_used" value="0" description="" />
  311 + <keyValuePair key="lut_as_logic_available" value="20800" description="" />
  312 + <keyValuePair key="lut_as_logic_available" value="20800" description="" />
  313 + <keyValuePair key="lut_as_logic_fixed" value="0" description="" />
  314 + <keyValuePair key="lut_as_logic_fixed" value="0" description="" />
  315 + <keyValuePair key="lut_as_logic_used" value="5" description="" />
  316 + <keyValuePair key="lut_as_logic_used" value="5" description="" />
  317 + <keyValuePair key="lut_as_logic_util_percentage" value="0.02" description="" />
  318 + <keyValuePair key="lut_as_logic_util_percentage" value="0.02" description="" />
  319 + <keyValuePair key="lut_as_memory_available" value="9600" description="" />
  320 + <keyValuePair key="lut_as_memory_available" value="9600" description="" />
  321 + <keyValuePair key="lut_as_memory_fixed" value="0" description="" />
  322 + <keyValuePair key="lut_as_memory_fixed" value="0" description="" />
  323 + <keyValuePair key="lut_as_memory_used" value="0" description="" />
  324 + <keyValuePair key="lut_as_memory_used" value="0" description="" />
  325 + <keyValuePair key="lut_as_memory_util_percentage" value="0.00" description="" />
  326 + <keyValuePair key="lut_as_memory_util_percentage" value="0.00" description="" />
  327 + <keyValuePair key="lut_as_shift_register_fixed" value="0" description="" />
  328 + <keyValuePair key="lut_as_shift_register_used" value="0" description="" />
  329 + <keyValuePair key="register_as_flip_flop_available" value="41600" description="" />
  330 + <keyValuePair key="register_as_flip_flop_fixed" value="0" description="" />
  331 + <keyValuePair key="register_as_flip_flop_used" value="20" description="" />
  332 + <keyValuePair key="register_as_flip_flop_util_percentage" value="0.05" description="" />
  333 + <keyValuePair key="register_as_latch_available" value="41600" description="" />
  334 + <keyValuePair key="register_as_latch_fixed" value="0" description="" />
  335 + <keyValuePair key="register_as_latch_used" value="0" description="" />
  336 + <keyValuePair key="register_as_latch_util_percentage" value="0.00" description="" />
  337 + <keyValuePair key="register_driven_from_outside_the_slice_fixed" value="0" description="" />
  338 + <keyValuePair key="register_driven_from_outside_the_slice_used" value="0" description="" />
  339 + <keyValuePair key="register_driven_from_within_the_slice_fixed" value="0" description="" />
  340 + <keyValuePair key="register_driven_from_within_the_slice_used" value="20" description="" />
  341 + <keyValuePair key="slice_available" value="8150" description="" />
  342 + <keyValuePair key="slice_fixed" value="0" description="" />
  343 + <keyValuePair key="slice_luts_available" value="20800" description="" />
  344 + <keyValuePair key="slice_luts_fixed" value="0" description="" />
  345 + <keyValuePair key="slice_luts_used" value="5" description="" />
  346 + <keyValuePair key="slice_luts_util_percentage" value="0.02" description="" />
  347 + <keyValuePair key="slice_registers_available" value="41600" description="" />
  348 + <keyValuePair key="slice_registers_available" value="41600" description="" />
  349 + <keyValuePair key="slice_registers_fixed" value="0" description="" />
  350 + <keyValuePair key="slice_registers_fixed" value="0" description="" />
  351 + <keyValuePair key="slice_registers_used" value="20" description="" />
  352 + <keyValuePair key="slice_registers_used" value="20" description="" />
  353 + <keyValuePair key="slice_registers_util_percentage" value="0.05" description="" />
  354 + <keyValuePair key="slice_registers_util_percentage" value="0.05" description="" />
  355 + <keyValuePair key="slice_used" value="6" description="" />
  356 + <keyValuePair key="slice_util_percentage" value="0.07" description="" />
  357 + <keyValuePair key="slicel_fixed" value="0" description="" />
  358 + <keyValuePair key="slicel_used" value="6" description="" />
  359 + <keyValuePair key="slicem_fixed" value="0" description="" />
  360 + <keyValuePair key="slicem_used" value="0" description="" />
  361 + <keyValuePair key="unique_control_sets_available" value="8150" description="" />
  362 + <keyValuePair key="unique_control_sets_fixed" value="8150" description="" />
  363 + <keyValuePair key="unique_control_sets_used" value="1" description="" />
  364 + <keyValuePair key="unique_control_sets_util_percentage" value="0.01" description="" />
  365 + <keyValuePair key="using_o5_and_o6_fixed" value="0.01" description="" />
  366 + <keyValuePair key="using_o5_and_o6_used" value="3" description="" />
  367 + <keyValuePair key="using_o5_output_only_fixed" value="3" description="" />
  368 + <keyValuePair key="using_o5_output_only_used" value="0" description="" />
  369 + <keyValuePair key="using_o6_output_only_fixed" value="0" description="" />
  370 + <keyValuePair key="using_o6_output_only_used" value="2" description="" />
  371 + </section>
  372 + <section name="specific_feature" level="2" order="7" description="">
  373 + <keyValuePair key="bscane2_available" value="4" description="" />
  374 + <keyValuePair key="bscane2_fixed" value="0" description="" />
  375 + <keyValuePair key="bscane2_used" value="0" description="" />
  376 + <keyValuePair key="bscane2_util_percentage" value="0.00" description="" />
  377 + <keyValuePair key="capturee2_available" value="1" description="" />
  378 + <keyValuePair key="capturee2_fixed" value="0" description="" />
  379 + <keyValuePair key="capturee2_used" value="0" description="" />
  380 + <keyValuePair key="capturee2_util_percentage" value="0.00" description="" />
  381 + <keyValuePair key="dna_port_available" value="1" description="" />
  382 + <keyValuePair key="dna_port_fixed" value="0" description="" />
  383 + <keyValuePair key="dna_port_used" value="0" description="" />
  384 + <keyValuePair key="dna_port_util_percentage" value="0.00" description="" />
  385 + <keyValuePair key="efuse_usr_available" value="1" description="" />
  386 + <keyValuePair key="efuse_usr_fixed" value="0" description="" />
  387 + <keyValuePair key="efuse_usr_used" value="0" description="" />
  388 + <keyValuePair key="efuse_usr_util_percentage" value="0.00" description="" />
  389 + <keyValuePair key="frame_ecce2_available" value="1" description="" />
  390 + <keyValuePair key="frame_ecce2_fixed" value="0" description="" />
  391 + <keyValuePair key="frame_ecce2_used" value="0" description="" />
  392 + <keyValuePair key="frame_ecce2_util_percentage" value="0.00" description="" />
  393 + <keyValuePair key="icape2_available" value="2" description="" />
  394 + <keyValuePair key="icape2_fixed" value="0" description="" />
  395 + <keyValuePair key="icape2_used" value="0" description="" />
  396 + <keyValuePair key="icape2_util_percentage" value="0.00" description="" />
  397 + <keyValuePair key="pcie_2_1_available" value="1" description="" />
  398 + <keyValuePair key="pcie_2_1_fixed" value="0" description="" />
  399 + <keyValuePair key="pcie_2_1_used" value="0" description="" />
  400 + <keyValuePair key="pcie_2_1_util_percentage" value="0.00" description="" />
  401 + <keyValuePair key="startupe2_available" value="1" description="" />
  402 + <keyValuePair key="startupe2_fixed" value="0" description="" />
  403 + <keyValuePair key="startupe2_used" value="0" description="" />
  404 + <keyValuePair key="startupe2_util_percentage" value="0.00" description="" />
  405 + <keyValuePair key="xadc_available" value="1" description="" />
  406 + <keyValuePair key="xadc_fixed" value="0" description="" />
  407 + <keyValuePair key="xadc_used" value="0" description="" />
  408 + <keyValuePair key="xadc_util_percentage" value="0.00" description="" />
  409 + </section>
  410 + </section>
  411 + <section name="synthesis" level="1" order="7" description="">
  412 + <section name="command_line_options" level="2" order="1" description="">
  413 + <keyValuePair key="-assert" value="default::[not_specified]" description="" />
  414 + <keyValuePair key="-bufg" value="default::12" description="" />
  415 + <keyValuePair key="-cascade_dsp" value="default::auto" description="" />
  416 + <keyValuePair key="-constrset" value="default::[not_specified]" description="" />
  417 + <keyValuePair key="-control_set_opt_threshold" value="default::auto" description="" />
  418 + <keyValuePair key="-directive" value="default::default" description="" />
  419 + <keyValuePair key="-fanout_limit" value="default::10000" description="" />
  420 + <keyValuePair key="-flatten_hierarchy" value="default::rebuilt" description="" />
  421 + <keyValuePair key="-fsm_extraction" value="default::auto" description="" />
  422 + <keyValuePair key="-gated_clock_conversion" value="default::off" description="" />
  423 + <keyValuePair key="-generic" value="default::[not_specified]" description="" />
  424 + <keyValuePair key="-include_dirs" value="default::[not_specified]" description="" />
  425 + <keyValuePair key="-keep_equivalent_registers" value="default::[not_specified]" description="" />
  426 + <keyValuePair key="-max_bram" value="default::-1" description="" />
  427 + <keyValuePair key="-max_bram_cascade_height" value="default::-1" description="" />
  428 + <keyValuePair key="-max_dsp" value="default::-1" description="" />
  429 + <keyValuePair key="-max_uram" value="default::-1" description="" />
  430 + <keyValuePair key="-max_uram_cascade_height" value="default::-1" description="" />
  431 + <keyValuePair key="-mode" value="default::default" description="" />
  432 + <keyValuePair key="-name" value="default::[not_specified]" description="" />
  433 + <keyValuePair key="-no_lc" value="default::[not_specified]" description="" />
  434 + <keyValuePair key="-no_srlextract" value="default::[not_specified]" description="" />
  435 + <keyValuePair key="-no_timing_driven" value="default::[not_specified]" description="" />
  436 + <keyValuePair key="-part" value="xc7a35tcpg236-1" description="" />
  437 + <keyValuePair key="-resource_sharing" value="default::auto" description="" />
  438 + <keyValuePair key="-retiming" value="default::[not_specified]" description="" />
  439 + <keyValuePair key="-rtl" value="default::[not_specified]" description="" />
  440 + <keyValuePair key="-rtl_skip_constraints" value="default::[not_specified]" description="" />
  441 + <keyValuePair key="-rtl_skip_ip" value="default::[not_specified]" description="" />
  442 + <keyValuePair key="-seu_protect" value="default::none" description="" />
  443 + <keyValuePair key="-sfcu" value="default::[not_specified]" description="" />
  444 + <keyValuePair key="-shreg_min_size" value="default::3" description="" />
  445 + <keyValuePair key="-top" value="Afficheur_7SEG" description="" />
  446 + <keyValuePair key="-verilog_define" value="default::[not_specified]" description="" />
  447 + </section>
  448 + <section name="usage" level="2" order="2" description="">
  449 + <keyValuePair key="elapsed" value="00:00:26s" description="" />
  450 + <keyValuePair key="hls_ip" value="0" description="" />
  451 + <keyValuePair key="memory_gain" value="600.383MB" description="" />
  452 + <keyValuePair key="memory_peak" value="908.391MB" description="" />
  453 + </section>
  454 + </section>
  455 + <section name="unisim_transformation" level="1" order="8" description="">
  456 + <section name="post_unisim_transformation" level="2" order="1" description="">
  457 + <keyValuePair key="bufg" value="1" description="" />
  458 + <keyValuePair key="carry4" value="5" description="" />
  459 + <keyValuePair key="fdce" value="20" description="" />
  460 + <keyValuePair key="gnd" value="1" description="" />
  461 + <keyValuePair key="ibuf" value="2" description="" />
  462 + <keyValuePair key="lut1" value="1" description="" />
  463 + <keyValuePair key="lut2" value="7" description="" />
  464 + <keyValuePair key="obuf" value="11" description="" />
  465 + <keyValuePair key="vcc" value="1" description="" />
  466 + </section>
  467 + <section name="pre_unisim_transformation" level="2" order="2" description="">
  468 + <keyValuePair key="bufg" value="1" description="" />
  469 + <keyValuePair key="carry4" value="5" description="" />
  470 + <keyValuePair key="fdce" value="20" description="" />
  471 + <keyValuePair key="gnd" value="1" description="" />
  472 + <keyValuePair key="ibuf" value="2" description="" />
  473 + <keyValuePair key="lut1" value="1" description="" />
  474 + <keyValuePair key="lut2" value="7" description="" />
  475 + <keyValuePair key="obuf" value="11" description="" />
  476 + <keyValuePair key="vcc" value="1" description="" />
  477 + </section>
  478 + </section>
  479 + <section name="vivado_usage" level="1" order="9" description="">
  480 + <section name="gui_handlers" level="2" order="1" description="">
  481 + <keyValuePair key="basedialog_cancel" value="1" description="" />
  482 + <keyValuePair key="basedialog_ok" value="11" description="" />
  483 + <keyValuePair key="basedialog_yes" value="3" description="" />
  484 + <keyValuePair key="filesetpanel_file_set_panel_tree" value="6" description="" />
  485 + <keyValuePair key="filtertoolbar_hide_all" value="1" description="" />
  486 + <keyValuePair key="filtertoolbar_show_all" value="2" description="" />
  487 + <keyValuePair key="flownavigatortreepanel_flow_navigator_tree" value="17" description="" />
  488 + <keyValuePair key="gettingstartedview_open_project" value="2" description="" />
  489 + <keyValuePair key="launchpanel_dont_show_this_dialog_again" value="1" description="" />
  490 + <keyValuePair key="logmonitor_monitor" value="12" description="" />
  491 + <keyValuePair key="maintoolbarmgr_run" value="9" description="" />
  492 + <keyValuePair key="messagewithoptiondialog_dont_show_this_dialog_again" value="6" description="" />
  493 + <keyValuePair key="msgtreepanel_message_view_tree" value="4" description="" />
  494 + <keyValuePair key="msgview_clear_messages_resulting_from_user_executed" value="5" description="" />
  495 + <keyValuePair key="msgview_information_messages" value="1" description="" />
  496 + <keyValuePair key="numjobschooser_number_of_jobs" value="1" description="" />
  497 + <keyValuePair key="pacommandnames_auto_connect_target" value="1" description="" />
  498 + <keyValuePair key="pacommandnames_run_bitgen" value="2" description="" />
  499 + <keyValuePair key="pacommandnames_run_implementation" value="3" description="" />
  500 + <keyValuePair key="pacommandnames_run_synthesis" value="6" description="" />
  501 + <keyValuePair key="paviews_project_summary" value="1" description="" />
  502 + <keyValuePair key="paviews_schematic" value="2" description="" />
  503 + <keyValuePair key="programdebugtab_program_device" value="1" description="" />
  504 + <keyValuePair key="programfpgadialog_program" value="1" description="" />
  505 + <keyValuePair key="projecttab_reload" value="1" description="" />
  506 + <keyValuePair key="rdicommands_line_comment" value="3" description="" />
  507 + <keyValuePair key="saveprojectutils_save" value="3" description="" />
  508 + </section>
  509 + <section name="java_command_handlers" level="2" order="2" description="">
  510 + <keyValuePair key="autoconnecttarget" value="1" description="" />
  511 + <keyValuePair key="launchprogramfpga" value="1" description="" />
  512 + <keyValuePair key="openhardwaremanager" value="1" description="" />
  513 + <keyValuePair key="openproject" value="2" description="" />
  514 + <keyValuePair key="openrecenttarget" value="1" description="" />
  515 + <keyValuePair key="runbitgen" value="8" description="" />
  516 + <keyValuePair key="runimplementation" value="5" description="" />
  517 + <keyValuePair key="runschematic" value="2" description="" />
  518 + <keyValuePair key="runsynthesis" value="7" description="" />
  519 + <keyValuePair key="showview" value="3" description="" />
  520 + </section>
  521 + <section name="other_data" level="2" order="3" description="">
  522 + <keyValuePair key="guimode" value="2" description="" />
  523 + </section>
  524 + <section name="project_data" level="2" order="4" description="">
  525 + <keyValuePair key="constraintsetcount" value="1" description="" />
  526 + <keyValuePair key="core_container" value="false" description="" />
  527 + <keyValuePair key="currentimplrun" value="impl_1" description="" />
  528 + <keyValuePair key="currentsynthesisrun" value="synth_1" description="" />
  529 + <keyValuePair key="default_library" value="xil_defaultlib" description="" />
  530 + <keyValuePair key="designmode" value="RTL" description="" />
  531 + <keyValuePair key="export_simulation_activehdl" value="0" description="" />
  532 + <keyValuePair key="export_simulation_ies" value="0" description="" />
  533 + <keyValuePair key="export_simulation_modelsim" value="0" description="" />
  534 + <keyValuePair key="export_simulation_questa" value="0" description="" />
  535 + <keyValuePair key="export_simulation_riviera" value="0" description="" />
  536 + <keyValuePair key="export_simulation_vcs" value="0" description="" />
  537 + <keyValuePair key="export_simulation_xsim" value="0" description="" />
  538 + <keyValuePair key="implstrategy" value="Vivado Implementation Defaults" description="" />
  539 + <keyValuePair key="launch_simulation_activehdl" value="0" description="" />
  540 + <keyValuePair key="launch_simulation_ies" value="0" description="" />
  541 + <keyValuePair key="launch_simulation_modelsim" value="0" description="" />
  542 + <keyValuePair key="launch_simulation_questa" value="0" description="" />
  543 + <keyValuePair key="launch_simulation_riviera" value="0" description="" />
  544 + <keyValuePair key="launch_simulation_vcs" value="0" description="" />
  545 + <keyValuePair key="launch_simulation_xsim" value="0" description="" />
  546 + <keyValuePair key="simulator_language" value="Mixed" description="" />
  547 + <keyValuePair key="srcsetcount" value="1" description="" />
  548 + <keyValuePair key="synthesisstrategy" value="Vivado Synthesis Defaults" description="" />
  549 + <keyValuePair key="target_language" value="VHDL" description="" />
  550 + <keyValuePair key="target_simulator" value="XSim" description="" />
  551 + <keyValuePair key="totalimplruns" value="1" description="" />
  552 + <keyValuePair key="totalsynthesisruns" value="1" description="" />
  553 + </section>
  554 + </section>
  555 +</section>
  556 +</webTalkData>
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado.jou 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado.jou
@@ -0,0 +1,12 @@ @@ -0,0 +1,12 @@
  1 +#-----------------------------------------------------------
  2 +# Vivado v2019.1 (64-bit)
  3 +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
  4 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
  5 +# Start of session at: Wed Oct 4 15:35:14 2023
  6 +# Process ID: 9160
  7 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1
  8 +# Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace
  9 +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi
  10 +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou
  11 +#-----------------------------------------------------------
  12 +source Afficheur_7SEG.tcl -notrace
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado.pb 0 → 100755
View file @231d00d
No preview for this file type
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_2876.backup.jou 0 → 100755
  Show/Hide comments   View file @231d00d
  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_2876.backup.jou
@@ -0,0 +1,12 @@ @@ -0,0 +1,12 @@
  1 +#-----------------------------------------------------------
  2 +# Vivado v2019.1 (64-bit)
  3 +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
  4 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
  5 +# Start of session at: Wed Oct 4 15:26:28 2023
  6 +# Process ID: 2876
  7 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1
  8 +# Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace
  9 +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi
  10 +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou
  11 +#-----------------------------------------------------------
  12 +source Afficheur_7SEG.tcl -notrace
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_3012.backup.jou 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_3012.backup.jou
@@ -0,0 +1,12 @@ @@ -0,0 +1,12 @@
  1 +#-----------------------------------------------------------
  2 +# Vivado v2019.1 (64-bit)
  3 +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
  4 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
  5 +# Start of session at: Wed Oct 4 14:25:17 2023
  6 +# Process ID: 3012
  7 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1
  8 +# Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace
  9 +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi
  10 +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou
  11 +#-----------------------------------------------------------
  12 +source Afficheur_7SEG.tcl -notrace
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_5200.backup.jou 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_5200.backup.jou
@@ -0,0 +1,12 @@ @@ -0,0 +1,12 @@
  1 +#-----------------------------------------------------------
  2 +# Vivado v2019.1 (64-bit)
  3 +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
  4 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
  5 +# Start of session at: Wed Oct 4 15:11:40 2023
  6 +# Process ID: 5200
  7 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1
  8 +# Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace
  9 +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi
  10 +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou
  11 +#-----------------------------------------------------------
  12 +source Afficheur_7SEG.tcl -notrace
Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_8792.backup.jou 0 → 100755
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  1 +++ a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_8792.backup.jou
@@ -0,0 +1,12 @@ @@ -0,0 +1,12 @@
  1 +#-----------------------------------------------------------
  2 +# Vivado v2019.1 (64-bit)
  3 +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
  4 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
  5 +# Start of session at: Wed Oct 4 15:12:47 2023
  6 +# Process ID: 8792
  7 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1
  8 +# Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace
  9 +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi
  10 +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou
  11 +#-----------------------------------------------------------
  12 +source Afficheur_7SEG.tcl -notrace