From 231d00d3387b94551d4d93e69e45358d322bcea0 Mon Sep 17 00:00:00 2001 From: bilalelhasnaoui Date: Mon, 30 Oct 2023 00:37:51 +0100 Subject: [PATCH] Les deux application 7segment et VGA control avec Basys3 FPGA --- Afficheur_7SEG/Afficheur_7SEG.cache/wt/gui_handlers.wdf | 41 +++++++++++++++++++++++++++++++++++++++++ Afficheur_7SEG/Afficheur_7SEG.cache/wt/java_command_handlers.wdf | 14 ++++++++++++++ Afficheur_7SEG/Afficheur_7SEG.cache/wt/project.wpc | 4 ++++ Afficheur_7SEG/Afficheur_7SEG.cache/wt/synthesis.wdf | 39 +++++++++++++++++++++++++++++++++++++++ Afficheur_7SEG/Afficheur_7SEG.cache/wt/synthesis_details.wdf | 3 +++ Afficheur_7SEG/Afficheur_7SEG.cache/wt/webtalk_pa.xml | 81 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Afficheur_7SEG/Afficheur_7SEG.hw/Afficheur_7SEG.lpr | 8 ++++++++ Afficheur_7SEG/Afficheur_7SEG.hw/hw_1/hw.xml | 17 +++++++++++++++++ Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/.xsim_webtallk.info | 5 +++++ Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/labtool_webtalk.log | 8 ++++++++ Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/usage_statistics_ext_labtool.html | 45 +++++++++++++++++++++++++++++++++++++++++++++ Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/usage_statistics_ext_labtool.xml | 39 +++++++++++++++++++++++++++++++++++++++ Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_1.xml | 8 ++++++++ Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_10.xml | 8 ++++++++ Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_11.xml | 8 ++++++++ Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_12.xml | 8 ++++++++ Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_13.xml | 11 +++++++++++ Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_14.xml | 11 +++++++++++ Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_15.xml | 8 ++++++++ Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_16.xml | 11 +++++++++++ Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_17.xml | 8 ++++++++ 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+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Afficheur_7SEG/Afficheur_7SEG.hw/Afficheur_7SEG.lpr b/Afficheur_7SEG/Afficheur_7SEG.hw/Afficheur_7SEG.lpr new file mode 100755 index 0000000..8d9c70d --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.hw/Afficheur_7SEG.lpr @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.hw/hw_1/hw.xml b/Afficheur_7SEG/Afficheur_7SEG.hw/hw_1/hw.xml new file mode 100755 index 0000000..45d7244 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/.xsim_webtallk.info b/Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/.xsim_webtallk.info new file mode 100755 index 0000000..934c8d3 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1696428411 +0 +2 +0 +58edfc98-0772-4f04-8438-85f24cad8e0d diff --git a/Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/labtool_webtalk.log b/Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/labtool_webtalk.log new file mode 100755 index 0000000..d1b0ef9 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/labtool_webtalk.log @@ -0,0 +1,8 @@ + +****** Webtalk v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/labtool_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Wed Oct 4 16:06:53 2023... diff --git a/Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/usage_statistics_ext_labtool.html b/Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/usage_statistics_ext_labtool.html new file mode 100755 index 0000000..4dabea9 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/usage_statistics_ext_labtool.html @@ -0,0 +1,45 @@ +Device Usage Statistics Report +

LABTOOL Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2552052
date_generatedWed Oct 4 16:06:51 2023os_platformWIN64
product_versionVivado v2019.1 (64-bit)project_id58edfc98-0772-4f04-8438-85f24cad8e0d
project_iteration1random_id543ca123-eb9d-49cf-8266-de8eac9687e5
registration_id543ca123-eb9d-49cf-8266-de8eac9687e5route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowlabtool

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) i5-8500 CPU @ 3.00GHzcpu_speed3000 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram12.000 GBtotal_processors1

+ + +
vivado_usage

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labtool
+ + + + + +
usage
cable=Digilent/Basys3/15000000:chain=0362D093pgmcnt=02:00:00
+

+ + diff --git a/Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/usage_statistics_ext_labtool.xml b/Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/usage_statistics_ext_labtool.xml new file mode 100755 index 0000000..e21f042 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.hw/webtalk/usage_statistics_ext_labtool.xml @@ -0,0 +1,39 @@ + + +
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+ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_1.xml b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_1.xml new file mode 100755 index 0000000..eab8e4b --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_10.xml b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_10.xml new file mode 100755 index 0000000..35799be --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_11.xml b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_11.xml new file mode 100755 index 0000000..00fb091 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_11.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_12.xml b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_12.xml new file mode 100755 index 0000000..00fb091 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_12.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_13.xml b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_13.xml new file mode 100755 index 0000000..04fd380 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_13.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_14.xml b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_14.xml new file mode 100755 index 0000000..04fd380 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_14.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_15.xml b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_15.xml new file mode 100755 index 0000000..35799be --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_15.xml @@ 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a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_7.xml b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_7.xml new file mode 100755 index 0000000..eab8e4b --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_8.xml b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_8.xml new file mode 100755 index 0000000..35799be --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_9.xml b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_9.xml new file mode 100755 index 0000000..eab8e4b --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.Vivado_Implementation.queue.rst b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.Vivado_Implementation.queue.rst new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.Vivado_Implementation.queue.rst diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.init_design.begin.rst b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.init_design.begin.rst new file mode 100755 index 0000000..0f3730e --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.init_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.init_design.end.rst b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.init_design.end.rst new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.init_design.end.rst diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.opt_design.begin.rst b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.opt_design.begin.rst new file mode 100755 index 0000000..0f3730e --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.opt_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.opt_design.end.rst b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.opt_design.end.rst new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.opt_design.end.rst diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.place_design.begin.rst b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.place_design.begin.rst new file mode 100755 index 0000000..0f3730e --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.place_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.place_design.end.rst b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.place_design.end.rst new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.place_design.end.rst diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.route_design.begin.rst b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.route_design.begin.rst new file mode 100755 index 0000000..0f3730e --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.route_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.route_design.end.rst b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.route_design.end.rst new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.route_design.end.rst diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.vivado.begin.rst b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.vivado.begin.rst new file mode 100755 index 0000000..fda49ea --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.vivado.end.rst b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.vivado.end.rst new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.vivado.end.rst diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.write_bitstream.begin.rst b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.write_bitstream.begin.rst new file mode 100755 index 0000000..0f3730e --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.write_bitstream.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.write_bitstream.end.rst b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.write_bitstream.end.rst new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/.write_bitstream.end.rst diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.bit b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.bit new file mode 100755 index 0000000..90432b3 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.bit differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.tcl b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.tcl new file mode 100755 index 0000000..98cb157 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.tcl @@ -0,0 +1,175 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param chipscope.maxJobs 1 + set_param synth.incrementalSynthesisCache C:/Xilinx/Vivado/2019.1/bin/.Xil/Vivado-7292-WIN10-TP/incrSyn + set_param xicom.use_bs_reader 1 + create_project -in_memory -part xc7a35tcpg236-1 + set_property board_part digilentinc.com:basys3:part0:1.2 [current_project] + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.cache/wt [current_project] + set_property parent.project_path C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.xpr [current_project] + set_property ip_output_repo C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG.dcp + read_xdc C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc + link_design -top Afficheur_7SEG -part xc7a35tcpg236-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force Afficheur_7SEG_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force Afficheur_7SEG_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file Afficheur_7SEG_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file Afficheur_7SEG_utilization_placed.rpt -pb Afficheur_7SEG_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file Afficheur_7SEG_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force Afficheur_7SEG_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file Afficheur_7SEG_route_status.rpt -pb Afficheur_7SEG_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file Afficheur_7SEG_timing_summary_routed.rpt -pb Afficheur_7SEG_timing_summary_routed.pb -rpx Afficheur_7SEG_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file Afficheur_7SEG_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file Afficheur_7SEG_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file Afficheur_7SEG_bus_skew_routed.rpt -pb Afficheur_7SEG_bus_skew_routed.pb -rpx Afficheur_7SEG_bus_skew_routed.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force Afficheur_7SEG_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + catch { write_mem_info -force Afficheur_7SEG.mmi } + write_bitstream -force Afficheur_7SEG.bit + catch {write_debug_probes -quiet -force Afficheur_7SEG} + catch {file copy -force Afficheur_7SEG.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi new file mode 100755 index 0000000..49d2dec --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi @@ -0,0 +1,500 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Wed Oct 4 15:35:14 2023 +# Process ID: 9160 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1 +# Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source Afficheur_7SEG.tcl -notrace +Command: link_design -top Afficheur_7SEG -part xc7a35tcpg236-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2019.1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc] +Finished Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 662.551 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 666.586 ; gain = 375.434 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.643 . Memory (MB): peak = 686.492 ; gain = 19.906 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 1b472ca95 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1200.875 ; gain = 514.383 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1b472ca95 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1b472ca95 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1f526e7c3 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1f526e7c3 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 1f526e7c3 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 1f526e7c3 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 260393764 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 260393764 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 260393764 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 260393764 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1341.555 ; gain = 674.969 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx +Command: report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1d171f48f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1b8f8806f + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.835 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 2ac1244c8 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.847 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 2ac1244c8 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.849 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 2ac1244c8 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.850 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 2ac1244c8 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.852 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 2.2 Global Placement Core +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2.2 Global Placement Core | Checksum: 21c4ed49b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 21c4ed49b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 21c4ed49b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18a378908 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 216e3a3c1 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 216e3a3c1 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 19592b163 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 19592b163 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 19592b163 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 19592b163 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 19592b163 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 19592b163 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 19592b163 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Phase 4.4 Final Placement Cleanup | Checksum: 19592b163 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 19592b163 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Ending Placer Task | Checksum: 16b3cb9b6 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +42 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1352.461 ; gain = 10.906 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file Afficheur_7SEG_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1352.461 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file Afficheur_7SEG_utilization_placed.rpt -pb Afficheur_7SEG_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file Afficheur_7SEG_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1352.461 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 92aaeef2 ConstDB: 0 ShapeSum: d891cac4 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 9fc16879 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1442.992 ; gain = 79.531 +Post Restoration Checksum: NetGraph: 769cd3b9 NumContArr: 292494c0 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 9fc16879 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1449.000 ; gain = 85.539 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 9fc16879 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1449.000 ; gain = 85.539 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 16939516a + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1452.375 ; gain = 88.914 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 32 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 32 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 106a7763c + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 131215cb1 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 +Phase 4 Rip-up And Reroute | Checksum: 131215cb1 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 131215cb1 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 131215cb1 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 +Phase 6 Post Hold Fix | Checksum: 131215cb1 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0058997 % + Global Horizontal Routing Utilization = 0.0158771 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 9.90991%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 9.00901%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 23.5294%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 131215cb1 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 131215cb1 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1455.516 ; gain = 92.055 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 1cda4acbc + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1455.516 ; gain = 92.055 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1455.516 ; gain = 92.055 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +55 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1455.516 ; gain = 103.055 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1455.516 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1465.422 ; gain = 9.906 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx +Command: report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx +Command: report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx +Command: report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +67 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file Afficheur_7SEG_route_status.rpt -pb Afficheur_7SEG_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Afficheur_7SEG_timing_summary_routed.rpt -pb Afficheur_7SEG_timing_summary_routed.pb -rpx Afficheur_7SEG_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file Afficheur_7SEG_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file Afficheur_7SEG_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Afficheur_7SEG_bus_skew_routed.rpt -pb Afficheur_7SEG_bus_skew_routed.pb -rpx Afficheur_7SEG_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force Afficheur_7SEG.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado 12-3199] DRC finished with 0 Errors +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Bitstream compression saved 15755616 bits. +Writing bitstream ./Afficheur_7SEG.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +86 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1920.316 ; gain = 405.871 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 4 15:36:15 2023... diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_2876.backup.vdi b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_2876.backup.vdi new file mode 100755 index 0000000..1ff3b4b --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_2876.backup.vdi @@ -0,0 +1,483 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Wed Oct 4 15:26:28 2023 +# Process ID: 2876 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1 +# Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source Afficheur_7SEG.tcl -notrace +Command: link_design -top Afficheur_7SEG -part xc7a35tcpg236-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2019.1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc] +WARNING: [Vivado 12-584] No ports matched 'clk'. [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc:7] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc:7] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'clk'. [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc:8] +CRITICAL WARNING: [Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_ports clk]'. [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc:8] +Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. +Finished Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 663.098 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 667.098 ; gain = 376.230 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.637 . Memory (MB): peak = 687.031 ; gain = 19.934 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 1a6e4ed6b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1200.539 ; gain = 513.508 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1a6e4ed6b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1342.637 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1a6e4ed6b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1342.637 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1b4ebe95c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1342.637 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1b4ebe95c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1342.637 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 1b4ebe95c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1342.637 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 1b4ebe95c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1342.637 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.637 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1779474dc + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1779474dc + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 1779474dc + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.637 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 1779474dc + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.637 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +24 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1342.637 ; gain = 675.539 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.637 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1342.637 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx +Command: report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.637 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 166f00538 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1342.637 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1780aa8b2 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.822 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 24b03694f + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.834 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 24b03694f + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.836 . Memory (MB): peak = 1342.637 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 24b03694f + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.837 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 24b03694f + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.839 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Phase 2.2 Global Placement Core +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2.2 Global Placement Core | Checksum: 21360a59b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 21360a59b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 21360a59b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 252e7eb40 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1e0afcabc + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1e0afcabc + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 241014ff4 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 241014ff4 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 241014ff4 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 241014ff4 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 241014ff4 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 241014ff4 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 241014ff4 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.637 ; gain = 0.000 +Phase 4.4 Final Placement Cleanup | Checksum: 241014ff4 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 241014ff4 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000 +Ending Placer Task | Checksum: 1619377e0 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.637 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +42 Infos, 3 Warnings, 2 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.637 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1352.469 ; gain = 9.832 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file Afficheur_7SEG_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1352.469 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file Afficheur_7SEG_utilization_placed.rpt -pb Afficheur_7SEG_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file Afficheur_7SEG_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1352.469 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 8901ad1c ConstDB: 0 ShapeSum: d891cac4 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 1323cb683 + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 1445.840 ; gain = 80.777 +Post Restoration Checksum: NetGraph: 6bfd2bd0 NumContArr: c63f8ab3 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 1323cb683 + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 1451.855 ; gain = 86.793 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 1323cb683 + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 1451.855 ; gain = 86.793 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 1830f2667 + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 1455.430 ; gain = 90.367 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 32 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 32 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 109c2c817 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1456.266 ; gain = 91.203 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 13e90e783 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1456.266 ; gain = 91.203 +Phase 4 Rip-up And Reroute | Checksum: 13e90e783 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1456.266 ; gain = 91.203 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 13e90e783 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1456.266 ; gain = 91.203 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 13e90e783 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1456.266 ; gain = 91.203 +Phase 6 Post Hold Fix | Checksum: 13e90e783 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1456.266 ; gain = 91.203 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.00550108 % + Global Horizontal Routing Utilization = 0.0163977 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 6.30631%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 17.1171%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 23.5294%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 13e90e783 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1456.266 ; gain = 91.203 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 13e90e783 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.332 ; gain = 93.270 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 7d951ad6 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.332 ; gain = 93.270 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.332 ; gain = 93.270 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +55 Infos, 3 Warnings, 2 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1458.332 ; gain = 105.863 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1458.332 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1468.191 ; gain = 9.859 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx +Command: report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx +Command: report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx +Command: report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +67 Infos, 4 Warnings, 2 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file Afficheur_7SEG_route_status.rpt -pb Afficheur_7SEG_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Afficheur_7SEG_timing_summary_routed.rpt -pb Afficheur_7SEG_timing_summary_routed.pb -rpx Afficheur_7SEG_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file Afficheur_7SEG_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file Afficheur_7SEG_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Afficheur_7SEG_bus_skew_routed.rpt -pb Afficheur_7SEG_bus_skew_routed.pb -rpx Afficheur_7SEG_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Wed Oct 4 15:27:17 2023... diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_3012.backup.vdi b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_3012.backup.vdi new file mode 100755 index 0000000..8cb32ad --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_3012.backup.vdi @@ -0,0 +1,485 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Wed Oct 4 14:25:17 2023 +# Process ID: 3012 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1 +# Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source Afficheur_7SEG.tcl -notrace +Command: link_design -top Afficheur_7SEG -part xc7a35tcpg236-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Project 1-479] Netlist was created with Vivado 2019.1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc] +Finished Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 662.062 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +5 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 666.074 ; gain = 366.730 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[0] expects both input and output buffering but the buffers are incomplete. +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[1] expects both input and output buffering but the buffers are incomplete. +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[2] expects both input and output buffering but the buffers are incomplete. +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[3] expects both input and output buffering but the buffers are incomplete. +INFO: [Project 1-461] DRC finished with 0 Errors, 4 Warnings +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.701 . Memory (MB): peak = 685.441 ; gain = 19.367 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 19ae0d74a + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1219.293 ; gain = 533.852 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 19ae0d74a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1362.355 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 19ae0d74a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1362.355 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 121b90616 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1362.355 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 2 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 121b90616 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1362.355 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 121b90616 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.046 . Memory (MB): peak = 1362.355 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 121b90616 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1362.355 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 2 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1362.355 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: dcf35d24 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: dcf35d24 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: dcf35d24 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.355 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: dcf35d24 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.355 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +22 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1362.355 ; gain = 696.281 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.355 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1362.355 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx +Command: report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[0] expects both input and output buffering but the buffers are incomplete. +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[1] expects both input and output buffering but the buffers are incomplete. +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[2] expects both input and output buffering but the buffers are incomplete. +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[3] expects both input and output buffering but the buffers are incomplete. +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 4 Warnings +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.355 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d81a4771 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1362.355 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +WARNING: [Place 30-87] Partially locked IO Bus is found. Following components of the IO Bus AFF are not locked: 'AFF[7]' +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 157f6087d + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.692 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 23548b804 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.729 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 23548b804 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.733 . Memory (MB): peak = 1362.355 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 23548b804 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.738 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 23548b804 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Phase 2.2 Global Placement Core +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2.2 Global Placement Core | Checksum: 166e98314 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 166e98314 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 166e98314 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1ab7c764c + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1b13b62f3 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1b13b62f3 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 2063d6819 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 2063d6819 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 2063d6819 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 2063d6819 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 2063d6819 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 2063d6819 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 2063d6819 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.355 ; gain = 0.000 +Phase 4.4 Final Placement Cleanup | Checksum: 2063d6819 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2063d6819 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000 +Ending Placer Task | Checksum: 15bec1324 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1362.355 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +40 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1362.355 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1370.227 ; gain = 7.871 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file Afficheur_7SEG_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1370.227 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file Afficheur_7SEG_utilization_placed.rpt -pb Afficheur_7SEG_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file Afficheur_7SEG_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1370.227 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC PLIO-3] Placement Constraints Check for IO constraints: Partially locked IO Bus is found. Following components of the IO Bus AFF[7:0] are not locked: AFF[7] +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 9cac4467 ConstDB: 0 ShapeSum: bf3fcebd RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 157fc0746 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1464.305 ; gain = 83.031 +Post Restoration Checksum: NetGraph: 81a272f1 NumContArr: d6599455 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 157fc0746 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1470.320 ; gain = 89.047 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 157fc0746 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1470.320 ; gain = 89.047 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 13bb64a85 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1473.793 ; gain = 92.520 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 21 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 21 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 105a773f9 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1473.883 ; gain = 92.609 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 15b772385 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1473.883 ; gain = 92.609 +Phase 4 Rip-up And Reroute | Checksum: 15b772385 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1473.883 ; gain = 92.609 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 15b772385 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1473.883 ; gain = 92.609 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 15b772385 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1473.883 ; gain = 92.609 +Phase 6 Post Hold Fix | Checksum: 15b772385 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1473.883 ; gain = 92.609 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.00829148 % + Global Horizontal Routing Utilization = 0.00390422 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 21.6216%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 9.00901%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 10.2941%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 15b772385 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1473.883 ; gain = 92.609 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 15b772385 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1475.930 ; gain = 94.656 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 144a3b6e0 + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1475.930 ; gain = 94.656 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1475.930 ; gain = 94.656 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +53 Infos, 11 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 1475.930 ; gain = 105.703 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1475.930 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1485.762 ; gain = 9.832 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx +Command: report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx +Command: report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx +Command: report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +65 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file Afficheur_7SEG_route_status.rpt -pb Afficheur_7SEG_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Afficheur_7SEG_timing_summary_routed.rpt -pb Afficheur_7SEG_timing_summary_routed.pb -rpx Afficheur_7SEG_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file Afficheur_7SEG_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file Afficheur_7SEG_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Afficheur_7SEG_bus_skew_routed.rpt -pb Afficheur_7SEG_bus_skew_routed.pb -rpx Afficheur_7SEG_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Wed Oct 4 14:26:14 2023... diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_5200.backup.vdi b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_5200.backup.vdi new file mode 100755 index 0000000..9c05335 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_5200.backup.vdi @@ -0,0 +1,487 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Wed Oct 4 15:11:40 2023 +# Process ID: 5200 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1 +# Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source Afficheur_7SEG.tcl -notrace +Command: link_design -top Afficheur_7SEG -part xc7a35tcpg236-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2019.1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc] +Finished Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 664.383 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 668.453 ; gain = 377.566 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[0] expects both input and output buffering but the buffers are incomplete. +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[1] expects both input and output buffering but the buffers are incomplete. +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[2] expects both input and output buffering but the buffers are incomplete. +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[3] expects both input and output buffering but the buffers are incomplete. +INFO: [Project 1-461] DRC finished with 0 Errors, 4 Warnings +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.647 . Memory (MB): peak = 685.898 ; gain = 17.445 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 1725a160a + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1199.828 ; gain = 513.930 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1725a160a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1342.863 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1725a160a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1342.863 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 16697666f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1342.863 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 16697666f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1342.863 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 16697666f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1342.863 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 16697666f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1342.863 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1342.863 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 13278e9b1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 13278e9b1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 13278e9b1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1342.863 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 13278e9b1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1342.863 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +24 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1342.863 ; gain = 674.410 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.863 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1342.863 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx +Command: report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[0] expects both input and output buffering but the buffers are incomplete. +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[1] expects both input and output buffering but the buffers are incomplete. +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[2] expects both input and output buffering but the buffers are incomplete. +WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port AN[3] expects both input and output buffering but the buffers are incomplete. +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 4 Warnings +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.863 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: ecbe64bb + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1342.863 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +WARNING: [Place 30-87] Partially locked IO Bus is found. Following components of the IO Bus AFF are not locked: 'AFF[7]' +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 16c9a25c7 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.576 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1d613607f + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.588 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1d613607f + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.589 . Memory (MB): peak = 1342.863 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 1d613607f + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.590 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 1d613607f + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.592 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Phase 2.2 Global Placement Core +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2.2 Global Placement Core | Checksum: 1ba501753 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 1ba501753 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1ba501753 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1e51ebdea + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1f2e580a4 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1f2e580a4 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1b679a68b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1b679a68b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1b679a68b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 1b679a68b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1b679a68b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1b679a68b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1b679a68b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.863 ; gain = 0.000 +Phase 4.4 Final Placement Cleanup | Checksum: 1b679a68b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1b679a68b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000 +Ending Placer Task | Checksum: 1383cb817 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.863 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +42 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.863 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1353.707 ; gain = 10.844 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file Afficheur_7SEG_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1353.707 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file Afficheur_7SEG_utilization_placed.rpt -pb Afficheur_7SEG_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file Afficheur_7SEG_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1353.707 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC PLIO-3] Placement Constraints Check for IO constraints: Partially locked IO Bus is found. Following components of the IO Bus AFF[7:0] are not locked: AFF[7] +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 6458cc10 ConstDB: 0 ShapeSum: d3e3ec07 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: c1d7b88d + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1446.727 ; gain = 79.938 +Post Restoration Checksum: NetGraph: 57081e63 NumContArr: 6acf9a2a Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: c1d7b88d + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1452.738 ; gain = 85.949 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: c1d7b88d + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1452.738 ; gain = 85.949 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 16c8cce5e + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1456.137 ; gain = 89.348 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 32 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 32 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +Phase 3 Initial Routing + Number of Nodes with overlaps = 0 +Phase 3 Initial Routing | Checksum: 1bf565ff7 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.086 ; gain = 91.297 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 +Phase 4.1 Global Iteration 0 | Checksum: 1bf565ff7 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.086 ; gain = 91.297 +Phase 4 Rip-up And Reroute | Checksum: 1bf565ff7 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.086 ; gain = 91.297 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 1bf565ff7 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.086 ; gain = 91.297 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 1bf565ff7 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.086 ; gain = 91.297 +Phase 6 Post Hold Fix | Checksum: 1bf565ff7 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.086 ; gain = 91.297 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0126764 % + Global Horizontal Routing Utilization = 0.00221239 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 12.6126%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 5.88235%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 1bf565ff7 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1458.086 ; gain = 91.297 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 1bf565ff7 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1460.137 ; gain = 93.348 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 14c66ac04 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1460.137 ; gain = 93.348 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1460.137 ; gain = 93.348 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +55 Infos, 11 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1460.137 ; gain = 106.430 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.137 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1469.973 ; gain = 9.836 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx +Command: report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx +Command: report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx +Command: report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +67 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file Afficheur_7SEG_route_status.rpt -pb Afficheur_7SEG_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Afficheur_7SEG_timing_summary_routed.rpt -pb Afficheur_7SEG_timing_summary_routed.pb -rpx Afficheur_7SEG_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file Afficheur_7SEG_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file Afficheur_7SEG_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Afficheur_7SEG_bus_skew_routed.rpt -pb Afficheur_7SEG_bus_skew_routed.pb -rpx Afficheur_7SEG_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Wed Oct 4 15:12:29 2023... diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_bus_skew_routed.pb b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_bus_skew_routed.pb new file mode 100755 index 0000000..3390588 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_bus_skew_routed.pb differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_bus_skew_routed.rpt b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_bus_skew_routed.rpt new file mode 100755 index 0000000..a568eaf --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_bus_skew_routed.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +| Date : Wed Oct 4 15:36:05 2023 +| Host : WIN10-TP running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file Afficheur_7SEG_bus_skew_routed.rpt -pb Afficheur_7SEG_bus_skew_routed.pb -rpx Afficheur_7SEG_bus_skew_routed.rpx +| Design : Afficheur_7SEG +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_bus_skew_routed.rpx b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_bus_skew_routed.rpx new file mode 100755 index 0000000..3b1a1f4 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_bus_skew_routed.rpx differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_clock_utilization_routed.rpt b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_clock_utilization_routed.rpt new file mode 100755 index 0000000..b05c664 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_clock_utilization_routed.rpt @@ -0,0 +1,146 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +| Date : Wed Oct 4 15:36:05 2023 +| Host : WIN10-TP running 64-bit major release (build 9200) +| Command : report_clock_utilization -file Afficheur_7SEG_clock_utilization_routed.rpt +| Design : Afficheur_7SEG +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +-------------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X0Y0 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+--------------------------+-------------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+--------------------------+-------------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 20 | 0 | | | Clk_sys_IBUF_BUFG_inst/O | Clk_sys_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+--------------------------+-------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+---------------------+--------------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+---------------------+--------------+ +| src0 | g0 | IBUF/O | IOB_X1Y26 | IOB_X1Y26 | X1Y0 | 1 | 0 | | | Clk_sys_IBUF_inst/O | Clk_sys_IBUF | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+---------------------+--------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 20 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 1 | 0 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------+ +| g0 | BUFG/O | n/a | | | | 20 | 0 | 0 | 0 | Clk_sys_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------+ +* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+-----+----+ +| | X0 | X1 | ++----+-----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 20 | 0 | ++----+-----+----+ + + +7. Clock Region Cell Placement per Global Clock: Region X0Y0 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ +| g0 | n/a | BUFG/O | None | 20 | 0 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Clk_sys_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells Clk_sys_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X1Y26 [get_ports Clk_sys] + +# Clock net "Clk_sys_IBUF_BUFG" driven by instance "Clk_sys_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_Clk_sys_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_Clk_sys_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="Clk_sys_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_Clk_sys_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0} +#endgroup diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_control_sets_placed.rpt b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_control_sets_placed.rpt new file mode 100755 index 0000000..dc9ab52 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_control_sets_placed.rpt @@ -0,0 +1,79 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +| Date : Wed Oct 4 15:35:41 2023 +| Host : WIN10-TP running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file Afficheur_7SEG_control_sets_placed.rpt +| Design : Afficheur_7SEG +| Device : xc7a35t +------------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Total control sets | 1 | +| Minimum number of control sets | 1 | +| Addition due to synthesis replication | 0 | +| Addition due to physical synthesis replication | 0 | +| Unused register locations in slices containing registers | 4 | ++----------------------------------------------------------+-------+ +* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers +** Run report_qor_suggestions for automated merging and remapping suggestions + + +2. Histogram +------------ + ++--------------------+-------+ +| Fanout | Count | ++--------------------+-------+ +| Total control sets | 1 | +| >= 0 to < 4 | 0 | +| >= 4 to < 6 | 0 | +| >= 6 to < 8 | 0 | +| >= 8 to < 10 | 0 | +| >= 10 to < 12 | 0 | +| >= 12 to < 14 | 0 | +| >= 14 to < 16 | 0 | +| >= 16 | 1 | ++--------------------+-------+ +* Control sets can be remapped at either synth_design or opt_design + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 20 | 5 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++--------------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++--------------------+---------------+------------------+------------------+----------------+ +| Clk_sys_IBUF_BUFG | | reset_IBUF | 5 | 20 | ++--------------------+---------------+------------------+------------------+----------------+ + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.pb b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.pb new file mode 100755 index 0000000..8ebaa78 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.pb differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpt b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpt new file mode 100755 index 0000000..b7e7d90 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpt @@ -0,0 +1,35 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +| Date : Wed Oct 4 15:35:39 2023 +| Host : WIN10-TP running 64-bit major release (build 9200) +| Command : report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx +| Design : Afficheur_7SEG +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 0 ++------+----------+-------------+------------+ +| Rule | Severity | Description | Violations | ++------+----------+-------------+------------+ ++------+----------+-------------+------------+ + +2. REPORT DETAILS +----------------- + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpx b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpx new file mode 100755 index 0000000..ff2ea74 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpx differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.pb b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.pb new file mode 100755 index 0000000..8ebaa78 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.pb differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpt b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpt new file mode 100755 index 0000000..20eda2d --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpt @@ -0,0 +1,35 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +| Date : Wed Oct 4 15:36:04 2023 +| Host : WIN10-TP running 64-bit major release (build 9200) +| Command : report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx +| Design : Afficheur_7SEG +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Fully Routed +------------------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 0 ++------+----------+-------------+------------+ +| Rule | Severity | Description | Violations | ++------+----------+-------------+------------+ ++------+----------+-------------+------------+ + +2. REPORT DETAILS +----------------- + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpx b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpx new file mode 100755 index 0000000..366b483 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpx differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_io_placed.rpt b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_io_placed.rpt new file mode 100755 index 0000000..65bd30c --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_io_placed.rpt @@ -0,0 +1,280 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +| Date : Wed Oct 4 15:35:41 2023 +| Host : WIN10-TP running 64-bit major release (build 9200) +| Command : report_io -file Afficheur_7SEG_io_placed.rpt +| Design : Afficheur_7SEG +| Device : xc7a35t +| Speed File : -1 +| Package : cpg236 +| Package Version : FINAL 2014-02-19 +| Package Pin Delay Version : VERS. 2.0 2014-02-19 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 13 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A2 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A4 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A6 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A8 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | | +| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | | +| A11 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| A12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| A13 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A18 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| A19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B1 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B2 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B4 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B8 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | | +| B9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | | +| B11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| B12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| B13 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| B14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B15 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B16 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B19 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C1 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| C2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C7 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | | +| C8 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| C9 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C11 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| C12 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| C13 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| C14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C15 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| D2 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D17 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| D19 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| E1 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| E2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| E3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E18 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| E19 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| F1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F3 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| F17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| F18 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| F19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G2 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| G10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | | +| G13 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| G17 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| G19 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H13 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H17 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| H18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H19 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| J1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| J7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| J17 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| J19 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| K1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| K2 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| K7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| K8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| K13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| K17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| K19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| L2 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| L3 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| L7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| L18 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| L19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| M7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| M8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| M12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| M18 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| M19 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| N3 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| N7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| N8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| N9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N17 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N19 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| P1 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| P2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| P17 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P19 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| R2 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| R17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| R18 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R19 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| T18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| T19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | AN[0] | High Range | IO_L9N_T1_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U3 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | AN[1] | High Range | IO_L11P_T1_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U5 | AFF[4] | High Range | IO_L16P_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U7 | AFF[6] | High Range | IO_L19P_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U8 | AFF[2] | High Range | IO_L14P_T2_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U10 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| U11 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| U12 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| U13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U14 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| U16 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| U19 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| V2 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V4 | AN[2] | High Range | IO_L11N_T1_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V5 | AFF[5] | High Range | IO_L16N_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| V7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | AFF[3] | High Range | IO_L14N_T2_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | | +| V10 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| V11 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | | | | +| V12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| V13 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| V14 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | reset | High Range | IO_L19N_T3_A09_D25_VREF_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| V18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V19 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| W1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W2 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W3 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| W4 | AN[3] | High Range | IO_L12N_T1_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| W5 | Clk_sys | High Range | IO_L12P_T1_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| W6 | AFF[1] | High Range | IO_L13N_T2_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| W7 | AFF[0] | High Range | IO_L13P_T2_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| W8 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| W9 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| W10 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| W11 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W13 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| W14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| W15 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| W16 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| W17 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| W18 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| W19 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.pb b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.pb new file mode 100755 index 0000000..b02990b Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.pb differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.rpt b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.rpt new file mode 100755 index 0000000..76e09ef --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.rpt @@ -0,0 +1,135 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +| Date : Wed Oct 4 15:36:04 2023 +| Host : WIN10-TP running 64-bit major release (build 9200) +| Command : report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx +| Design : Afficheur_7SEG +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Fully Routed +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 20 ++-----------+------------------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+------------------+-----------------------------+------------+ +| TIMING-17 | Critical Warning | Non-clocked sequential cell | 20 | ++-----------+------------------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#4 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#5 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#6 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#7 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#8 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#9 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#10 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#11 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#12 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#13 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#14 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#15 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#16 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#17 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#18 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#19 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#20 Critical Warning +Non-clocked sequential cell +The clock pin refresh_counter_reg[9]/C is not reached by a timing clock +Related violations: + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.rpx b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.rpx new file mode 100755 index 0000000..72ee1e3 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.rpx differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_opt.dcp b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_opt.dcp new file mode 100755 index 0000000..74b4b0a Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_opt.dcp differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_placed.dcp b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_placed.dcp new file mode 100755 index 0000000..be469cd Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_placed.dcp differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_power_routed.rpt b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_power_routed.rpt new file mode 100755 index 0000000..d631f09 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_power_routed.rpt @@ -0,0 +1,144 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +| Date : Wed Oct 4 15:36:05 2023 +| Host : WIN10-TP running 64-bit major release (build 9200) +| Command : report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx +| Design : Afficheur_7SEG +| Device : xc7a35tcpg236-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 8.293 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 8.176 | +| Device Static (W) | 0.117 | +| Effective TJA (C/W) | 5.0 | +| Max Ambient (C) | 43.5 | +| Junction Temperature (C) | 66.5 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.041 | 36 | --- | --- | +| LUT as Logic | 0.013 | 5 | 20800 | 0.02 | +| CARRY4 | 0.013 | 5 | 8150 | 0.06 | +| Register | 0.009 | 20 | 41600 | 0.05 | +| BUFG | 0.006 | 1 | 32 | 3.13 | +| Others | 0.000 | 2 | --- | --- | +| Signals | 0.114 | 34 | --- | --- | +| I/O | 8.021 | 13 | 106 | 12.26 | +| Static Power | 0.117 | | | | +| Total | 8.293 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.206 | 0.159 | 0.047 | +| Vccaux | 1.800 | 0.310 | 0.294 | 0.017 | +| Vcco33 | 3.300 | 2.270 | 2.269 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 5.0 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++----------------+-----------+ +| Name | Power (W) | ++----------------+-----------+ +| Afficheur_7SEG | 8.176 | ++----------------+-----------+ + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_power_routed.rpx b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_power_routed.rpx new file mode 100755 index 0000000..f7c5828 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_power_routed.rpx differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_power_summary_routed.pb b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_power_summary_routed.pb new file mode 100755 index 0000000..0912b0a Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_power_summary_routed.pb differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_route_status.pb b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_route_status.pb new file mode 100755 index 0000000..7a75ed7 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_route_status.pb differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_route_status.rpt b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_route_status.rpt new file mode 100755 index 0000000..4dc2802 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 70 : + # of nets not needing routing.......... : 34 : + # of internally routed nets........ : 34 : + # of routable nets..................... : 36 : + # of fully routed nets............. : 36 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_routed.dcp b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_routed.dcp new file mode 100755 index 0000000..db7743b Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_routed.dcp differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_timing_summary_routed.pb b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_timing_summary_routed.pb new file mode 100755 index 0000000..4526e93 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_timing_summary_routed.pb @@ -0,0 +1,2 @@ + +2012.4’)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_timing_summary_routed.rpt b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_timing_summary_routed.rpt new file mode 100755 index 0000000..78123dd --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_timing_summary_routed.rpt @@ -0,0 +1,174 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +| Date : Wed Oct 4 15:36:05 2023 +| Host : WIN10-TP running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file Afficheur_7SEG_timing_summary_routed.rpt -pb Afficheur_7SEG_timing_summary_routed.pb -rpx Afficheur_7SEG_timing_summary_routed.rpx -warn_on_violation +| Design : Afficheur_7SEG +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 20 register/latch pins with no clock driven by root clock pin: Clk_sys (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 40 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There is 1 input port with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 10 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_timing_summary_routed.rpx b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_timing_summary_routed.rpx new file mode 100755 index 0000000..b0da479 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_timing_summary_routed.rpx differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_utilization_placed.pb b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_utilization_placed.pb new file mode 100755 index 0000000..33529b6 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_utilization_placed.pb differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_utilization_placed.rpt b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_utilization_placed.rpt new file mode 100755 index 0000000..f833dfe --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_utilization_placed.rpt @@ -0,0 +1,203 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +| Date : Wed Oct 4 15:35:41 2023 +| Host : WIN10-TP running 64-bit major release (build 9200) +| Command : report_utilization -file Afficheur_7SEG_utilization_placed.rpt -pb Afficheur_7SEG_utilization_placed.pb +| Design : Afficheur_7SEG +| Device : 7a35tcpg236-1 +| Design State : Fully Placed +------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 5 | 0 | 20800 | 0.02 | +| LUT as Logic | 5 | 0 | 20800 | 0.02 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 20 | 0 | 41600 | 0.05 | +| Register as Flip Flop | 20 | 0 | 41600 | 0.05 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 20 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------------------------------------+------+-------+-----------+-------+ +| Slice | 6 | 0 | 8150 | 0.07 | +| SLICEL | 6 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 5 | 0 | 20800 | 0.02 | +| using O5 output only | 0 | | | | +| using O6 output only | 2 | | | | +| using O5 and O6 | 3 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 20 | 0 | 41600 | 0.05 | +| Register driven from within the Slice | 20 | | | | +| Register driven from outside the Slice | 0 | | | | +| Unique Control Sets | 1 | | 8150 | 0.01 | ++------------------------------------------+------+-------+-----------+-------+ +* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 13 | 13 | 106 | 12.26 | +| IOB Master Pads | 6 | | | | +| IOB Slave Pads | 7 | | | | +| Bonded IPADs | 0 | 0 | 10 | 0.00 | +| Bonded OPADs | 0 | 0 | 4 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 104 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 106 | 0.00 | +| OLOGIC | 0 | 0 | 106 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDCE | 20 | Flop & Latch | +| OBUF | 11 | IO | +| LUT2 | 7 | LUT | +| CARRY4 | 5 | CarryLogic | +| IBUF | 2 | IO | +| LUT1 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/ISEWrap.js b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/ISEWrap.js new file mode 100755 index 0000000..3e83de1 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/ISEWrap.sh b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/ISEWrap.sh new file mode 100755 index 0000000..f679f2e --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/gen_run.xml b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/gen_run.xml new file mode 100755 index 0000000..4ebf978 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/gen_run.xml @@ -0,0 +1,118 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/htr.txt b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/htr.txt new file mode 100755 index 0000000..c16cc93 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log Afficheur_7SEG.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/init_design.pb b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/init_design.pb new file mode 100755 index 0000000..1e33fdf Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/init_design.pb differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/opt_design.pb b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/opt_design.pb new file mode 100755 index 0000000..a3062f6 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/opt_design.pb differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/place_design.pb b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/place_design.pb new file mode 100755 index 0000000..d956036 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/place_design.pb differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/project.wdf b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/project.wdf new file mode 100755 index 0000000..9b11492 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/project.wdf @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 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+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6333633239656530336164323430373839623861306364656562396331663962:506172656e742050412070726f6a656374204944:00 +eof:3020042384 diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/route_design.pb b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/route_design.pb new file mode 100755 index 0000000..afcd1a6 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/route_design.pb differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/rundef.js b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/rundef.js new file mode 100755 index 0000000..3199cc2 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log Afficheur_7SEG.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/runme.bat b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/runme.bat new file mode 100755 index 0000000..bc78723 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/runme.log b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/runme.log new file mode 100755 index 0000000..e158302 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/runme.log @@ -0,0 +1,499 @@ + +*** Running vivado + with args -log Afficheur_7SEG.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source Afficheur_7SEG.tcl -notrace +Command: link_design -top Afficheur_7SEG -part xc7a35tcpg236-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2019.1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc] +Finished Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 662.551 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 666.586 ; gain = 375.434 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.643 . Memory (MB): peak = 686.492 ; gain = 19.906 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 1b472ca95 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1200.875 ; gain = 514.383 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1b472ca95 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1b472ca95 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1f526e7c3 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1f526e7c3 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 1f526e7c3 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 1f526e7c3 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 260393764 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 260393764 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 260393764 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 260393764 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1341.555 ; gain = 674.969 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx +Command: report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1d171f48f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1b8f8806f + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.835 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 2ac1244c8 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.847 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 2ac1244c8 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.849 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 2ac1244c8 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.850 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 2ac1244c8 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.852 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 2.2 Global Placement Core +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2.2 Global Placement Core | Checksum: 21c4ed49b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 21c4ed49b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 21c4ed49b + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18a378908 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 216e3a3c1 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 216e3a3c1 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 19592b163 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 19592b163 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 19592b163 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 19592b163 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 19592b163 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 19592b163 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 19592b163 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Phase 4.4 Final Placement Cleanup | Checksum: 19592b163 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 19592b163 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 +Ending Placer Task | Checksum: 16b3cb9b6 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +42 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1352.461 ; gain = 10.906 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file Afficheur_7SEG_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1352.461 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file Afficheur_7SEG_utilization_placed.rpt -pb Afficheur_7SEG_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file Afficheur_7SEG_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1352.461 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 92aaeef2 ConstDB: 0 ShapeSum: d891cac4 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 9fc16879 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1442.992 ; gain = 79.531 +Post Restoration Checksum: NetGraph: 769cd3b9 NumContArr: 292494c0 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 9fc16879 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1449.000 ; gain = 85.539 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 9fc16879 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1449.000 ; gain = 85.539 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 16939516a + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1452.375 ; gain = 88.914 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 32 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 32 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 106a7763c + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 131215cb1 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 +Phase 4 Rip-up And Reroute | Checksum: 131215cb1 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 131215cb1 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 131215cb1 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 +Phase 6 Post Hold Fix | Checksum: 131215cb1 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0058997 % + Global Horizontal Routing Utilization = 0.0158771 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 9.90991%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 9.00901%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 23.5294%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 131215cb1 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 131215cb1 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1455.516 ; gain = 92.055 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 1cda4acbc + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1455.516 ; gain = 92.055 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1455.516 ; gain = 92.055 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +55 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1455.516 ; gain = 103.055 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1455.516 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1465.422 ; gain = 9.906 +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx +Command: report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx +Command: report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx +Command: report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +67 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file Afficheur_7SEG_route_status.rpt -pb Afficheur_7SEG_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Afficheur_7SEG_timing_summary_routed.rpt -pb Afficheur_7SEG_timing_summary_routed.pb -rpx Afficheur_7SEG_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file Afficheur_7SEG_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file Afficheur_7SEG_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Afficheur_7SEG_bus_skew_routed.rpt -pb Afficheur_7SEG_bus_skew_routed.pb -rpx Afficheur_7SEG_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force Afficheur_7SEG.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado 12-3199] DRC finished with 0 Errors +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Bitstream compression saved 15755616 bits. +Writing bitstream ./Afficheur_7SEG.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +86 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1920.316 ; gain = 405.871 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 4 15:36:15 2023... diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/runme.sh b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/runme.sh new file mode 100755 index 0000000..4d9ce94 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/runme.sh @@ -0,0 +1,47 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin +else + PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log Afficheur_7SEG.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/usage_statistics_webtalk.html b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/usage_statistics_webtalk.html new file mode 100755 index 0000000..79b019c --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/usage_statistics_webtalk.html @@ -0,0 +1,616 @@ +Device Usage Statistics Report +

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2552052
date_generatedWed Oct 4 15:36:14 2023os_platformWIN64
product_versionVivado v2019.1 (64-bit)project_idc3c29ee03ad240789b8a0cdeeb9c1f9b
project_iteration2random_id6cd05f76f4a55b4793934a9f19deaa2b
registration_id6cd05f76f4a55b4793934a9f19deaa2broute_designTRUE
target_devicexc7a35ttarget_familyartix7
target_packagecpg236target_speed-1
tool_flowVivado

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) i5-8500 CPU @ 3.00GHzcpu_speed3000 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram12.000 GBtotal_processors1

+ + +
vivado_usage
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
gui_handlers
basedialog_cancel=1basedialog_ok=11basedialog_yes=3filesetpanel_file_set_panel_tree=6
filtertoolbar_hide_all=1filtertoolbar_show_all=2flownavigatortreepanel_flow_navigator_tree=17gettingstartedview_open_project=2
launchpanel_dont_show_this_dialog_again=1logmonitor_monitor=12maintoolbarmgr_run=9messagewithoptiondialog_dont_show_this_dialog_again=6
msgtreepanel_message_view_tree=4msgview_clear_messages_resulting_from_user_executed=5msgview_information_messages=1numjobschooser_number_of_jobs=1
pacommandnames_auto_connect_target=1pacommandnames_run_bitgen=2pacommandnames_run_implementation=3pacommandnames_run_synthesis=6
paviews_project_summary=1paviews_schematic=2programdebugtab_program_device=1programfpgadialog_program=1
projecttab_reload=1rdicommands_line_comment=3saveprojectutils_save=3
+ + + + + + + + + + + + +
java_command_handlers
autoconnecttarget=1launchprogramfpga=1openhardwaremanager=1openproject=2
openrecenttarget=1runbitgen=8runimplementation=5runschematic=2
runsynthesis=7showview=3
+ + + +
other_data
guimode=2
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
project_data
constraintsetcount=1core_container=falsecurrentimplrun=impl_1currentsynthesisrun=synth_1
default_library=xil_defaultlibdesignmode=RTLexport_simulation_activehdl=0export_simulation_ies=0
export_simulation_modelsim=0export_simulation_questa=0export_simulation_riviera=0export_simulation_vcs=0
export_simulation_xsim=0implstrategy=Vivado Implementation Defaultslaunch_simulation_activehdl=0launch_simulation_ies=0
launch_simulation_modelsim=0launch_simulation_questa=0launch_simulation_riviera=0launch_simulation_vcs=0
launch_simulation_xsim=0simulator_language=Mixedsrcsetcount=1synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDLtarget_simulator=XSimtotalimplruns=1totalsynthesisruns=1
+
+ + + + +
unisim_transformation
+ + + + + + + + + + + +
post_unisim_transformation
bufg=1carry4=5fdce=20gnd=1
ibuf=2lut1=1lut2=7obuf=11
vcc=1
+
+ + + + + + + + + + + +
pre_unisim_transformation
bufg=1carry4=5fdce=20gnd=1
ibuf=2lut1=1lut2=7obuf=11
vcc=1
+

+ + + +
report_drc
+ + + + + + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-internal=default::[not_specified]-internal_only=default::[not_specified]-messages=default::[not_specified]
-name=default::[not_specified]-no_waivers=default::[not_specified]-return_string=default::[not_specified]-ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified]-waived=default::[not_specified]
+

+ + + + +
report_methodology
+ + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified]-waived=default::[not_specified]
+
+ + + +
results
timing-17=20
+

+ + + + +
report_power
+ + + + + + + + + + + + + + + + +
command_line_options
-advisory=default::[not_specified]-append=default::[not_specified]-file=[specified]-format=default::text
-hier=default::power-hierarchical_depth=default::4-l=default::[not_specified]-name=default::[not_specified]
-no_propagation=default::[not_specified]-return_string=default::[not_specified]-rpx=[specified]-verbose=default::[not_specified]
-vid=default::[not_specified]-xpe=default::[not_specified]
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
usage
airflow=250 (LFM)ambient_temp=25.0 (C)bi-dir_toggle=12.500000bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers)board_selection=medium (10"x10")confidence_level_clock_activity=Lowconfidence_level_design_state=High
confidence_level_device_models=Highconfidence_level_internal_activity=Mediumconfidence_level_io_activity=Lowconfidence_level_overall=Low
customer=TBDcustomer_class=TBDdevstatic=0.117417die=xc7a35tcpg236-1
dsp_output_toggle=12.500000dynamic=8.175883effective_thetaja=5.0enable_probability=0.990000
family=artix7ff_toggle=12.500000flow_state=routedheatsink=medium (Medium Profile)
i/o=8.021022input_toggle=12.500000junction_temp=66.5 (C)logic=0.041129
mgtavcc_dynamic_current=0.000000mgtavcc_static_current=0.000000mgtavcc_total_current=0.000000mgtavcc_voltage=1.000000
mgtavtt_dynamic_current=0.000000mgtavtt_static_current=0.000000mgtavtt_total_current=0.000000mgtavtt_voltage=1.200000
netlist_net_matched=NAoff-chip_power=0.000000on-chip_power=8.293299output_enable=1.000000
output_load=5.000000output_toggle=12.500000package=cpg236pct_clock_constrained=1.000000
pct_inputs_defined=0platform=nt64process=typicalram_enable=50.000000
ram_write=50.000000read_saif=Falseset/reset_probability=0.000000signal_rate=False
signals=0.113732simulation_file=Nonespeedgrade=-1static_prob=False
temp_grade=commercialthetajb=7.5 (C/W)thetasa=4.6 (C/W)toggle_rate=False
user_board_temp=25.0 (C)user_effective_thetaja=5.0user_junc_temp=66.5 (C)user_thetajb=7.5 (C/W)
user_thetasa=4.6 (C/W)vccadc_dynamic_current=0.000000vccadc_static_current=0.020000vccadc_total_current=0.020000
vccadc_voltage=1.800000vccaux_dynamic_current=0.293778vccaux_io_dynamic_current=0.000000vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000vccaux_io_voltage=1.800000vccaux_static_current=0.016636vccaux_total_current=0.310414
vccaux_voltage=1.800000vccbram_dynamic_current=0.000000vccbram_static_current=0.000967vccbram_total_current=0.000967
vccbram_voltage=1.000000vccint_dynamic_current=0.158861vccint_static_current=0.047205vccint_total_current=0.206066
vccint_voltage=1.000000vcco12_dynamic_current=0.000000vcco12_static_current=0.000000vcco12_total_current=0.000000
vcco12_voltage=1.200000vcco135_dynamic_current=0.000000vcco135_static_current=0.000000vcco135_total_current=0.000000
vcco135_voltage=1.350000vcco15_dynamic_current=0.000000vcco15_static_current=0.000000vcco15_total_current=0.000000
vcco15_voltage=1.500000vcco18_dynamic_current=0.000000vcco18_static_current=0.000000vcco18_total_current=0.000000
vcco18_voltage=1.800000vcco25_dynamic_current=0.000000vcco25_static_current=0.000000vcco25_total_current=0.000000
vcco25_voltage=2.500000vcco33_dynamic_current=2.269158vcco33_static_current=0.001000vcco33_total_current=2.270158
vcco33_voltage=3.300000version=2019.1
+

+ + + + + + + + + +
report_utilization
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
clocking
bufgctrl_available=32bufgctrl_fixed=0bufgctrl_used=1bufgctrl_util_percentage=3.13
bufhce_available=72bufhce_fixed=0bufhce_used=0bufhce_util_percentage=0.00
bufio_available=20bufio_fixed=0bufio_used=0bufio_util_percentage=0.00
bufmrce_available=10bufmrce_fixed=0bufmrce_used=0bufmrce_util_percentage=0.00
bufr_available=20bufr_fixed=0bufr_used=0bufr_util_percentage=0.00
mmcme2_adv_available=5mmcme2_adv_fixed=0mmcme2_adv_used=0mmcme2_adv_util_percentage=0.00
plle2_adv_available=5plle2_adv_fixed=0plle2_adv_used=0plle2_adv_util_percentage=0.00
+
+ + + + + + +
dsp
dsps_available=90dsps_fixed=0dsps_used=0dsps_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
io_standard
blvds_25=0diff_hstl_i=0diff_hstl_i_18=0diff_hstl_ii=0
diff_hstl_ii_18=0diff_hsul_12=0diff_mobile_ddr=0diff_sstl135=0
diff_sstl135_r=0diff_sstl15=0diff_sstl15_r=0diff_sstl18_i=0
diff_sstl18_ii=0hstl_i=0hstl_i_18=0hstl_ii=0
hstl_ii_18=0hsul_12=0lvcmos12=0lvcmos15=0
lvcmos18=0lvcmos25=0lvcmos33=1lvds_25=0
lvttl=0mini_lvds_25=0mobile_ddr=0pci33_3=0
ppds_25=0rsds_25=0sstl135=0sstl135_r=0
sstl15=0sstl15_r=0sstl18_i=0sstl18_ii=0
tmds_33=0
+
+ + + + + + + + + + + + + + +
memory
block_ram_tile_available=50block_ram_tile_fixed=0block_ram_tile_used=0block_ram_tile_util_percentage=0.00
ramb18_available=100ramb18_fixed=0ramb18_used=0ramb18_util_percentage=0.00
ramb36_fifo_available=50ramb36_fifo_fixed=0ramb36_fifo_used=0ramb36_fifo_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + +
primitives
bufg_functional_category=Clockbufg_used=1carry4_functional_category=CarryLogiccarry4_used=5
fdce_functional_category=Flop & Latchfdce_used=20ibuf_functional_category=IOibuf_used=2
lut1_functional_category=LUTlut1_used=1lut2_functional_category=LUTlut2_used=7
obuf_functional_category=IOobuf_used=11
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
slice_logic
f7_muxes_available=16300f7_muxes_fixed=0f7_muxes_used=0f7_muxes_util_percentage=0.00
f8_muxes_available=8150f8_muxes_fixed=0f8_muxes_used=0f8_muxes_util_percentage=0.00
lut_as_logic_available=20800lut_as_logic_fixed=0lut_as_logic_used=5lut_as_logic_util_percentage=0.02
lut_as_memory_available=9600lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=41600register_as_flip_flop_fixed=0register_as_flip_flop_used=20register_as_flip_flop_util_percentage=0.05
register_as_latch_available=41600register_as_latch_fixed=0register_as_latch_used=0register_as_latch_util_percentage=0.00
slice_luts_available=20800slice_luts_fixed=0slice_luts_used=5slice_luts_util_percentage=0.02
slice_registers_available=41600slice_registers_fixed=0slice_registers_used=20slice_registers_util_percentage=0.05
lut_as_distributed_ram_fixed=0lut_as_distributed_ram_used=0lut_as_logic_available=20800lut_as_logic_fixed=0
lut_as_logic_used=5lut_as_logic_util_percentage=0.02lut_as_memory_available=9600lut_as_memory_fixed=0
lut_as_memory_used=0lut_as_memory_util_percentage=0.00lut_as_shift_register_fixed=0lut_as_shift_register_used=0
register_driven_from_outside_the_slice_fixed=0register_driven_from_outside_the_slice_used=0register_driven_from_within_the_slice_fixed=0register_driven_from_within_the_slice_used=20
slice_available=8150slice_fixed=0slice_registers_available=41600slice_registers_fixed=0
slice_registers_used=20slice_registers_util_percentage=0.05slice_used=6slice_util_percentage=0.07
slicel_fixed=0slicel_used=6slicem_fixed=0slicem_used=0
unique_control_sets_available=8150unique_control_sets_fixed=8150unique_control_sets_used=1unique_control_sets_util_percentage=0.01
using_o5_and_o6_fixed=0.01using_o5_and_o6_used=3using_o5_output_only_fixed=3using_o5_output_only_used=0
using_o6_output_only_fixed=0using_o6_output_only_used=2
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
specific_feature
bscane2_available=4bscane2_fixed=0bscane2_used=0bscane2_util_percentage=0.00
capturee2_available=1capturee2_fixed=0capturee2_used=0capturee2_util_percentage=0.00
dna_port_available=1dna_port_fixed=0dna_port_used=0dna_port_util_percentage=0.00
efuse_usr_available=1efuse_usr_fixed=0efuse_usr_used=0efuse_usr_util_percentage=0.00
frame_ecce2_available=1frame_ecce2_fixed=0frame_ecce2_used=0frame_ecce2_util_percentage=0.00
icape2_available=2icape2_fixed=0icape2_used=0icape2_util_percentage=0.00
pcie_2_1_available=1pcie_2_1_fixed=0pcie_2_1_used=0pcie_2_1_util_percentage=0.00
startupe2_available=1startupe2_fixed=0startupe2_used=0startupe2_util_percentage=0.00
xadc_available=1xadc_fixed=0xadc_used=0xadc_util_percentage=0.00
+

+ + + + +
synthesis
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-assert=default::[not_specified]-bufg=default::12-cascade_dsp=default::auto-constrset=default::[not_specified]
-control_set_opt_threshold=default::auto-directive=default::default-fanout_limit=default::10000-flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto-gated_clock_conversion=default::off-generic=default::[not_specified]-include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified]-max_bram=default::-1-max_bram_cascade_height=default::-1-max_dsp=default::-1
-max_uram=default::-1-max_uram_cascade_height=default::-1-mode=default::default-name=default::[not_specified]
-no_lc=default::[not_specified]-no_srlextract=default::[not_specified]-no_timing_driven=default::[not_specified]-part=xc7a35tcpg236-1
-resource_sharing=default::auto-retiming=default::[not_specified]-rtl=default::[not_specified]-rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified]-seu_protect=default::none-sfcu=default::[not_specified]-shreg_min_size=default::3
-top=Afficheur_7SEG-verilog_define=default::[not_specified]
+
+ + + + + + +
usage
elapsed=00:00:26shls_ip=0memory_gain=600.383MBmemory_peak=908.391MB
+

+ + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/usage_statistics_webtalk.xml b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/usage_statistics_webtalk.xml new file mode 100755 index 0000000..fe795d4 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,556 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+ + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + +
+
+ +
+
+
+
+ + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
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+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
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+
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+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
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+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado.jou b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado.jou new file mode 100755 index 0000000..f5120b6 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Wed Oct 4 15:35:14 2023 +# Process ID: 9160 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1 +# Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source Afficheur_7SEG.tcl -notrace diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado.pb b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado.pb new file mode 100755 index 0000000..ec239df Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado.pb differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_2876.backup.jou b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_2876.backup.jou new file mode 100755 index 0000000..13970dd --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_2876.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Wed Oct 4 15:26:28 2023 +# Process ID: 2876 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1 +# Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source Afficheur_7SEG.tcl -notrace diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_3012.backup.jou b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_3012.backup.jou new file mode 100755 index 0000000..30f096a --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_3012.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Wed Oct 4 14:25:17 2023 +# Process ID: 3012 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1 +# Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source Afficheur_7SEG.tcl -notrace diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_5200.backup.jou b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_5200.backup.jou new file mode 100755 index 0000000..1dc4d2b --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_5200.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Wed Oct 4 15:11:40 2023 +# Process ID: 5200 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1 +# Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source Afficheur_7SEG.tcl -notrace diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_8792.backup.jou b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_8792.backup.jou new file mode 100755 index 0000000..69a512c --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/vivado_8792.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Wed Oct 4 15:12:47 2023 +# Process ID: 8792 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1 +# Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source Afficheur_7SEG.tcl -notrace diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/write_bitstream.pb b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/write_bitstream.pb new file mode 100755 index 0000000..a8303f1 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/write_bitstream.pb differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/.Vivado_Synthesis.queue.rst b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/.Vivado_Synthesis.queue.rst new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/.Vivado_Synthesis.queue.rst diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/.Xil/Afficheur_7SEG_propImpl.xdc b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/.Xil/Afficheur_7SEG_propImpl.xdc new file mode 100755 index 0000000..5fb0cc9 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/.Xil/Afficheur_7SEG_propImpl.xdc @@ -0,0 +1,27 @@ +set_property SRC_FILE_INFO {cfile:C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc rfile:../../../Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports Clk_sys] +set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {reset}] +set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports {AFF[0]}] +set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports {AFF[1]}] +set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports {AFF[2]}] +set_property src_info {type:XDC file:1 line:53 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports {AFF[3]}] +set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports {AFF[4]}] +set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports {AFF[5]}] +set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports {AFF[6]}] +set_property src_info {type:XDC file:1 line:60 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports {AN[0]}] +set_property src_info {type:XDC file:1 line:61 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports {AN[1]}] +set_property src_info {type:XDC file:1 line:62 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports {AN[2]}] +set_property src_info {type:XDC file:1 line:63 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {AN[3]}] diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/.vivado.begin.rst b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/.vivado.begin.rst new file mode 100755 index 0000000..3fcd9f3 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/.vivado.end.rst b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/.vivado.end.rst new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/.vivado.end.rst diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG.dcp b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG.dcp new file mode 100755 index 0000000..6efa2b1 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG.dcp differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG.tcl b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG.tcl new file mode 100755 index 0000000..6881a8c --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG.tcl @@ -0,0 +1,60 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param chipscope.maxJobs 1 +set_param synth.incrementalSynthesisCache C:/Xilinx/Vivado/2019.1/bin/.Xil/Vivado-7292-WIN10-TP/incrSyn +set_param xicom.use_bs_reader 1 +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 +create_project -in_memory -part xc7a35tcpg236-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.cache/wt [current_project] +set_property parent.project_path C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language VHDL [current_project] +set_property board_part digilentinc.com:basys3:part0:1.2 [current_project] +set_property ip_output_repo c:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_vhdl -library xil_defaultlib C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/sources_1/new/Afficheur_7SEG.vhd +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc +set_property used_in_implementation false [get_files C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc] + +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +synth_design -top Afficheur_7SEG -part xc7a35tcpg236-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef Afficheur_7SEG.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file Afficheur_7SEG_utilization_synth.rpt -pb Afficheur_7SEG_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG.vds b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG.vds new file mode 100755 index 0000000..d36f21b --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG.vds @@ -0,0 +1,273 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Wed Oct 4 15:34:37 2023 +# Process ID: 10000 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1 +# Command line: vivado.exe -log Afficheur_7SEG.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Afficheur_7SEG.tcl +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG.vds +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source Afficheur_7SEG.tcl -notrace +Command: synth_design -top Afficheur_7SEG -part xc7a35tcpg236-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 2784 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 727.012 ; gain = 177.500 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'Afficheur_7SEG' [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/sources_1/new/Afficheur_7SEG.vhd:43] +INFO: [Synth 8-256] done synthesizing module 'Afficheur_7SEG' (1#1) [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/sources_1/new/Afficheur_7SEG.vhd:43] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 790.121 ; gain = 240.609 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 790.121 ; gain = 240.609 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 790.121 ; gain = 240.609 +--------------------------------------------------------------------------------- +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc] +Finished Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/Afficheur_7SEG_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/Afficheur_7SEG_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 872.348 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 872.348 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 872.348 ; gain = 322.836 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcpg236-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 872.348 ; gain = 322.836 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 872.348 ; gain = 322.836 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 872.348 ; gain = 322.836 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Muxes : + 4 Input 7 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module Afficheur_7SEG +Detailed RTL Component Info : ++---Muxes : + 4 Input 7 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +WARNING: [Synth 8-3917] design Afficheur_7SEG has port AFF[1] driven by constant 0 +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 872.348 ; gain = 322.836 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 882.926 ; gain = 333.414 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 883.000 ; gain = 333.488 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 892.578 ; gain = 343.066 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 908.391 ; gain = 358.879 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 908.391 ; gain = 358.879 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 908.391 ; gain = 358.879 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 908.391 ; gain = 358.879 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 908.391 ; gain = 358.879 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 908.391 ; gain = 358.879 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 5| +|3 |LUT1 | 1| +|4 |LUT2 | 7| +|5 |FDCE | 20| +|6 |IBUF | 2| +|7 |OBUF | 11| ++------+-------+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 47| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 908.391 ; gain = 358.879 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:19 . Memory (MB): peak = 908.391 ; gain = 276.652 +Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 908.391 ; gain = 358.879 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 923.996 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 923.996 ; gain = 632.125 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 923.996 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file Afficheur_7SEG_utilization_synth.rpt -pb Afficheur_7SEG_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Wed Oct 4 15:35:07 2023... diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG_utilization_synth.pb b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG_utilization_synth.pb new file mode 100755 index 0000000..33529b6 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG_utilization_synth.pb differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG_utilization_synth.rpt b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG_utilization_synth.rpt new file mode 100755 index 0000000..3833614 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG_utilization_synth.rpt @@ -0,0 +1,177 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +| Date : Wed Oct 4 15:35:07 2023 +| Host : WIN10-TP running 64-bit major release (build 9200) +| Command : report_utilization -file Afficheur_7SEG_utilization_synth.rpt -pb Afficheur_7SEG_utilization_synth.pb +| Design : Afficheur_7SEG +| Device : 7a35tcpg236-1 +| Design State : Synthesized +----------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 5 | 0 | 20800 | 0.02 | +| LUT as Logic | 5 | 0 | 20800 | 0.02 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 20 | 0 | 41600 | 0.05 | +| Register as Flip Flop | 20 | 0 | 41600 | 0.05 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 20 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 13 | 0 | 106 | 12.26 | +| Bonded IPADs | 0 | 0 | 10 | 0.00 | +| Bonded OPADs | 0 | 0 | 4 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 104 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 106 | 0.00 | +| OLOGIC | 0 | 0 | 106 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDCE | 20 | Flop & Latch | +| OBUF | 11 | IO | +| LUT2 | 7 | LUT | +| CARRY4 | 5 | CarryLogic | +| IBUF | 2 | IO | +| LUT1 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/ISEWrap.js b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/ISEWrap.js new file mode 100755 index 0000000..3e83de1 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/ISEWrap.sh b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/ISEWrap.sh new file mode 100755 index 0000000..f679f2e --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/__synthesis_is_complete__ b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/__synthesis_is_complete__ new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/__synthesis_is_complete__ diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/gen_run.xml b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/gen_run.xml new file mode 100755 index 0000000..8504c13 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/gen_run.xml @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/htr.txt b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/htr.txt new file mode 100755 index 0000000..14cd321 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log Afficheur_7SEG.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Afficheur_7SEG.tcl diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/rundef.js b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/rundef.js new file mode 100755 index 0000000..2ea0411 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/rundef.js @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log Afficheur_7SEG.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Afficheur_7SEG.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/runme.bat b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/runme.bat new file mode 100755 index 0000000..bc78723 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/runme.log b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/runme.log new file mode 100755 index 0000000..ede3f86 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/runme.log @@ -0,0 +1,272 @@ + +*** Running vivado + with args -log Afficheur_7SEG.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Afficheur_7SEG.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source Afficheur_7SEG.tcl -notrace +Command: synth_design -top Afficheur_7SEG -part xc7a35tcpg236-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 2784 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 727.012 ; gain = 177.500 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'Afficheur_7SEG' [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/sources_1/new/Afficheur_7SEG.vhd:43] +INFO: [Synth 8-256] done synthesizing module 'Afficheur_7SEG' (1#1) [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/sources_1/new/Afficheur_7SEG.vhd:43] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 790.121 ; gain = 240.609 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 790.121 ; gain = 240.609 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 790.121 ; gain = 240.609 +--------------------------------------------------------------------------------- +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc] +Finished Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/Afficheur_7SEG_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/Afficheur_7SEG_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 872.348 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 872.348 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 872.348 ; gain = 322.836 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcpg236-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 872.348 ; gain = 322.836 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 872.348 ; gain = 322.836 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 872.348 ; gain = 322.836 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Muxes : + 4 Input 7 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module Afficheur_7SEG +Detailed RTL Component Info : ++---Muxes : + 4 Input 7 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +WARNING: [Synth 8-3917] design Afficheur_7SEG has port AFF[1] driven by constant 0 +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 872.348 ; gain = 322.836 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 882.926 ; gain = 333.414 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 883.000 ; gain = 333.488 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 892.578 ; gain = 343.066 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 908.391 ; gain = 358.879 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 908.391 ; gain = 358.879 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 908.391 ; gain = 358.879 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 908.391 ; gain = 358.879 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 908.391 ; gain = 358.879 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 908.391 ; gain = 358.879 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 5| +|3 |LUT1 | 1| +|4 |LUT2 | 7| +|5 |FDCE | 20| +|6 |IBUF | 2| +|7 |OBUF | 11| ++------+-------+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 47| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 908.391 ; gain = 358.879 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:19 . Memory (MB): peak = 908.391 ; gain = 276.652 +Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 908.391 ; gain = 358.879 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 923.996 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 923.996 ; gain = 632.125 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 923.996 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file Afficheur_7SEG_utilization_synth.rpt -pb Afficheur_7SEG_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Wed Oct 4 15:35:07 2023... diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/runme.sh b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/runme.sh new file mode 100755 index 0000000..c349449 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin +else + PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log Afficheur_7SEG.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Afficheur_7SEG.tcl diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/vivado.jou b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/vivado.jou new file mode 100755 index 0000000..b605d5b --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Wed Oct 4 15:34:37 2023 +# Process ID: 10000 +# Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1 +# Command line: vivado.exe -log Afficheur_7SEG.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Afficheur_7SEG.tcl +# Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/Afficheur_7SEG.vds +# Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source Afficheur_7SEG.tcl -notrace diff --git a/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/vivado.pb b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/vivado.pb new file mode 100755 index 0000000..92f3d06 Binary files /dev/null and b/Afficheur_7SEG/Afficheur_7SEG.runs/synth_1/vivado.pb differ diff --git a/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc b/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc new file mode 100755 index 0000000..28b5ef0 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc @@ -0,0 +1,159 @@ +## This file is a general .xdc for the Basys3 rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports Clk_sys] +#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] + + +## Switches +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {reset}] +#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {sw[1]}] +#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {sw[2]}] +#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}] +#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}] +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {sw[5]}] +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports {sw[6]}] +#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports {sw[7]}] +#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports {sw[8]}] +#set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {sw[9]}] +#set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {sw[10]}] +#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {sw[11]}] +#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {sw[12]}] +#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {sw[13]}] +#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {sw[14]}] +#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {sw[15]}] + + +## LEDs +#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports {led[0]}] +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports {led[1]}] +#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports {led[2]}] +#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports {led[3]}] +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports {led[4]}] +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports {led[5]}] +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports {led[6]}] +#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports {led[7]}] +#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports {led[8]}] +#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports {led[9]}] +#set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports {led[10]}] +#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports {led[11]}] +#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports {led[12]}] +#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports {led[13]}] +#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports {led[14]}] +#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports {led[15]}] + + +##7 Segment Display +set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports {AFF[0]}] +set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports {AFF[1]}] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports {AFF[2]}] +set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports {AFF[3]}] +set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports {AFF[4]}] +set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports {AFF[5]}] +set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports {AFF[6]}] + +#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports dp] + +set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports {AN[0]}] +set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports {AN[1]}] +set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports {AN[2]}] +set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {AN[3]}] + + +##Buttons +#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC] +#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports btnU] +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports btnL] +#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports btnR] +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports btnD] + + +##Pmod Header JA +#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports {JA[0]];#Sch name = JA1 +#set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports {JA[1]}];#Sch name = JA2 +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports {JA[2]}];#Sch name = JA3 +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports {JA[3]}];#Sch name = JA4 +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports {JA[4]}];#Sch name = JA7 +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports {JA[5]}];#Sch name = JA8 +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports {JA[6]}];#Sch name = JA9 +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports {JA[7]}];#Sch name = JA10 + +##Pmod Header JB +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports {JB[0]}];#Sch name = JB1 +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports {JB[1]}];#Sch name = JB2 +#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports {JB[2]}];#Sch name = JB3 +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports {JB[3]}];#Sch name = JB4 +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports {JB[4]}];#Sch name = JB7 +#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports {JB[5]}];#Sch name = JB8 +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports {JB[6]}];#Sch name = JB9 +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports {JB[7]}];#Sch name = JB10 + +##Pmod Header JC +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports {JC[0]}];#Sch name = JC1 +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports {JC[1]}];#Sch name = JC2 +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports {JC[2]}];#Sch name = JC3 +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports {JC[3]}];#Sch name = JC4 +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports {JC[4]}];#Sch name = JC7 +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports {JC[5]}];#Sch name = JC8 +#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports {JC[6]}];#Sch name = JC9 +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports {JC[7]}];#Sch name = JC10 + +##Pmod Header JXADC +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[0]}];#Sch name = XA1_P +#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[1]}];#Sch name = XA2_P +#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[2]}];#Sch name = XA3_P +#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[3]}];#Sch name = XA4_P +#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[4]}];#Sch name = XA1_N +#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[5]}];#Sch name = XA2_N +#set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[6]}];#Sch name = XA3_N +#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[7]}];#Sch name = XA4_N + + +##VGA Connector +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[0]}] +#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[1]}] +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[2]}] +#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[3]}] +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[0]}] +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[1]}] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[2]}] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[3]}] +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[0]}] +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[1]}] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[2]}] +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[3]}] +#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports Hsync] +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports Vsync] + + +##USB-RS232 Interface +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports RsRx] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports RsTx] + + +##USB HID (PS/2) +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Clk] +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Data] + + +##Quad SPI Flash +##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the +##STARTUPE2 primitive. +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[0]}] +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[1]}] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[2]}] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[3]}] +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports QspiCSn] + + +## Configuration options, can be used for all designs +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] + +## SPI configuration mode options for QSPI boot, can be used for all designs +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] \ No newline at end of file diff --git a/Afficheur_7SEG/Afficheur_7SEG.srcs/sources_1/new/Afficheur_7SEG.vhd b/Afficheur_7SEG/Afficheur_7SEG.srcs/sources_1/new/Afficheur_7SEG.vhd new file mode 100755 index 0000000..76cfda3 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.srcs/sources_1/new/Afficheur_7SEG.vhd @@ -0,0 +1,73 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 27.09.2023 11:56:26 +-- Design Name: +-- Module Name: Afficheur_7SEG - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Afficheur_7SEG is + Port ( Clk_sys : in STD_LOGIC; + reset : in STD_LOGIC; + AFF : out STD_LOGIC_VECTOR (6 downto 0); + AN : out STD_LOGIC_VECTOR (3 downto 0)); +end Afficheur_7SEG; + +architecture Behavioral of Afficheur_7SEG is + +signal LED_activating_counter: std_logic_vector(1 downto 0); +signal refresh_counter: STD_LOGIC_VECTOR (19 downto 0); +begin +CLK_refresh : process (Clk_sys, reset) +begin + if reset='1' then + refresh_counter <= (others => '0'); + elsif rising_edge(Clk_sys) then + refresh_counter <= refresh_counter + 1; + end if; +end process; +---------- +---------- +LED_activating_counter <= refresh_counter(19 downto 18); +Afficheur: process(LED_activating_counter) +begin + case LED_activating_counter is + when "00" => AN <= "0111"; + AFF <= "1111001";-- afficher 1 + when "01" => AN <= "1011"; + AFF <= "0100100"; -- 0100100-- afficher 2 + when "10" => AN <= "1101"; + AFF <= "0110000"; --0110000 afficher 3 + when "11" => AN <= "1110"; + AFF <= "0011001"; --0011001 afficher 4 + end case; +end process; + +end Behavioral; diff --git a/Afficheur_7SEG/Afficheur_7SEG.srcs/sources_1/new/Afficheur_POLYTECH.vhd b/Afficheur_7SEG/Afficheur_7SEG.srcs/sources_1/new/Afficheur_POLYTECH.vhd new file mode 100755 index 0000000..f0b9ee0 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.srcs/sources_1/new/Afficheur_POLYTECH.vhd @@ -0,0 +1,96 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 27.09.2023 11:56:26 +-- Design Name: +-- Module Name: Afficheur_7SEG - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Afficheur_POLYTECH is + Port ( Clk_sys : in STD_LOGIC; + reset : in STD_LOGIC; + AFF : out STD_LOGIC_VECTOR (6 downto 0); + AN : out STD_LOGIC_VECTOR (3 downto 0)); +end Afficheur_POLYTECH; + +architecture Behavioral of Afficheur_POLYTECH is + +signal LED_activating_counter: std_logic_vector(1 downto 0); +signal refresh_counter: STD_LOGIC_VECTOR (19 downto 0); +signal count_clk: std_logic_vector (2 downto 0); +begin +CLK_refresh : process (Clk_sys, reset) +begin + if reset='1' then + refresh_counter <= (others => '0'); + elsif rising_edge(Clk_sys) then + refresh_counter <= refresh_counter + 1; + end if; +end process; +---------- +count : process (Clk_sys) +begin + if reset='1' then + count_clk <= (others => '0'); + elsif rising_edge(Clk_sys) then + count_clk <= count_clk + 1; + end if; +end process; +---------- +LED_activating_counter <= refresh_counter(19 downto 18); +Afficheur: process(LED_activating_counter, count_clk) +begin + if count_clk = "000" then + case LED_activating_counter is + when "00" => AN <= "0111"; + AFF <= "0001100";-- afficher + when "01" => AN <= "1011"; + AFF <= "1000000"; -- afficher O + when "10" => AN <= "1101"; + AFF <= "1000111"; -- afficher L + when "11" => AN <= "1110"; + AFF <= "0011001"; -- afficher Y + end case; + elsif count_clk = "001" then + case LED_activating_counter is + when "00" => AN <= "0111"; + AFF <= "0001100";-- afficher O + when "01" => AN <= "1011"; + AFF <= "1000000"; -- afficher L + when "10" => AN <= "1101"; + AFF <= "1000111"; -- afficher Y + when "11" => AN <= "1110"; + AFF <= "0011001"; -- afficher T + end case; + ---------- a continuer ... + end if; +end process; + +end Behavioral; diff --git a/Afficheur_7SEG/Afficheur_7SEG.xpr b/Afficheur_7SEG/Afficheur_7SEG.xpr new file mode 100755 index 0000000..18f98e4 --- /dev/null +++ b/Afficheur_7SEG/Afficheur_7SEG.xpr @@ -0,0 +1,219 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Afficheur_7SEG/Basys-3-Master.xdc b/Afficheur_7SEG/Basys-3-Master.xdc new file mode 100755 index 0000000..458e8f9 --- /dev/null +++ b/Afficheur_7SEG/Basys-3-Master.xdc @@ -0,0 +1,159 @@ +## This file is a general .xdc for the Basys3 rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +#set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports clk] +#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] + + +## Switches +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {sw[0]}] +#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {sw[1]}] +#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {sw[2]}] +#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}] +#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}] +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {sw[5]}] +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports {sw[6]}] +#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports {sw[7]}] +#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports {sw[8]}] +#set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {sw[9]}] +#set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {sw[10]}] +#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {sw[11]}] +#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {sw[12]}] +#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {sw[13]}] +#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {sw[14]}] +#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {sw[15]}] + + +## LEDs +#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports {led[0]}] +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports {led[1]}] +#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports {led[2]}] +#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports {led[3]}] +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports {led[4]}] +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports {led[5]}] +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports {led[6]}] +#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports {led[7]}] +#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports {led[8]}] +#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports {led[9]}] +#set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports {led[10]}] +#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports {led[11]}] +#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports {led[12]}] +#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports {led[13]}] +#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports {led[14]}] +#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports {led[15]}] + + +##7 Segment Display +#set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports {seg[0]}] +#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports {seg[1]}] +#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports {seg[2]}] +#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports {seg[3]}] +#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports {seg[4]}] +#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports {seg[5]}] +#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports {seg[6]}] + +#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports dp] + +#set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports {an[0]}] +#set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports {an[1]}] +#set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports {an[2]}] +#set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {an[3]}] + + +##Buttons +#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC] +#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports btnU] +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports btnL] +#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports btnR] +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports btnD] + + +##Pmod Header JA +#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports {JA[0]];#Sch name = JA1 +#set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports {JA[1]}];#Sch name = JA2 +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports {JA[2]}];#Sch name = JA3 +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports {JA[3]}];#Sch name = JA4 +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports {JA[4]}];#Sch name = JA7 +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports {JA[5]}];#Sch name = JA8 +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports {JA[6]}];#Sch name = JA9 +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports {JA[7]}];#Sch name = JA10 + +##Pmod Header JB +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports {JB[0]}];#Sch name = JB1 +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports {JB[1]}];#Sch name = JB2 +#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports {JB[2]}];#Sch name = JB3 +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports {JB[3]}];#Sch name = JB4 +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports {JB[4]}];#Sch name = JB7 +#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports {JB[5]}];#Sch name = JB8 +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports {JB[6]}];#Sch name = JB9 +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports {JB[7]}];#Sch name = JB10 + +##Pmod Header JC +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports {JC[0]}];#Sch name = JC1 +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports {JC[1]}];#Sch name = JC2 +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports {JC[2]}];#Sch name = JC3 +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports {JC[3]}];#Sch name = JC4 +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports {JC[4]}];#Sch name = JC7 +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports {JC[5]}];#Sch name = JC8 +#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports {JC[6]}];#Sch name = JC9 +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports {JC[7]}];#Sch name = JC10 + +##Pmod Header JXADC +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[0]}];#Sch name = XA1_P +#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[1]}];#Sch name = XA2_P +#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[2]}];#Sch name = XA3_P +#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[3]}];#Sch name = XA4_P +#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[4]}];#Sch name = XA1_N +#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[5]}];#Sch name = XA2_N +#set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[6]}];#Sch name = XA3_N +#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[7]}];#Sch name = XA4_N + + +##VGA Connector +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[0]}] +#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[1]}] +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[2]}] +#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[3]}] +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[0]}] +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[1]}] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[2]}] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[3]}] +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[0]}] +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[1]}] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[2]}] +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[3]}] +#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports Hsync] +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports Vsync] + + +##USB-RS232 Interface +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports RsRx] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports RsTx] + + +##USB HID (PS/2) +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Clk] +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Data] + + +##Quad SPI Flash +##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the +##STARTUPE2 primitive. +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[0]}] +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[1]}] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[2]}] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[3]}] +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports QspiCSn] + + +## Configuration options, can be used for all designs +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] + +## SPI configuration mode options for QSPI boot, can be used for all designs +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] \ No newline at end of file diff --git a/README.md b/README.md new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/README.md diff --git a/TP_VGA/.~lock.Basys-3-Master.xdc# b/TP_VGA/.~lock.Basys-3-Master.xdc# new file mode 100644 index 0000000..e7443e5 --- /dev/null +++ b/TP_VGA/.~lock.Basys-3-Master.xdc# @@ -0,0 +1 @@ +,belhasna,gedeon02,30.10.2023 00:34,file:///home/b/e/belhasna/.config/libreoffice/4; \ No newline at end of file diff --git a/TP_VGA/Basys-3-Master.xdc b/TP_VGA/Basys-3-Master.xdc new file mode 100755 index 0000000..cef6eb0 --- /dev/null +++ b/TP_VGA/Basys-3-Master.xdc @@ -0,0 +1,159 @@ +## This file is a general .xdc for the Basys3 rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +#set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports clk] +#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] + + +## Switches +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {sw[0]}] +#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {sw[1]}] +#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {sw[2]}] +#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}] +#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}] +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {sw[5]}] +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports {sw[6]}] +#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports {sw[7]}] +#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports {sw[8]}] +#set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {sw[9]}] +#set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {sw[10]}] +#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {sw[11]}] +#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {sw[12]}] +#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {sw[13]}] +#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {sw[14]}] +#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {sw[15]}] + + +## LEDs +#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports {led[0]}] +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports {led[1]}] +#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports {led[2]}] +#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports {led[3]}] +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports {led[4]}] +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports {led[5]}] +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports {led[6]}] +#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports {led[7]}] +#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports {led[8]}] +#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports {led[9]}] +#set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports {led[10]}] +#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports {led[11]}] +#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports {led[12]}] +#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports {led[13]}] +#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports {led[14]}] +#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports {led[15]}] + + +##7 Segment Display +#set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports {seg[0]}] +#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports {seg[1]}] +#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports {seg[2]}] +#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports {seg[3]}] +#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports {seg[4]}] +#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports {seg[5]}] +#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports {seg[6]}] + +#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports dp] + +#set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports {an[0]}] +#set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports {an[1]}] +#set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports {an[2]}] +#set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {an[3]}] + + +##Buttons +#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC] +#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports btnU] +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports btnL] +#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports btnR] +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports btnD] + + +##Pmod Header JA +#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports {JA[0]];#Sch name = JA1 +#set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports {JA[1]}];#Sch name = JA2 +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports {JA[2]}];#Sch name = JA3 +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports {JA[3]}];#Sch name = JA4 +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports {JA[4]}];#Sch name = JA7 +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports {JA[5]}];#Sch name = JA8 +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports {JA[6]}];#Sch name = JA9 +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports {JA[7]}];#Sch name = JA10 + +##Pmod Header JB +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports {JB[0]}];#Sch name = JB1 +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports {JB[1]}];#Sch name = JB2 +#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports {JB[2]}];#Sch name = JB3 +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports {JB[3]}];#Sch name = JB4 +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports {JB[4]}];#Sch name = JB7 +#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports {JB[5]}];#Sch name = JB8 +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports {JB[6]}];#Sch name = JB9 +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports {JB[7]}];#Sch name = JB10 + +##Pmod Header JC +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports {JC[0]}];#Sch name = JC1 +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports {JC[1]}];#Sch name = JC2 +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports {JC[2]}];#Sch name = JC3 +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports {JC[3]}];#Sch name = JC4 +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports {JC[4]}];#Sch name = JC7 +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports {JC[5]}];#Sch name = JC8 +#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports {JC[6]}];#Sch name = JC9 +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports {JC[7]}];#Sch name = JC10 + +##Pmod Header JXADC +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[0]}];#Sch name = XA1_P +#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[1]}];#Sch name = XA2_P +#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[2]}];#Sch name = XA3_P +#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[3]}];#Sch name = XA4_P +#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[4]}];#Sch name = XA1_N +#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[5]}];#Sch name = XA2_N +#set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[6]}];#Sch name = XA3_N +#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[7]}];#Sch name = XA4_N + + +##VGA Connector +set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[0]}] +set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[1]}] +set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[2]}] +set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[3]}] +set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[0]}] +set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[1]}] +set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[2]}] +set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[3]}] +set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[0]}] +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[1]}] +set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[2]}] +set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[3]}] +set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports Hsync] +set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports Vsync] + + +##USB-RS232 Interface +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports RsRx] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports RsTx] + + +##USB HID (PS/2) +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Clk] +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Data] + + +##Quad SPI Flash +##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the +##STARTUPE2 primitive. +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[0]}] +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[1]}] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[2]}] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[3]}] +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports QspiCSn] + + +## Configuration options, can be used for all designs +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] + +## SPI configuration mode options for QSPI boot, can be used for all designs +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] \ No newline at end of file diff --git a/TP_VGA/TP_VGA.cache/ip/2019.1/4e61f1d817877072/4e61f1d817877072.xci b/TP_VGA/TP_VGA.cache/ip/2019.1/4e61f1d817877072/4e61f1d817877072.xci new file mode 100755 index 0000000..a0d8e3a --- /dev/null +++ b/TP_VGA/TP_VGA.cache/ip/2019.1/4e61f1d817877072/4e61f1d817877072.xci @@ -0,0 +1,296 @@ + + + xilinx.com + ipcache + 4e61f1d817877072 + 0 + + + clk_wiz_0 + + + 100000000 + 100000000 + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 0.010 + 100.0 + 0.010 + BUFG + 254.866 + false + 297.890 + 50.000 + 65.000 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clk_wiz_0 + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 50.375 + 0.000 + false + 10.000 + 10.000 + 15.500 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 5 + None + 0.010 + 0.010 + false + 1 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 100.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + false + false + false + false + true + false + false + false + false + false + artix7 + digilentinc.com:basys3:part0:1.2 + xc7a35t + cpg236 + VHDL + + -1 + + + TRUE + TRUE + 2e0224e4 + 4e61f1d817877072 + clk_wiz_0 + 556c84fe + 29 + IP_Unknown + 3 + TRUE + . + + . + 2019.1 + GLOBAL + + + + diff --git a/TP_VGA/TP_VGA.cache/ip/2019.1/4e61f1d817877072/clk_wiz_0.dcp b/TP_VGA/TP_VGA.cache/ip/2019.1/4e61f1d817877072/clk_wiz_0.dcp new file mode 100755 index 0000000..1eacb91 Binary files /dev/null and b/TP_VGA/TP_VGA.cache/ip/2019.1/4e61f1d817877072/clk_wiz_0.dcp differ diff --git a/TP_VGA/TP_VGA.cache/ip/2019.1/4e61f1d817877072/clk_wiz_0_sim_netlist.v b/TP_VGA/TP_VGA.cache/ip/2019.1/4e61f1d817877072/clk_wiz_0_sim_netlist.v new file mode 100755 index 0000000..4b3336a --- /dev/null +++ b/TP_VGA/TP_VGA.cache/ip/2019.1/4e61f1d817877072/clk_wiz_0_sim_netlist.v @@ -0,0 +1,231 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed Oct 4 16:31:39 2023 +// Host : WIN10-TP running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.v +// Design : clk_wiz_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7a35tcpg236-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (clk_out1, + clk_in1); + output clk_out1; + input clk_in1; + + (* IBUF_LOW_PWR *) wire clk_in1; + wire clk_out1; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz inst + (.clk_in1(clk_in1), + .clk_out1(clk_out1)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz + (clk_out1, + clk_in1); + output clk_out1; + input clk_in1; + + wire clk_in1; + wire clk_in1_clk_wiz_0; + wire clk_out1; + wire clk_out1_clk_wiz_0; + wire clkfbout_buf_clk_wiz_0; + wire clkfbout_clk_wiz_0; + wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED; + wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED; + wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED; + wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED; + wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkf_buf + (.I(clkfbout_clk_wiz_0), + .O(clkfbout_buf_clk_wiz_0)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF #( + .IOSTANDARD("DEFAULT")) + clkin1_ibufg + (.I(clk_in1), + .O(clk_in1_clk_wiz_0)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkout1_buf + (.I(clk_out1_clk_wiz_0), + .O(clk_out1)); + (* BOX_TYPE = "PRIMITIVE" *) + MMCME2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT_F(50.375000), + .CLKFBOUT_PHASE(0.000000), + .CLKFBOUT_USE_FINE_PS("FALSE"), + .CLKIN1_PERIOD(10.000000), + .CLKIN2_PERIOD(0.000000), + .CLKOUT0_DIVIDE_F(15.500000), + .CLKOUT0_DUTY_CYCLE(0.500000), + .CLKOUT0_PHASE(0.000000), + .CLKOUT0_USE_FINE_PS("FALSE"), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.500000), + .CLKOUT1_PHASE(0.000000), + .CLKOUT1_USE_FINE_PS("FALSE"), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.500000), + .CLKOUT2_PHASE(0.000000), + .CLKOUT2_USE_FINE_PS("FALSE"), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.500000), + .CLKOUT3_PHASE(0.000000), + .CLKOUT3_USE_FINE_PS("FALSE"), + .CLKOUT4_CASCADE("FALSE"), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.500000), + .CLKOUT4_PHASE(0.000000), + .CLKOUT4_USE_FINE_PS("FALSE"), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.500000), + .CLKOUT5_PHASE(0.000000), + .CLKOUT5_USE_FINE_PS("FALSE"), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.500000), + .CLKOUT6_PHASE(0.000000), + .CLKOUT6_USE_FINE_PS("FALSE"), + .COMPENSATION("ZHOLD"), + .DIVCLK_DIVIDE(5), + .IS_CLKINSEL_INVERTED(1'b0), + .IS_PSEN_INVERTED(1'b0), + .IS_PSINCDEC_INVERTED(1'b0), + .IS_PWRDWN_INVERTED(1'b0), + .IS_RST_INVERTED(1'b0), + .REF_JITTER1(0.010000), + .REF_JITTER2(0.010000), + .SS_EN("FALSE"), + .SS_MODE("CENTER_HIGH"), + .SS_MOD_PERIOD(10000), + .STARTUP_WAIT("FALSE")) + mmcm_adv_inst + (.CLKFBIN(clkfbout_buf_clk_wiz_0), + .CLKFBOUT(clkfbout_clk_wiz_0), + .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED), + .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED), + .CLKIN1(clk_in1_clk_wiz_0), + .CLKIN2(1'b0), + .CLKINSEL(1'b1), + .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), + .CLKOUT0(clk_out1_clk_wiz_0), + .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), + .CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED), + .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), + .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED), + .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), + .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED), + .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED), + .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED), + .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED), + .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED), + .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DCLK(1'b0), + .DEN(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]), + .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED), + .DWE(1'b0), + .LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED), + .PSCLK(1'b0), + .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .PWRDWN(1'b0), + .RST(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/TP_VGA/TP_VGA.cache/ip/2019.1/4e61f1d817877072/clk_wiz_0_sim_netlist.vhdl b/TP_VGA/TP_VGA.cache/ip/2019.1/4e61f1d817877072/clk_wiz_0_sim_netlist.vhdl new file mode 100755 index 0000000..187aa2c --- /dev/null +++ b/TP_VGA/TP_VGA.cache/ip/2019.1/4e61f1d817877072/clk_wiz_0_sim_netlist.vhdl @@ -0,0 +1,183 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed Oct 4 16:31:39 2023 +-- Host : WIN10-TP running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.vhdl +-- Design : clk_wiz_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7a35tcpg236-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz is + port ( + clk_out1 : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz is + signal clk_in1_clk_wiz_0 : STD_LOGIC; + signal clk_out1_clk_wiz_0 : STD_LOGIC; + signal clkfbout_buf_clk_wiz_0 : STD_LOGIC; + signal clkfbout_clk_wiz_0 : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; + attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; +begin +clkf_buf: unisim.vcomponents.BUFG + port map ( + I => clkfbout_clk_wiz_0, + O => clkfbout_buf_clk_wiz_0 + ); +clkin1_ibufg: unisim.vcomponents.IBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => clk_in1, + O => clk_in1_clk_wiz_0 + ); +clkout1_buf: unisim.vcomponents.BUFG + port map ( + I => clk_out1_clk_wiz_0, + O => clk_out1 + ); +mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV + generic map( + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT_F => 50.375000, + CLKFBOUT_PHASE => 0.000000, + CLKFBOUT_USE_FINE_PS => false, + CLKIN1_PERIOD => 10.000000, + CLKIN2_PERIOD => 0.000000, + CLKOUT0_DIVIDE_F => 15.500000, + CLKOUT0_DUTY_CYCLE => 0.500000, + CLKOUT0_PHASE => 0.000000, + CLKOUT0_USE_FINE_PS => false, + CLKOUT1_DIVIDE => 1, + CLKOUT1_DUTY_CYCLE => 0.500000, + CLKOUT1_PHASE => 0.000000, + CLKOUT1_USE_FINE_PS => false, + CLKOUT2_DIVIDE => 1, + CLKOUT2_DUTY_CYCLE => 0.500000, + CLKOUT2_PHASE => 0.000000, + CLKOUT2_USE_FINE_PS => false, + CLKOUT3_DIVIDE => 1, + CLKOUT3_DUTY_CYCLE => 0.500000, + CLKOUT3_PHASE => 0.000000, + CLKOUT3_USE_FINE_PS => false, + CLKOUT4_CASCADE => false, + CLKOUT4_DIVIDE => 1, + CLKOUT4_DUTY_CYCLE => 0.500000, + CLKOUT4_PHASE => 0.000000, + CLKOUT4_USE_FINE_PS => false, + CLKOUT5_DIVIDE => 1, + CLKOUT5_DUTY_CYCLE => 0.500000, + CLKOUT5_PHASE => 0.000000, + CLKOUT5_USE_FINE_PS => false, + CLKOUT6_DIVIDE => 1, + CLKOUT6_DUTY_CYCLE => 0.500000, + CLKOUT6_PHASE => 0.000000, + CLKOUT6_USE_FINE_PS => false, + COMPENSATION => "ZHOLD", + DIVCLK_DIVIDE => 5, + IS_CLKINSEL_INVERTED => '0', + IS_PSEN_INVERTED => '0', + IS_PSINCDEC_INVERTED => '0', + IS_PWRDWN_INVERTED => '0', + IS_RST_INVERTED => '0', + REF_JITTER1 => 0.010000, + REF_JITTER2 => 0.010000, + SS_EN => "FALSE", + SS_MODE => "CENTER_HIGH", + SS_MOD_PERIOD => 10000, + STARTUP_WAIT => false + ) + port map ( + CLKFBIN => clkfbout_buf_clk_wiz_0, + CLKFBOUT => clkfbout_clk_wiz_0, + CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, + CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, + CLKIN1 => clk_in1_clk_wiz_0, + CLKIN2 => '0', + CLKINSEL => '1', + CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, + CLKOUT0 => clk_out1_clk_wiz_0, + CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, + CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, + CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, + CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, + CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, + CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, + CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, + CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, + CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, + CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, + DADDR(6 downto 0) => B"0000000", + DCLK => '0', + DEN => '0', + DI(15 downto 0) => B"0000000000000000", + DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), + DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, + DWE => '0', + LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED, + PSCLK => '0', + PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, + PSEN => '0', + PSINCDEC => '0', + PWRDWN => '0', + RST => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + port ( + clk_out1 : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +begin +inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz + port map ( + clk_in1 => clk_in1, + clk_out1 => clk_out1 + ); +end STRUCTURE; diff --git a/TP_VGA/TP_VGA.cache/ip/2019.1/4e61f1d817877072/clk_wiz_0_stub.v b/TP_VGA/TP_VGA.cache/ip/2019.1/4e61f1d817877072/clk_wiz_0_stub.v new file mode 100755 index 0000000..08660a3 --- /dev/null +++ b/TP_VGA/TP_VGA.cache/ip/2019.1/4e61f1d817877072/clk_wiz_0_stub.v @@ -0,0 +1,20 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed Oct 4 16:31:39 2023 +// Host : WIN10-TP running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.v +// Design : clk_wiz_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7a35tcpg236-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, clk_in1) +/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_in1" */; + output clk_out1; + input clk_in1; +endmodule diff --git a/TP_VGA/TP_VGA.cache/ip/2019.1/4e61f1d817877072/clk_wiz_0_stub.vhdl b/TP_VGA/TP_VGA.cache/ip/2019.1/4e61f1d817877072/clk_wiz_0_stub.vhdl new file mode 100755 index 0000000..ef36d86 --- /dev/null +++ b/TP_VGA/TP_VGA.cache/ip/2019.1/4e61f1d817877072/clk_wiz_0_stub.vhdl @@ -0,0 +1,29 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed Oct 4 16:31:39 2023 +-- Host : WIN10-TP running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.vhdl +-- Design : clk_wiz_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7a35tcpg236-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk_out1 : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_in1"; +begin +end; diff --git a/TP_VGA/TP_VGA.cache/wt/gui_handlers.wdf b/TP_VGA/TP_VGA.cache/wt/gui_handlers.wdf new file mode 100755 index 0000000..2d76e14 --- /dev/null +++ b/TP_VGA/TP_VGA.cache/wt/gui_handlers.wdf @@ -0,0 +1,34 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f6f725f6372656174655f636f6e73747261696e745f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6170706c79:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:31:00:00 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b/TP_VGA/TP_VGA.cache/wt/java_command_handlers.wdf new file mode 100755 index 0000000..730393a --- /dev/null +++ b/TP_VGA/TP_VGA.cache/wt/java_command_handlers.wdf @@ -0,0 +1,8 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:34:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f726576696577:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:33:00:00 +eof:473180984 diff --git a/TP_VGA/TP_VGA.cache/wt/project.wpc b/TP_VGA/TP_VGA.cache/wt/project.wpc new file mode 100755 index 0000000..aa1e48b --- /dev/null +++ b/TP_VGA/TP_VGA.cache/wt/project.wpc @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:2 +eof: diff --git a/TP_VGA/TP_VGA.cache/wt/synthesis.wdf b/TP_VGA/TP_VGA.cache/wt/synthesis.wdf new file mode 100755 index 0000000..685fb1b --- /dev/null +++ b/TP_VGA/TP_VGA.cache/wt/synthesis.wdf @@ -0,0 +1,39 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:786337613335746370673233362d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:636c6b5f77697a5f30:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 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+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/TP_VGA/TP_VGA.hw/TP_VGA.lpr b/TP_VGA/TP_VGA.hw/TP_VGA.lpr new file mode 100755 index 0000000..6789539 --- /dev/null +++ b/TP_VGA/TP_VGA.hw/TP_VGA.lpr @@ -0,0 +1,6 @@ + + + + + + diff --git a/TP_VGA/TP_VGA.ip_user_files/README.txt b/TP_VGA/TP_VGA.ip_user_files/README.txt new file mode 100755 index 0000000..9015e04 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/TP_VGA/TP_VGA.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho b/TP_VGA/TP_VGA.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho new file mode 100755 index 0000000..bb4b3b2 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho @@ -0,0 +1,88 @@ + +-- +-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +------------------------------------------------------------------------------ +-- User entered comments +------------------------------------------------------------------------------ +-- None +-- +------------------------------------------------------------------------------ +-- Output Output Phase Duty Cycle Pk-to-Pk Phase +-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +------------------------------------------------------------------------------ +-- clk_out1____65.000______0.000______50.0______254.866____297.890 +-- +------------------------------------------------------------------------------ +-- Input Clock Freq (MHz) Input Jitter (UI) +------------------------------------------------------------------------------ +-- __primary_________100.000____________0.010 + + +-- The following code must appear in the VHDL architecture header: +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component clk_wiz_0 +port + (-- Clock in ports + -- Clock out ports + clk_out1 : out std_logic; + clk_in1 : in std_logic + ); +end component; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : clk_wiz_0 + port map ( + -- Clock out ports + clk_out1 => clk_out1, + -- Clock in ports + clk_in1 => clk_in1 + ); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ diff --git a/TP_VGA/TP_VGA.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v b/TP_VGA/TP_VGA.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v new file mode 100755 index 0000000..626c381 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -0,0 +1,20 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed Oct 4 16:31:39 2023 +// Host : WIN10-TP running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +// Design : clk_wiz_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7a35tcpg236-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module clk_wiz_0(clk_out1, clk_in1) +/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_in1" */; + output clk_out1; + input clk_in1; +endmodule diff --git a/TP_VGA/TP_VGA.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/TP_VGA/TP_VGA.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl new file mode 100755 index 0000000..7166d8c --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -0,0 +1,29 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed Oct 4 16:31:39 2023 +-- Host : WIN10-TP running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub +-- c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +-- Design : clk_wiz_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7a35tcpg236-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_wiz_0 is + Port ( + clk_out1 : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + +end clk_wiz_0; + +architecture stub of clk_wiz_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_in1"; +begin +end; diff --git a/TP_VGA/TP_VGA.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh b/TP_VGA/TP_VGA.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh new file mode 100755 index 0000000..481cd2d --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh @@ -0,0 +1,671 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing +// Date: 7/30/2014 +// Design Name: MMCME2 DRP +// Module Name: mmcme2_drp_func.h +// Version: 1.04 +// Target Devices: 7 Series || MMCM +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 MMCM. +// +// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1011_00, + 10'b0010_1101_00, + 10'b0010_0011_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0100_1111_00, + 10'b0101_1011_00, + 10'b0111_0111_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_1001_00, + 10'b1101_0001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0111_0001_00, + 10'b0111_0001_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0110_0001_00, + 10'b0110_0001_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0100_1010_00, + 10'b0011_1100_00, + 10'b0011_1100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/TP_VGA/TP_VGA.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh b/TP_VGA/TP_VGA.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh new file mode 100755 index 0000000..d34dbe7 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh @@ -0,0 +1,531 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing +// Date: 7/30/2014 +// Design Name: PLLE2 DRP +// Module Name: plle2_drp_func.h +// Version: 2.00 +// Target Devices: 7 Series || PLL +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// Updated for CR663854. +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + +`ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); +`endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end +`ifdef DEBUG + $display("round_frac: %h", round_frac); +`endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + +`ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); +`endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + +`ifdef DEBUG + $display("temp: %h", temp); +`endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1101_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0011_0111_00, + 10'b0011_0111_00, + 10'b0101_1111_00, + 10'b0111_1111_00, + 10'b0111_1011_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_1101_00, + 10'b1111_0111_00, + 10'b1111_1011_00, + 10'b1111_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); +`endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + +`ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); +`endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction diff --git a/TP_VGA/TP_VGA.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh b/TP_VGA/TP_VGA.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh new file mode 100755 index 0000000..811d433 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh @@ -0,0 +1,671 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa +// Date: 7/30/2014 +// Design Name: MMCME2 DRP +// Module Name: mmcme2_drp_func.h +// Version: 1.04 +// Target Devices: UltraScale Architecture || MMCM +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 MMCM. +// +// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_0011_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_1001_11, + 10'b0010_1001_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1011_11, + 10'b0011_1111_11, + 10'b0100_1111_11, + 10'b0100_1111_11, + 10'b0101_1111_11, + 10'b0110_1111_11, + 10'b0111_1111_11, + 10'b0111_1111_11, + 10'b1100_1111_11, + 10'b1101_1111_11, + 10'b1110_1111_11, + 10'b1111_1111_11, + 10'b1111_1111_11, + 10'b1110_0111_11, + 10'b1110_1011_11, + 10'b1111_0111_11, + 10'b1111_1011_11, + 10'b1111_1011_11, + 10'b1110_1101_11, + 10'b1111_1101_11, + 10'b1111_1101_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/TP_VGA/TP_VGA.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh b/TP_VGA/TP_VGA.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh new file mode 100755 index 0000000..9439f23 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh @@ -0,0 +1,530 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa +// Date: 6/15/2015 +// Design Name: PLLE3 DRP +// Module Name: plle3_drp_func.h +// Version: 1.10 +// Target Devices: UltraScale Architecture +// Tool versions: 2015.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// +// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 +// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 +// PM_Rise bits have been removed for PLLE3 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [759:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, //1 + 40'b00110_00110_1111101000_1111101001_0000000001, //2 + 40'b01000_01000_1111101000_1111101001_0000000001, //3 + 40'b01011_01011_1111101000_1111101001_0000000001, //4 + 40'b01110_01110_1111101000_1111101001_0000000001, //5 + 40'b10001_10001_1111101000_1111101001_0000000001, //6 + 40'b10011_10011_1111101000_1111101001_0000000001, //7 + 40'b10110_10110_1111101000_1111101001_0000000001, //8 + 40'b11001_11001_1111101000_1111101001_0000000001, //9 + 40'b11100_11100_1111101000_1111101001_0000000001, //10 + 40'b11111_11111_1110000100_1111101001_0000000001, //11 + 40'b11111_11111_1100111001_1111101001_0000000001, //12 + 40'b11111_11111_1011101110_1111101001_0000000001, //13 + 40'b11111_11111_1010111100_1111101001_0000000001, //14 + 40'b11111_11111_1010001010_1111101001_0000000001, //15 + 40'b11111_11111_1001110001_1111101001_0000000001, //16 + 40'b11111_11111_1000111111_1111101001_0000000001, //17 + 40'b11111_11111_1000100110_1111101001_0000000001, //18 + 40'b11111_11111_1000001101_1111101001_0000000001 //19 + + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide // Max divide is 19 + ); + + reg [639:0] lookup; + reg [9:0] lookup_entry; + + begin + + lookup = { + // CP_RES_LFHF + 10'b0010_1111_01, //1 + 10'b0010_0011_11, //2 + 10'b0011_0011_11, //3 + 10'b0010_0001_11, //4 + 10'b0010_0110_11, //5 + 10'b0010_1010_11, //6 + 10'b0010_1010_11, //7 + 10'b0011_0110_11, //8 + 10'b0010_1100_11, //9 + 10'b0010_1100_11, //10 + 10'b0010_1100_11, //11 + 10'b0010_0010_11, //12 + 10'b0011_1100_11, //13 + 10'b0011_1100_11, //14 + 10'b0011_1100_11, //15 + 10'b0011_1100_11, //16 + 10'b0011_0010_11, //17 + 10'b0011_0010_11, //18 + 10'b0011_0010_11 //19 + }; + + mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10]; + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function set the CLKOUTPHY divide settings to match +// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then +// the CLKOUTPHY will be set to 2'b00 since the VCO is internally +// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10 +function [9:0] mmcm_pll_clkoutphy_calc + ( + input [8*9:0] CLKOUTPHY_MODE + ); + + if(CLKOUTPHY_MODE == "VCO_X2") begin + mmcm_pll_clkoutphy_calc= 2'b00; + end else if(CLKOUTPHY_MODE == "VCO") begin + mmcm_pll_clkoutphy_calc= 2'b01; + end else if(CLKOUTPHY_MODE == "CLKIN") begin + mmcm_pll_clkoutphy_calc= 2'b11; + end else begin // Assume "VCO_HALF" + mmcm_pll_clkoutphy_calc= 2'b10; + end + +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_pll_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_pll_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits +// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); + `endif + + end +endfunction + + diff --git a/TP_VGA/TP_VGA.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh b/TP_VGA/TP_VGA.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh new file mode 100755 index 0000000..ebf87be --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh @@ -0,0 +1,861 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa. Updated by Ralf Krueger +// Date: 7/30/2014 +// Design Name: MMCME4 DRP +// Module Name: mmcme4_drp_func.h +// Version: 1.31 +// Target Devices: UltraScale Plus Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for UltraScal+ MMCM. +// +// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function +// 2/28/17 - Updated for Ultrascale Plus +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2017 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages during elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_phase-divide:%d,phase:%d", divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [7:0] divide // Max M divide is 128 in UltrascalePlus + ); + + reg [5119:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed) + 40'b00110_00110_1111101000_1111101001_0000000001, // M=2 + 40'b01000_01000_1111101000_1111101001_0000000001, // M=3 + 40'b01011_01011_1111101000_1111101001_0000000001, // M=4 + 40'b01110_01110_1111101000_1111101001_0000000001, // M=5 + 40'b10001_10001_1111101000_1111101001_0000000001, // M=6 + 40'b10011_10011_1111101000_1111101001_0000000001, // M=7 + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, // M=127 + 40'b11111_11111_0011111010_1111101001_0000000001 // M=128 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus + input [8*9:0] BANDWIDTH + ); + + reg [1279:0] lookup_low; + reg [1279:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0011_1111_11, // M=1 - not legal + 10'b0011_1111_11, // M=2 + 10'b0011_1101_11, // M=3 + 10'b0011_0101_11, // M=4 + 10'b0011_1001_11, // M=5 + 10'b0011_1110_11, // M=6 + 10'b0011_1110_11, // M=7 + 10'b0011_0001_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0100_0110_11, + 10'b0011_1100_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, // M=127 + 10'b1101_1000_11 // M=128 +}; + + lookup_high = { + // CP_RES_LFHF + 10'b0111_1111_11, // M=1 - not legal + 10'b0111_1111_11, // M=2 + 10'b1110_1111_11, // M=3 + 10'b1111_1111_11, // M=4 + 10'b1111_1011_11, // M=5 + 10'b1111_1101_11, // M=6 + 10'b1111_0011_11, // M=7 + 10'b1110_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1110_0110_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11 // M=128 +}; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/TP_VGA/TP_VGA.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh b/TP_VGA/TP_VGA.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh new file mode 100755 index 0000000..1d2dc69 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh @@ -0,0 +1,536 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+ +// Date: 6/15/2015 +// Design Name: PLLE4 DRP +// Module Name: plle4_drp_func.h +// Version: 2.0 +// Target Devices: UltraScale+ Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// +// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 +// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 +// M_Rise bits have been removed for PLLE3 +// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for +// Ultrascale+ and for max M of 21 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2017 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); +`endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 21 + ); + + reg [839:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+ + 40'b00110_00110_1111101000_1111101001_0000000001, //2 + 40'b01000_01000_1111101000_1111101001_0000000001, //3 + 40'b01011_01011_1111101000_1111101001_0000000001, //4 + 40'b01110_01110_1111101000_1111101001_0000000001, //5 + 40'b10001_10001_1111101000_1111101001_0000000001, //6 + 40'b10011_10011_1111101000_1111101001_0000000001, //7 + 40'b10110_10110_1111101000_1111101001_0000000001, //8 + 40'b11001_11001_1111101000_1111101001_0000000001, //9 + 40'b11100_11100_1111101000_1111101001_0000000001, //10 + 40'b11111_11111_1110000100_1111101001_0000000001, //11 + 40'b11111_11111_1100111001_1111101001_0000000001, //12 + 40'b11111_11111_1011101110_1111101001_0000000001, //13 + 40'b11111_11111_1010111100_1111101001_0000000001, //14 + 40'b11111_11111_1010001010_1111101001_0000000001, //15 + 40'b11111_11111_1001110001_1111101001_0000000001, //16 + 40'b11111_11111_1000111111_1111101001_0000000001, //17 + 40'b11111_11111_1000100110_1111101001_0000000001, //18 + 40'b11111_11111_1000001101_1111101001_0000000001, //19 + 40'b11111_11111_0111110100_1111101001_0000000001, //20 + 40'b11111_11111_0111011011_1111101001_0000000001 //21 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide // Max divide is 21 + ); + + reg [209:0] lookup; + reg [9:0] lookup_entry; + + begin + + lookup = { + // CP_RES_LFHF + 10'b0011_0111_11, //1 not legal in Ultrascale+ + 10'b0011_0111_11, //2 + 10'b0011_0011_11, //3 + 10'b0011_1001_11, //4 + 10'b0011_0001_11, //5 + 10'b0100_1110_11, //6 + 10'b0011_0110_11, //7 + 10'b0011_1010_11, //8 + 10'b0111_1001_11, //9 + 10'b0111_1001_11, //10 + 10'b0101_0110_11, //11 + 10'b1100_0101_11, //12 + 10'b0101_1010_11, //13 + 10'b0110_0110_11, //14 + 10'b0110_1010_11, //15 + 10'b0111_0110_11, //16 + 10'b1111_0101_11, //17 + 10'b1100_0110_11, //18 + 10'b1110_0001_11, //19 + 10'b1101_0110_11, //20 + 10'b1111_0001_11 //21 + }; + + mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10]; + + `ifdef DEBUG + $display("filter_lookup: %b", pll_filter_lookup); + `endif + end +endfunction + +// This function set the CLKOUTPHY divide settings to match +// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then +// the CLKOUTPHY will be set to 2'b00 since the VCO is internally +// doubled and 2'b00 will represent divide by 1. Similarly "VCO" +// will need to divide the doubled clock VCO clock frequency by +// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will +// need to divide the doubled VCO by 4, therefore 2'b10 +function [9:0] mmcm_pll_clkoutphy_calc + ( + input [8*9:0] CLKOUTPHY_MODE + ); + + if(CLKOUTPHY_MODE == "VCO_X2") begin + mmcm_pll_clkoutphy_calc= 2'b00; + end else if(CLKOUTPHY_MODE == "VCO") begin + mmcm_pll_clkoutphy_calc= 2'b01; + end else if(CLKOUTPHY_MODE == "CLKIN") begin + mmcm_pll_clkoutphy_calc= 2'b11; + end else begin // Assume "VCO_HALF" + mmcm_pll_clkoutphy_calc= 2'b10; + end + +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_pll_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_pll_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/README.txt b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/README.txt new file mode 100755 index 0000000..22c1387 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt new file mode 100755 index 0000000..28f4cbb --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Oct 04 16:31:05 +0200 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh new file mode 100755 index 0000000..1d846e1 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Oct 04 16:31:05 +0200 2023 +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2019.1 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.cache/compile_simlib/activehdl" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.udo b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.udo new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.udo diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do new file mode 100755 index 0000000..20f1608 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ipstatic" \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" \ +"../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ +"../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt new file mode 100755 index 0000000..5060d09 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v new file mode 100755 index 0000000..be64233 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do new file mode 100755 index 0000000..02fe1b9 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+clk_wiz_0 -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {clk_wiz_0.udo} + +run -all + +endsim + +quit -force diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/wave.do b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/wave.do new file mode 100755 index 0000000..d682cd4 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/ies/README.txt b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/ies/README.txt new file mode 100755 index 0000000..7dea85f --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Oct 04 16:31:05 +0200 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/ies/clk_wiz_0.sh b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/ies/clk_wiz_0.sh new file mode 100755 index 0000000..da334a6 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/ies/clk_wiz_0.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Oct 04 16:31:05 +0200 2023 +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2019.1 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.clk_wiz_0 \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../ipstatic" \ + +incdir+"../../../ipstatic" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/ies/file_info.txt b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/ies/file_info.txt new file mode 100755 index 0000000..41e3dc7 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/ies/glbl.v b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/ies/glbl.v new file mode 100755 index 0000000..be64233 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/ies/run.f b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/ies/run.f new file mode 100755 index 0000000..ef4b617 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +-endlib +-makelib ies_lib/xpm \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ + "../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt new file mode 100755 index 0000000..28f4cbb --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Oct 04 16:31:05 +0200 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh new file mode 100755 index 0000000..b4264b4 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Oct 04 16:31:05 +0200 2023 +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2019.1 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.cache/compile_simlib/modelsim" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.udo b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.udo new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.udo diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do new file mode 100755 index 0000000..1551744 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do @@ -0,0 +1,22 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/xpm + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap xpm modelsim_lib/msim/xpm + +vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ipstatic" \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -64 -93 \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic" \ +"../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ +"../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt new file mode 100755 index 0000000..5060d09 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v new file mode 100755 index 0000000..be64233 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do new file mode 100755 index 0000000..7c8b392 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {clk_wiz_0.udo} + +run -all + +quit -force diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do new file mode 100755 index 0000000..d682cd4 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt new file mode 100755 index 0000000..28f4cbb --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Oct 04 16:31:05 +0200 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh new file mode 100755 index 0000000..0913415 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Oct 04 16:31:05 +0200 2023 +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2019.1 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.udo b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.udo new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.udo diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do new file mode 100755 index 0000000..11ccae3 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ipstatic" \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -64 -93 \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic" \ +"../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ +"../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do new file mode 100755 index 0000000..3301455 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -o clk_wiz_0_opt diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt new file mode 100755 index 0000000..5060d09 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v new file mode 100755 index 0000000..be64233 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do new file mode 100755 index 0000000..dc877a0 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib clk_wiz_0_opt + +do {wave.do} + +view wave +view structure +view signals + +do {clk_wiz_0.udo} + +run -all + +quit -force diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do new file mode 100755 index 0000000..d682cd4 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt new file mode 100755 index 0000000..28f4cbb --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Oct 04 16:31:05 +0200 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh new file mode 100755 index 0000000..18ef9b8 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Oct 04 16:31:05 +0200 2023 +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2019.1 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.udo b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.udo new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.udo diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do new file mode 100755 index 0000000..bf14e65 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ipstatic" \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 \ +"C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" \ +"../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ +"../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt new file mode 100755 index 0000000..5060d09 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v new file mode 100755 index 0000000..be64233 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do new file mode 100755 index 0000000..02fe1b9 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+clk_wiz_0 -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {clk_wiz_0.udo} + +run -all + +endsim + +quit -force diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/wave.do b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/wave.do new file mode 100755 index 0000000..d682cd4 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt new file mode 100755 index 0000000..28f4cbb --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Oct 04 16:31:05 +0200 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh new file mode 100755 index 0000000..7f3bbd7 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh @@ -0,0 +1,229 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Oct 04 16:31:05 +0200 2023 +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2019.1 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ipstatic" \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic" \ + "$ref_dir/../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ + "$ref_dir/../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -o clk_wiz_0_simv +} + +# RUN_STEP: +simulate() +{ + ./clk_wiz_0_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key clk_wiz_0_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc clk_wiz_0_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt new file mode 100755 index 0000000..41e3dc7 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v new file mode 100755 index 0000000..be64233 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do new file mode 100755 index 0000000..a06099a --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt new file mode 100755 index 0000000..7dea85f --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Oct 04 16:31:05 +0200 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh new file mode 100755 index 0000000..1023c43 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Oct 04 16:31:05 +0200 2023 +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'clk_wiz_0.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2019.1 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.clk_wiz_0 \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../ipstatic" \ + +incdir+"../../../ipstatic" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt new file mode 100755 index 0000000..41e3dc7 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v new file mode 100755 index 0000000..be64233 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xcelium/run.f b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xcelium/run.f new file mode 100755 index 0000000..df1ca10 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "C:/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ + "../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt new file mode 100755 index 0000000..28f4cbb --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Oct 04 16:31:05 +0200 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./clk_wiz_0.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './clk_wiz_0.sh' script. + +./clk_wiz_0.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./clk_wiz_0.sh -noclean_files + +For more information on the script, please type './clk_wiz_0.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh new file mode 100755 index 0000000..778f848 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1 (64-bit) +# +# Filename : clk_wiz_0.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Oct 04 16:31:05 +0200 2023 +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: clk_wiz_0.sh [-help] +# usage: clk_wiz_0.sh [-lib_map_path] +# usage: clk_wiz_0.sh [-noclean_files] +# usage: clk_wiz_0.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=C:/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2019.1 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot clk_wiz_0 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim clk_wiz_0 -key {Behavioral:sim_1:Functional:clk_wiz_0} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="C:/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=(xil_defaultlib) + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb clk_wiz_0.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: clk_wiz_0.sh [-help]\n\ +Usage: clk_wiz_0.sh [-lib_map_path]\n\ +Usage: clk_wiz_0.sh [-reset_run]\n\ +Usage: clk_wiz_0.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl new file mode 100755 index 0000000..05f1b4f --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/elab.opt b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/elab.opt new file mode 100755 index 0000000..12b1280 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/elab.opt @@ -0,0 +1 @@ +--relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot clk_wiz_0 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -log elaborate.log diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt new file mode 100755 index 0000000..8ac58ed --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt @@ -0,0 +1,3 @@ +clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +clk_wiz_0.v,verilog,xil_defaultlib,../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v new file mode 100755 index 0000000..be64233 --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj new file mode 100755 index 0000000..665039b --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj @@ -0,0 +1,7 @@ +verilog xil_defaultlib --include "../../../ipstatic" \ +"../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \ +"../../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/xsim.ini b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/xsim.ini new file mode 100755 index 0000000..5f84e1d --- /dev/null +++ b/TP_VGA/TP_VGA.ip_user_files/sim_scripts/clk_wiz_0/xsim/xsim.ini @@ -0,0 +1,431 @@ +std=$RDI_DATADIR/xsim/vhdl/std +ieee=$RDI_DATADIR/xsim/vhdl/ieee +ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed +vl=$RDI_DATADIR/xsim/vhdl/vl +synopsys=$RDI_DATADIR/xsim/vhdl/synopsys +secureip=$RDI_DATADIR/xsim/verilog/secureip +unisim=$RDI_DATADIR/xsim/vhdl/unisim +unimacro=$RDI_DATADIR/xsim/vhdl/unimacro +unifast=$RDI_DATADIR/xsim/vhdl/unifast +unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver +unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver +unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver +simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver +system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6 +bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 +g709_rs_decoder_v2_2_8=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_8 +xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0 +iomodule_v3_1_4=$RDI_DATADIR/xsim/ip/iomodule_v3_1_4 +ieee802d3_50g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_11 +l_ethernet_v2_4_1=$RDI_DATADIR/xsim/ip/l_ethernet_v2_4_1 +common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0 +lte_fft_v2_1_0=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_0 +convolution_v9_0_14=$RDI_DATADIR/xsim/ip/convolution_v9_0_14 +gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4 +v_cfa_v7_0_14=$RDI_DATADIR/xsim/ip/v_cfa_v7_0_14 +axi4svideo_bridge_v1_0_10=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_10 +pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11 +v_vscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_13 +xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6 +gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux +zynq_ultra_ps_e_v3_3_0=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_0 +v_cresample_v4_0_14=$RDI_DATADIR/xsim/ip/v_cresample_v4_0_14 +v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9 +v_scenechange_v1_0_1=$RDI_DATADIR/xsim/ip/v_scenechange_v1_0_1 +hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0 +ahblite_axi_bridge_v3_0_14=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_14 +tri_mode_ethernet_mac_v9_0_14=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_14 +blk_mem_gen_v8_4_3=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_3 +noc_mc_ddr4_phy_v1_0_0=$RDI_DATADIR/xsim/ip/noc_mc_ddr4_phy_v1_0_0 +axi_data_fifo_v2_1_18=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_18 +axi_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_5 +compact_gt_v1_0_5=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_5 +axi_gpio_v2_0_21=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_21 +viterbi_v9_1_11=$RDI_DATADIR/xsim/ip/viterbi_v9_1_11 +sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2 +ba317=$RDI_DATADIR/xsim/ip/ba317 +xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4 +fifo_generator_v13_2_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_4 +axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14 +vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0 +axi_emc_v3_0_19=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_19 +floating_point_v7_1_8=$RDI_DATADIR/xsim/ip/floating_point_v7_1_8 +xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6 +vid_phy_controller_v2_2_3=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_3 +common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1 +axi_firewall_v1_0_7=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_7 +util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1 +axis_accelerator_adapter_v2_1_15=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_15 +tmr_comparator_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_2 +sd_fec_v1_0_2=$RDI_DATADIR/xsim/ip/sd_fec_v1_0_2 +tmr_manager_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_4 +tsn_temac_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_4 +usxgmii_v1_0_5=$RDI_DATADIR/xsim/ip/usxgmii_v1_0_5 +lte_dl_channel_encoder_v4_0_0=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_0 +rama_v1_1_1_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_1_lib +ai_noc=$RDI_DATADIR/xsim/ip/ai_noc +lte_3gpp_mimo_decoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_15 +v_uhdsdi_audio_v1_0_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_0 +axi4stream_vip_v1_1_5=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_5 +cmac_usplus_v2_4_5=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_4_5 +etrnic_v1_1_2=$RDI_DATADIR/xsim/ip/etrnic_v1_1_2 +floating_point_v7_0_16=$RDI_DATADIR/xsim/ip/floating_point_v7_0_16 +axi_dma_v7_1_20=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_20 +jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi +axi_traffic_gen_v3_0_5=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_5 +emb_mem_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_1 +axi_amm_bridge_v1_0_9=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_9 +axi_datamover_v5_1_21=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_21 +v_axi4s_vid_out_v4_0_10=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_10 +jesd204_v7_2_6=$RDI_DATADIR/xsim/ip/jesd204_v7_2_6 +v_letterbox_v1_0_13=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_13 +cmac_v2_5_0=$RDI_DATADIR/xsim/ip/cmac_v2_5_0 +interlaken_v2_4_3=$RDI_DATADIR/xsim/ip/interlaken_v2_4_3 +uhdsdi_gt_v2_0_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_0 +axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7 +rst_vip_v1_0_3=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_3 +audio_formatter_v1_0_1=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_1 +lte_3gpp_channel_estimator_v2_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_16 +v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13 +g709_fec_v2_3_5=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_5 +xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6 +v_mix_v3_0_3=$RDI_DATADIR/xsim/ip/v_mix_v3_0_3 +in_system_ibert_v1_0_9=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_9 +axis_broadcaster_v1_1_18=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_18 +axis_combiner_v1_1_17=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_17 +axi_apb_bridge_v3_0_15=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_15 +displayport_v9_0_1=$RDI_DATADIR/xsim/ip/displayport_v9_0_1 +clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2 +hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1 +axi_register_slice_v2_1_19=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_19 +vid_phy_controller_v2_1_5=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_5 +picxo=$RDI_DATADIR/xsim/ip/picxo +usxgmii_v1_1_0=$RDI_DATADIR/xsim/ip/usxgmii_v1_1_0 +v_vcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_13 +bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0 +prc_v1_3_2=$RDI_DATADIR/xsim/ip/prc_v1_3_2 +axi_usb2_device_v5_0_20=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_20 +lte_3gpp_mimo_encoder_v4_0_14=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_14 +xdma_v4_1_3=$RDI_DATADIR/xsim/ip/xdma_v4_1_3 +qdma_v3_0_1=$RDI_DATADIR/xsim/ip/qdma_v3_0_1 +axis_vio_v1_0_0=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_0 +c_counter_binary_v12_0_13=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_13 +noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0 +xbip_dsp48_macro_v3_0_17=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_17 +c_accum_v12_0_13=$RDI_DATADIR/xsim/ip/c_accum_v12_0_13 +xbip_multadd_v3_0_14=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_14 +axi_uartlite_v2_0_23=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_23 +noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0 +axi_intc_v4_1_13=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_13 +i2s_transmitter_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_3 +pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8 +mutex_v2_1_10=$RDI_DATADIR/xsim/ip/mutex_v2_1_10 +c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6 +sid_v8_0_14=$RDI_DATADIR/xsim/ip/sid_v8_0_14 +fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6 +quadsgmii_v3_4_6=$RDI_DATADIR/xsim/ip/quadsgmii_v3_4_6 +microblaze_v11_0_1=$RDI_DATADIR/xsim/ip/microblaze_v11_0_1 +lib_bmg_v1_0_12=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_12 +dds_compiler_v6_0_18=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_18 +me_pl_v1_0=$RDI_DATADIR/xsim/ip/me_pl_v1_0 +gtwizard_ultrascale_v1_7_6=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_6 +axis_clock_converter_v1_1_20=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_20 +nvmeha_v1_0_0=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_0 +tmr_inject_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_3 +axi_mcdma_v1_1_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_0 +axi_hwicap_v3_0_23=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_23 +ieee802d3_rs_fec_v2_0_4=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_4 +v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 +v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 +canfd_v2_0_1=$RDI_DATADIR/xsim/ip/canfd_v2_0_1 +gig_ethernet_pcs_pma_v16_1_6=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_6 +lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 +ibert_lib_v1_0_6=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_6 +high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1 +xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6 +fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1 +tmr_voter_v1_0_2=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_2 +hdmi_gt_controller_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_0 +axi_traffic_gen_v2_0_20=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_20 +multi_channel_25g_rs_fec_v1_0_2=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_2 +v_smpte_uhdsdi_v1_0_7=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_7 +xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6 +fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10 +ieee802d3_rs_fec_v1_0_15=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_15 +axis_subset_converter_v1_1_19=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_19 +noc_nmu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_v1_0_0 +duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15 +dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13 +l_ethernet_v2_5_0=$RDI_DATADIR/xsim/ip/l_ethernet_v2_5_0 +mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0 +axi_chip2chip_v5_0_5=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_5 +cpri_v8_10_0=$RDI_DATADIR/xsim/ip/cpri_v8_10_0 +sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1 +mrmac_v1_0_0=$RDI_DATADIR/xsim/ip/mrmac_v1_0_0 +ethernet_1_10_25g_v2_3_0=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_3_0 +ieee802d3_25g_rs_fec_v1_0_12=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_12 +sem_ultra_v3_1_11=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_11 +v_tpg_v8_0_1=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_1 +axi_tft_v2_0_22=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_22 +ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13 +ieee802d3_200g_rs_fec_v1_0_6=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_6 +switch_core_top_v1_0_7=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_7 +v_hcresampler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_13 +emb_fifo_gen_v1_0_1=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_1 +hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 +axis_data_fifo_v2_0_1=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_1 +hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0 +rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1 +displayport_v8_1_1=$RDI_DATADIR/xsim/ip/displayport_v8_1_1 +axi_mmu_v2_1_17=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_17 +proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13 +pc_cfr_v6_3_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_0 +v_osd_v6_0_16=$RDI_DATADIR/xsim/ip/v_osd_v6_0_16 +pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12 +xfft_v9_0_17=$RDI_DATADIR/xsim/ip/xfft_v9_0_17 +axi_cdma_v4_1_19=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_19 +audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 +lib_fifo_v1_0_13=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_13 +v_enhance_v8_0_15=$RDI_DATADIR/xsim/ip/v_enhance_v8_0_15 +axi_clock_converter_v2_1_18=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_18 +xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 +emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 +ethernet_1_10_25g_v2_2_2=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_2_2 +axi_mm2s_mapper_v1_1_18=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_18 +xfft_v7_2_9=$RDI_DATADIR/xsim/ip/xfft_v7_2_9 +pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0 +xxv_ethernet_v2_5_2=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_5_2 +v_smpte_sdi_v3_0_8=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_8 +fir_compiler_v7_2_12=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_12 +div_gen_v5_1_15=$RDI_DATADIR/xsim/ip/div_gen_v5_1_15 +mdm_v3_2_16=$RDI_DATADIR/xsim/ip/mdm_v3_2_16 +v_axi4s_remap_v1_0_11=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_11 +xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2 +ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig +remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 +pr_axi_shutdown_manager_v1_0_1=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_1 +axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 +smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 +axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib +axi_dwidth_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_19 +xlconstant_v1_1_6=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_6 +tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 +mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 +v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1 +axi_fifo_mm_s_v4_2_1=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_1 +xxv_ethernet_v3_0_0=$RDI_DATADIR/xsim/ip/xxv_ethernet_v3_0_0 +util_idelay_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_1 +rs_toolbox_v9_0_7=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_7 +v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0 +dsp_macro_v1_0_0=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_0 +pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2 +axi_timer_v2_0_21=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_21 +high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1 +axi_sideband_util_v1_0_3=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_3 +sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2 +gmii_to_rgmii_v4_0_7=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_0_7 +ieee802d3_400g_rs_fec_v1_0_6=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_6 +xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 +high_speed_selectio_wiz_v3_5_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_1 +axi_msg_v1_0_5=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_5 +axi_ahblite_bridge_v3_0_16=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_16 +v_rgb2ycrcb_v7_1_13=$RDI_DATADIR/xsim/ip/v_rgb2ycrcb_v7_1_13 +v_mix_v4_0_0=$RDI_DATADIR/xsim/ip/v_mix_v4_0_0 +axi_ethernetlite_v3_0_17=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_17 +ieee802d3_50g_rs_fec_v2_0_0=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_0 +axi_uart16550_v2_0_21=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_21 +axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0 +vfb_v1_0_13=$RDI_DATADIR/xsim/ip/vfb_v1_0_13 +advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0 +ats_switch_v1_0_2=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_2 +interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 +axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub +c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6 +v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0 +stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0 +rld3_pl_v1_0_1=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_1 +ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 +lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 +axi_epc_v2_0_22=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_22 +g709_rs_encoder_v2_2_6=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_6 +blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 +fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 +axi_vdma_v6_3_7=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_7 +axis_data_fifo_v1_1_20=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_20 +xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip +axi_ethernet_buffer_v2_0_20=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_20 +rs_encoder_v9_0_15=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_15 +axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 +ta_dma_v1_0_3=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_3 +tcc_encoder_3gpp_v5_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_15 +axi_perf_mon_v5_0_21=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_21 +noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0 +sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1 +lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 +v_csc_v1_0_13=$RDI_DATADIR/xsim/ip/v_csc_v1_0_13 +shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0 +lte_fft_v2_0_18=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_18 +gtwizard_ultrascale_v1_6_11=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_11 +amm_axi_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_5 +cmac_usplus_v2_6_0=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_6_0 +mii_to_rmii_v2_0_21=$RDI_DATADIR/xsim/ip/mii_to_rmii_v2_0_21 +videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 +audio_clock_recovery_v1_0=$RDI_DATADIR/xsim/ip/audio_clock_recovery_v1_0 +cmac_v2_4_1=$RDI_DATADIR/xsim/ip/cmac_v2_4_1 +i2s_receiver_v1_0_3=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_3 +v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 +v_demosaic_v1_0_5=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_5 +remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 +microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 +hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3 +etrnic_v1_0_3=$RDI_DATADIR/xsim/ip/etrnic_v1_0_3 +xfft_v9_1_2=$RDI_DATADIR/xsim/ip/xfft_v9_1_2 +ddr4_pl_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_2 +xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6 +debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1 +axis_protocol_checker_v2_0_3=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_3 +v_frmbuf_wr_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_2 +v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9 +mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 +lte_dl_channel_encoder_v3_0_15=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_15 +axi_protocol_converter_v2_1_19=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_19 +xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0 +clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0 +axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0 +microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7 +cmpy_v6_0_17=$RDI_DATADIR/xsim/ip/cmpy_v6_0_17 +cmac_v2_3_5=$RDI_DATADIR/xsim/ip/cmac_v2_3_5 +axi_timebase_wdt_v3_0_11=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_11 +tcc_decoder_3gppmm_v2_0_18=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_18 +mipi_dphy_v4_1_3=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_1_3 +v_deinterlacer_v5_0_13=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_13 +dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16 +axi_fifo_mm_s_v4_1_16=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_16 +processing_system7_vip_v1_0_7=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_7 +g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18 +rs_decoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_16 +c_shift_ram_v12_0_13=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_13 +displayport_v7_0_11=$RDI_DATADIR/xsim/ip/displayport_v7_0_11 +v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 +v_deinterlacer_v4_0_12=$RDI_DATADIR/xsim/ip/v_deinterlacer_v4_0_12 +sem_v4_1_12=$RDI_DATADIR/xsim/ip/sem_v4_1_12 +xaui_v12_3_6=$RDI_DATADIR/xsim/ip/xaui_v12_3_6 +ten_gig_eth_mac_v15_1_7=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_7 +oddr_v1_0_0=$RDI_DATADIR/xsim/ip/oddr_v1_0_0 +c_addsub_v12_0_13=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_13 +v_ccm_v6_0_15=$RDI_DATADIR/xsim/ip/v_ccm_v6_0_15 +zynq_ultra_ps_e_vip_v1_0_5=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_5 +cic_compiler_v4_0_14=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_14 +versal_cips_v1_0_0=$RDI_DATADIR/xsim/ip/versal_cips_v1_0_0 +c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6 +axi_memory_init_v1_0_0=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_0 +xxv_ethernet_v2_4_4=$RDI_DATADIR/xsim/ip/xxv_ethernet_v2_4_4 +pr_decoupler_v1_0_7=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_7 +timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 +lte_pucch_receiver_v2_0_16=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_16 +zynq_ultra_ps_e_v3_2_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_3 +v_gamma_lut_v1_0_5=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_5 +ethernet_1_10_25g_v2_0_4=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_0_4 +bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 +pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 +tcc_encoder_3gpplte_v4_0_15=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_15 +polar_v1_0_3=$RDI_DATADIR/xsim/ip/polar_v1_0_3 +cmac_usplus_v2_5_1=$RDI_DATADIR/xsim/ip/cmac_usplus_v2_5_1 +rxaui_v4_4_6=$RDI_DATADIR/xsim/ip/rxaui_v4_4_6 +xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6 +v_gamma_v7_0_15=$RDI_DATADIR/xsim/ip/v_gamma_v7_0_15 +ernic_v1_0_1=$RDI_DATADIR/xsim/ip/ernic_v1_0_1 +high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3 +mailbox_v2_1_11=$RDI_DATADIR/xsim/ip/mailbox_v2_1_11 +video_frame_crc_v1_0_1=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_1 +axi_sg_v4_1_12=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_12 +ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0 +lmb_bram_if_cntlr_v4_0_16=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_16 +dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1 +rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0 +axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6 +v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0 +stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0 +lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 +uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3 +pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4 +lmb_v10_v3_0_9=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_9 +axis_interconnect_v1_1_17=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_17 +cordic_v6_0_15=$RDI_DATADIR/xsim/ip/cordic_v6_0_15 +axis_register_slice_v1_1_19=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_19 +axis_switch_v1_1_19=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_19 +axi_interconnect_v1_7_16=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_16 +mult_gen_v12_0_15=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_15 +spdif_v2_0_21=$RDI_DATADIR/xsim/ip/spdif_v2_0_21 +v_hscaler_v1_0_13=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_13 +xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6 +roe_framer_v2_0_0=$RDI_DATADIR/xsim/ip/roe_framer_v2_0_0 +axi_quad_spi_v3_2_18=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_18 +axi_bram_ctrl_v4_1_1=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_1 +axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 +axi_protocol_checker_v2_0_5=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_5 +axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0 +mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7 +aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0 +xtlm=$RDI_DATADIR/xsim/ip/xtlm +iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0 +ieee802d3_clause74_fec_v1_0_4=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_4 +xlconcat_v2_1_3=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_3 +perf_axi_tg_v1_0_8=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_8 +axi_crossbar_v2_1_20=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_20 +tsn_endpoint_ethernet_mac_block_v1_0_4=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_4 +v_ycrcb2rgb_v7_1_13=$RDI_DATADIR/xsim/ip/v_ycrcb2rgb_v7_1_13 +xhmc_v1_0_9=$RDI_DATADIR/xsim/ip/xhmc_v1_0_9 +dp_videoaxi4s_bridge_v1_0_0=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_0 +lte_ul_channel_decoder_v4_0_16=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_16 +soft_ecc_proxy_v1_0_0=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_0 +pr_bitstream_monitor_v1_0_1=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_1 +sync_ip=$RDI_DATADIR/xsim/ip/sync_ip +v_frmbuf_rd_v2_1_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_2 +c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6 +axi_mcdma_v1_0_5=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_5 +fc32_rs_fec_v1_0_10=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_10 +c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6 +g709_fec_v2_4_1=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_1 +lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0 +ai_pl=$RDI_DATADIR/xsim/ip/ai_pl +fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 +v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0 +l_ethernet_v2_3_5=$RDI_DATADIR/xsim/ip/l_ethernet_v2_3_5 +ethernet_1_10_25g_v2_1_3=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_1_3 +microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 +v_uhdsdi_audio_v2_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_1 +ldpc_v2_0_3=$RDI_DATADIR/xsim/ip/ldpc_v2_0_3 +xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6 +xpm=$RDI_DATADIR/xsim/ip/xpm +srio_gen2_v4_1_6=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_6 +g975_efec_i4_v1_0_17=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_17 +noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0 +xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10 +tmr_sem_v1_0_8=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_8 +generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0 +ten_gig_eth_pcs_pma_v6_0_15=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_15 +can_v5_0_22=$RDI_DATADIR/xsim/ip/can_v5_0_22 +av_pat_gen_v1_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_0 +fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1 +lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0 +axis_dwidth_converter_v1_1_18=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_18 +lte_rach_detector_v3_1_5=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_5 +axi_iic_v2_0_22=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_22 +axi_pcie_v2_9_1=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_1 +util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4 +sim_trig_top_v1_0=$RDI_DATADIR/xsim/ip/sim_trig_top_v1_0 +v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0 +v_tpg_v7_0_13=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_13 +sd_fec_v1_1_3=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_3 +flexo_100g_rs_fec_v1_0_10=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_10 +xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6 +lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2 +v_multi_scaler_v1_0_1=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_0_1 +axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0 +advanced_io_wizard_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_0 +mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8 +axi_pcie3_v3_0_9=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_9 +axi_vfifo_ctrl_v2_0_21=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_21 +xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0 +jesd204c_v4_1_0=$RDI_DATADIR/xsim/ip/jesd204c_v4_1_0 diff --git a/TP_VGA/TP_VGA.runs/.jobs/vrs_config_1.xml b/TP_VGA/TP_VGA.runs/.jobs/vrs_config_1.xml new file mode 100755 index 0000000..3794cfa --- /dev/null +++ b/TP_VGA/TP_VGA.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/.Vivado_Synthesis.queue.rst b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/.Vivado_Synthesis.queue.rst new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/.Vivado_Synthesis.queue.rst diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc new file mode 100755 index 0000000..f530b84 --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc @@ -0,0 +1,4 @@ +set_property SRC_FILE_INFO {cfile:c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc rfile:../../../TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc id:1 order:EARLY scoped_inst:inst} [current_design] +current_instance inst +set_property src_info {type:SCOPED_XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design] +set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1 diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/.vivado.begin.rst b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/.vivado.begin.rst new file mode 100755 index 0000000..a44704f --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/.vivado.end.rst b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/.vivado.end.rst new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/.vivado.end.rst diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/ISEWrap.js b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/ISEWrap.js new file mode 100755 index 0000000..3e83de1 --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/ISEWrap.sh b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/ISEWrap.sh new file mode 100755 index 0000000..f679f2e --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/__synthesis_is_complete__ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/__synthesis_is_complete__ new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/__synthesis_is_complete__ diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp new file mode 100755 index 0000000..0e4fef4 Binary files /dev/null and b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp differ diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl new file mode 100755 index 0000000..715c0c6 --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl @@ -0,0 +1,177 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param chipscope.maxJobs 1 +set_param xicom.use_bs_reader 1 +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7a35tcpg236-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.cache/wt [current_project] +set_property parent.project_path C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.xpr [current_project] +set_property XPM_LIBRARIES XPM_CDC [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language VHDL [current_project] +set_property board_part digilentinc.com:basys3:part0:1.2 [current_project] +set_property ip_output_repo c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +set_property used_in_implementation false [get_files -all c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] +set_property used_in_implementation false [get_files -all c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] +set_property used_in_implementation false [get_files -all c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1 -new_name clk_wiz_0 -ip [get_ips clk_wiz_0]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top clk_wiz_0 -part xc7a35tcpg236-1 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix clk_wiz_0_ clk_wiz_0.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.v + lappend ipCachedFiles clk_wiz_0_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.vhdl + lappend ipCachedFiles clk_wiz_0_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.v + lappend ipCachedFiles clk_wiz_0_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.vhdl + lappend ipCachedFiles clk_wiz_0_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp clk_wiz_0.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips clk_wiz_0] +} + +rename_ref -prefix_all clk_wiz_0_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef clk_wiz_0.dcp +create_report "clk_wiz_0_synth_1_synth_report_utilization_0" "report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb" + +if { [catch { + file copy -force C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + write_verilog -force -mode synth_stub c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +if { [catch { + file copy -force C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + file rename -force C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0_stub.v c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0_stub.vhdl c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0_sim_netlist.v c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + file rename -force C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0_sim_netlist.vhdl c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +}; # end if cached_ip + +if {[file isdir C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.ip_user_files/ip/clk_wiz_0]} { + catch { + file copy -force c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.ip_user_files/ip/clk_wiz_0 + } +} + +if {[file isdir C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.ip_user_files/ip/clk_wiz_0]} { + catch { + file copy -force c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.ip_user_files/ip/clk_wiz_0 + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0.vds b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0.vds new file mode 100755 index 0000000..33af64b --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0.vds @@ -0,0 +1,338 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Wed Oct 4 16:31:07 2023 +# Process ID: 416 +# Current directory: C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1 +# Command line: vivado.exe -log clk_wiz_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl +# Log file: C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0.vds +# Journal file: C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1\vivado.jou +#----------------------------------------------------------- +source clk_wiz_0.tcl -notrace +Command: synth_design -top clk_wiz_0 -part xc7a35tcpg236-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 4700 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 737.098 ; gain = 178.203 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0' [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70] +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0_clk_wiz' [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68] +INFO: [Synth 8-6157] synthesizing module 'IBUF' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:32856] + Parameter CAPACITANCE bound to: DONT_CARE - type: string + Parameter IBUF_DELAY_VALUE bound to: 0 - type: string + Parameter IBUF_LOW_PWR bound to: TRUE - type: string + Parameter IFD_DELAY_VALUE bound to: AUTO - type: string + Parameter IOSTANDARD bound to: DEFAULT - type: string +INFO: [Synth 8-6155] done synthesizing module 'IBUF' (1#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:32856] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:39813] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT_F bound to: 50.375000 - type: float + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float + Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float + Parameter CLKOUT0_DIVIDE_F bound to: 15.500000 - type: float + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string + Parameter COMPENSATION bound to: ZHOLD - type: string + Parameter DIVCLK_DIVIDE bound to: 5 - type: integer + Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 + Parameter IS_PSEN_INVERTED bound to: 1'b0 + Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 + Parameter IS_PWRDWN_INVERTED bound to: 1'b0 + Parameter IS_RST_INVERTED bound to: 1'b0 + Parameter REF_JITTER1 bound to: 0.010000 - type: float + Parameter REF_JITTER2 bound to: 0.010000 - type: float + Parameter SS_EN bound to: FALSE - type: string + Parameter SS_MODE bound to: CENTER_HIGH - type: string + Parameter SS_MOD_PERIOD bound to: 10000 - type: integer + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (2#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:39813] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1075] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (3#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1075] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0_clk_wiz' (4#1) [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0' (5#1) [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 801.016 ; gain = 242.121 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 801.016 ; gain = 242.121 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 801.016 ; gain = 242.121 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst' +Parsing XDC File [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst' +Finished Parsing XDC File [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst' +Parsing XDC File [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst' +Finished Parsing XDC File [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_wiz_0_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/clk_wiz_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Parsing XDC File [C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/dont_touch.xdc] +Finished Parsing XDC File [C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 835.332 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 836.332 ; gain = 1.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 836.332 ; gain = 277.438 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcpg236-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 836.332 ; gain = 277.438 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for inst. (constraint file C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 836.332 ; gain = 277.438 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 836.332 ; gain = 277.438 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 836.332 ; gain = 277.438 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 869.223 ; gain = 310.328 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 869.223 ; gain = 310.328 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 878.801 ; gain = 319.906 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 894.617 ; gain = 335.723 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 894.617 ; gain = 335.723 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 894.617 ; gain = 335.723 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 894.617 ; gain = 335.723 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 894.617 ; gain = 335.723 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 894.617 ; gain = 335.723 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----------+------+ +| |Cell |Count | ++------+-----------+------+ +|1 |BUFG | 2| +|2 |MMCME2_ADV | 1| +|3 |IBUF | 1| ++------+-----------+------+ + +Report Instance Areas: ++------+---------+------------------+------+ +| |Instance |Module |Cells | ++------+---------+------------------+------+ +|1 |top | | 4| +|2 | inst |clk_wiz_0_clk_wiz | 4| ++------+---------+------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 894.617 ; gain = 335.723 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 894.617 ; gain = 300.406 +Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 894.617 ; gain = 335.723 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 915.270 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 915.270 ; gain = 597.117 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 915.270 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP clk_wiz_0, cache-ID = 4e61f1d817877072 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 915.270 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Wed Oct 4 16:31:39 2023... diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb new file mode 100755 index 0000000..636d896 Binary files /dev/null and b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb differ diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt new file mode 100755 index 0000000..8102333 --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt @@ -0,0 +1,173 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +| Date : Wed Oct 4 16:31:39 2023 +| Host : WIN10-TP running 64-bit major release (build 9200) +| Command : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb +| Design : clk_wiz_0 +| Device : 7a35tcpg236-1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 0 | 0 | 20800 | 0.00 | +| LUT as Logic | 0 | 0 | 20800 | 0.00 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 0 | 0 | 41600 | 0.00 | +| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 1 | 0 | 106 | 0.94 | +| Bonded IPADs | 0 | 0 | 10 | 0.00 | +| Bonded OPADs | 0 | 0 | 4 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 104 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 106 | 0.00 | +| OLOGIC | 0 | 0 | 106 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 2 | 0 | 32 | 6.25 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 1 | 0 | 5 | 20.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++------------+------+---------------------+ +| Ref Name | Used | Functional Category | ++------------+------+---------------------+ +| BUFG | 2 | Clock | +| MMCME2_ADV | 1 | Clock | +| IBUF | 1 | IO | ++------------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/dont_touch.xdc b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/dont_touch.xdc new file mode 100755 index 0000000..ce3b9ed --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/dont_touch.xdc @@ -0,0 +1,32 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +# IP: The module: 'clk_wiz_0' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc +# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc +# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# IP: c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +# IP: The module: 'clk_wiz_0' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc +# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc +# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/gen_run.xml b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/gen_run.xml new file mode 100755 index 0000000..d2f150f --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/gen_run.xml @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/htr.txt b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/htr.txt new file mode 100755 index 0000000..1ed47e3 --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/project.wdf b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/project.wdf new file mode 100755 index 0000000..cac5274 --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/project.wdf @@ -0,0 +1,32 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:32:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:32:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f335c636c6b5f77697a5f30:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3130646337373431653963363462343261363830653262343661643735663634:506172656e742050412070726f6a656374204944:00 +eof:3176436582 diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/rundef.js b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/rundef.js new file mode 100755 index 0000000..dab32d1 --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/rundef.js @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/runme.bat b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/runme.bat new file mode 100755 index 0000000..bc78723 --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/runme.log b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/runme.log new file mode 100755 index 0000000..00f4391 --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/runme.log @@ -0,0 +1,337 @@ + +*** Running vivado + with args -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source clk_wiz_0.tcl -notrace +Command: synth_design -top clk_wiz_0 -part xc7a35tcpg236-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 4700 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 737.098 ; gain = 178.203 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0' [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70] +INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0_clk_wiz' [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68] +INFO: [Synth 8-6157] synthesizing module 'IBUF' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:32856] + Parameter CAPACITANCE bound to: DONT_CARE - type: string + Parameter IBUF_DELAY_VALUE bound to: 0 - type: string + Parameter IBUF_LOW_PWR bound to: TRUE - type: string + Parameter IFD_DELAY_VALUE bound to: AUTO - type: string + Parameter IOSTANDARD bound to: DEFAULT - type: string +INFO: [Synth 8-6155] done synthesizing module 'IBUF' (1#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:32856] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:39813] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT_F bound to: 50.375000 - type: float + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float + Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float + Parameter CLKOUT0_DIVIDE_F bound to: 15.500000 - type: float + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string + Parameter COMPENSATION bound to: ZHOLD - type: string + Parameter DIVCLK_DIVIDE bound to: 5 - type: integer + Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 + Parameter IS_PSEN_INVERTED bound to: 1'b0 + Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 + Parameter IS_PWRDWN_INVERTED bound to: 1'b0 + Parameter IS_RST_INVERTED bound to: 1'b0 + Parameter REF_JITTER1 bound to: 0.010000 - type: float + Parameter REF_JITTER2 bound to: 0.010000 - type: float + Parameter SS_EN bound to: FALSE - type: string + Parameter SS_MODE bound to: CENTER_HIGH - type: string + Parameter SS_MOD_PERIOD bound to: 10000 - type: integer + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (2#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:39813] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1075] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (3#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1075] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0_clk_wiz' (4#1) [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68] +INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0' (5#1) [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 801.016 ; gain = 242.121 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 801.016 ; gain = 242.121 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 801.016 ; gain = 242.121 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst' +Parsing XDC File [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst' +Finished Parsing XDC File [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst' +Parsing XDC File [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst' +Finished Parsing XDC File [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_wiz_0_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/clk_wiz_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Parsing XDC File [C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/dont_touch.xdc] +Finished Parsing XDC File [C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 835.332 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 836.332 ; gain = 1.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 836.332 ; gain = 277.438 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcpg236-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 836.332 ; gain = 277.438 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for inst. (constraint file C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 836.332 ; gain = 277.438 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 836.332 ; gain = 277.438 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 836.332 ; gain = 277.438 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 869.223 ; gain = 310.328 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 869.223 ; gain = 310.328 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 878.801 ; gain = 319.906 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 894.617 ; gain = 335.723 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 894.617 ; gain = 335.723 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 894.617 ; gain = 335.723 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 894.617 ; gain = 335.723 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 894.617 ; gain = 335.723 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 894.617 ; gain = 335.723 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----------+------+ +| |Cell |Count | ++------+-----------+------+ +|1 |BUFG | 2| +|2 |MMCME2_ADV | 1| +|3 |IBUF | 1| ++------+-----------+------+ + +Report Instance Areas: ++------+---------+------------------+------+ +| |Instance |Module |Cells | ++------+---------+------------------+------+ +|1 |top | | 4| +|2 | inst |clk_wiz_0_clk_wiz | 4| ++------+---------+------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 894.617 ; gain = 335.723 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 894.617 ; gain = 300.406 +Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 894.617 ; gain = 335.723 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 915.270 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 915.270 ; gain = 597.117 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 915.270 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP clk_wiz_0, cache-ID = 4e61f1d817877072 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 915.270 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Wed Oct 4 16:31:39 2023... diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/runme.sh b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/runme.sh new file mode 100755 index 0000000..4447b0d --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin +else + PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/vivado.jou b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/vivado.jou new file mode 100755 index 0000000..a873a88 --- /dev/null +++ b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Wed Oct 4 16:31:07 2023 +# Process ID: 416 +# Current directory: C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1 +# Command line: vivado.exe -log clk_wiz_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl +# Log file: C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/clk_wiz_0.vds +# Journal file: C:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1\vivado.jou +#----------------------------------------------------------- +source clk_wiz_0.tcl -notrace diff --git a/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/vivado.pb b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/vivado.pb new file mode 100755 index 0000000..9dcfbdd Binary files /dev/null and b/TP_VGA/TP_VGA.runs/clk_wiz_0_synth_1/vivado.pb differ diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp new file mode 100755 index 0000000..0e4fef4 Binary files /dev/null and b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp differ diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v new file mode 100755 index 0000000..ba688a9 --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v @@ -0,0 +1,86 @@ + +// file: clk_wiz_0.v +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1____65.000______0.000______50.0______254.866____297.890 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________100.000____________0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_3_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) + +module clk_wiz_0 + ( + // Clock out ports + output clk_out1, + // Clock in ports + input clk_in1 + ); + + clk_wiz_0_clk_wiz inst + ( + // Clock out ports + .clk_out1(clk_out1), + // Clock in ports + .clk_in1(clk_in1) + ); + +endmodule diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.vho b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.vho new file mode 100755 index 0000000..bb4b3b2 --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.vho @@ -0,0 +1,88 @@ + +-- +-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +------------------------------------------------------------------------------ +-- User entered comments +------------------------------------------------------------------------------ +-- None +-- +------------------------------------------------------------------------------ +-- Output Output Phase Duty Cycle Pk-to-Pk Phase +-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +------------------------------------------------------------------------------ +-- clk_out1____65.000______0.000______50.0______254.866____297.890 +-- +------------------------------------------------------------------------------ +-- Input Clock Freq (MHz) Input Jitter (UI) +------------------------------------------------------------------------------ +-- __primary_________100.000____________0.010 + + +-- The following code must appear in the VHDL architecture header: +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component clk_wiz_0 +port + (-- Clock in ports + -- Clock out ports + clk_out1 : out std_logic; + clk_in1 : in std_logic + ); +end component; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : clk_wiz_0 + port map ( + -- Clock out ports + clk_out1 => clk_out1, + -- Clock in ports + clk_in1 => clk_in1 + ); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci new file mode 100755 index 0000000..89d15c9 --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci @@ -0,0 +1,696 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_wiz_0 + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 100.0 + 0000 + 0000 + 65.000 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 65.000 + 0.000 + 50.000 + 65.000 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + clk_out1 + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 0.65 + 0.65 + 0.65 + 0.65 + 0.65 + 0.65 + dout + drdy + dwe + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________100.000____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 50.375 + 0.000 + FALSE + 10.000 + 10.000 + 15.500 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 5 + None + 0.010 + 0.010 + FALSE + 1 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + clk_out1____65.000______0.000______50.0______254.866____297.890 + no_CLK_OUT2_output + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + MMCM + AUTO + 100.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + clk_wiz_0 + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 0.010 + 100.0 + 0.010 + BUFG + 254.866 + false + 297.890 + 50.000 + 65.000 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clk_wiz_0 + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 50.375 + 0.000 + false + 10.000 + 10.000 + 15.500 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 5 + None + 0.010 + 0.010 + false + 1 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 100.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + false + false + false + false + true + false + false + false + false + false + artix7 + digilentinc.com:basys3:part0:1.2 + + xc7a35t + cpg236 + VHDL + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc new file mode 100755 index 0000000..a5da024 --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc @@ -0,0 +1,60 @@ + +# file: clk_wiz_0.xdc +# +# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system. If required +# commented constraints can be used in the top level xdc +#---------------------------------------------------------------- +# Connect to input port when clock capable pin is selected for input +create_clock -period 10.000 [get_ports clk_in1] +set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1 + + +set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*] diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml new file mode 100755 index 0000000..0aa026e --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml @@ -0,0 +1,4886 @@ + + + xilinx.com + customized_ip + clk_wiz_0 + 1.0 + + + s_axi_lite + S_AXI_LITE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARREADY + + + s_axi_arready + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWREADY + + + s_axi_awready + + + + + AWVALID + + + s_axi_awvalid + + + + + BREADY + + + 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+ VHDL Instantiation Template + vhdlSource:vivado.xilinx.com:synthesis.template + vhdl + clk_wiz_v6_0_3 + + xilinx_vhdlinstantiationtemplate_view_fileset + + + + GENtimestamp + Wed Oct 04 14:30:53 UTC 2023 + + + outputProductCRC + 9:a191ce05 + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + clk_wiz_v6_0_3 + + xilinx_anylanguagesynthesis_view_fileset + + + + GENtimestamp + Wed Oct 04 14:31:03 UTC 2023 + + + outputProductCRC + 9:a191ce05 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:a191ce05 + + + + + xilinx_anylanguagesynthesiswrapper + Synthesis Wrapper + :vivado.xilinx.com:synthesis.wrapper + clk_wiz_0 + + xilinx_anylanguagesynthesiswrapper_view_fileset + + + + GENtimestamp + Wed Oct 04 14:31:03 UTC 2023 + + + outputProductCRC + 9:a191ce05 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + clk_wiz_v6_0_3 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + GENtimestamp + Wed Oct 04 14:31:03 UTC 2023 + + + outputProductCRC + 9:32979d73 + + + + + xilinx_anylanguagesimulationwrapper + Simulation Wrapper + :vivado.xilinx.com:simulation.wrapper + clk_wiz_0 + + xilinx_anylanguagesimulationwrapper_view_fileset + + + + GENtimestamp + Wed Oct 04 14:31:03 UTC 2023 + + + outputProductCRC + 9:32979d73 + + + + + xilinx_implementation + Implementation + :vivado.xilinx.com:implementation + + xilinx_implementation_view_fileset + + + + GENtimestamp + Wed Oct 04 14:31:04 UTC 2023 + + + outputProductCRC + 9:a191ce05 + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + GENtimestamp + Wed Oct 04 14:31:04 UTC 2023 + + + outputProductCRC + 9:a191ce05 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Wed Oct 04 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C_CLKOUT7_DRIVES + BUFG + + + C_INCLK_SUM_ROW0 + Input Clock Freq (MHz) Input Jitter (UI) + + + C_INCLK_SUM_ROW1 + __primary_________100.000____________0.010 + + + C_INCLK_SUM_ROW2 + no_secondary_input_clock + + + C_OUTCLK_SUM_ROW0A + C Outclk Sum Row0a + Output Output Phase Duty Cycle Pk-to-Pk Phase + + + C_OUTCLK_SUM_ROW0B + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + + + C_OUTCLK_SUM_ROW1 + clk_out1____65.000______0.000______50.0______254.866____297.890 + + + C_OUTCLK_SUM_ROW2 + no_CLK_OUT2_output + + + C_OUTCLK_SUM_ROW3 + no_CLK_OUT3_output + + + C_OUTCLK_SUM_ROW4 + no_CLK_OUT4_output + + + C_OUTCLK_SUM_ROW5 + no_CLK_OUT5_output + + + C_OUTCLK_SUM_ROW6 + no_CLK_OUT6_output + + + C_OUTCLK_SUM_ROW7 + no_CLK_OUT7_output + + + C_CLKOUT1_REQUESTED_OUT_FREQ + 65.000 + + + C_CLKOUT2_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT1_REQUESTED_PHASE + 0.000 + + + C_CLKOUT2_REQUESTED_PHASE + 0.000 + + + C_CLKOUT3_REQUESTED_PHASE + 0.000 + + + C_CLKOUT4_REQUESTED_PHASE + 0.000 + + + C_CLKOUT5_REQUESTED_PHASE + 0.000 + + + C_CLKOUT6_REQUESTED_PHASE + 0.000 + + + C_CLKOUT7_REQUESTED_PHASE + 0.000 + + + C_CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT1_OUT_FREQ + 65.000 + + + C_CLKOUT2_OUT_FREQ + 100.000 + + + C_CLKOUT3_OUT_FREQ + 100.000 + + + C_CLKOUT4_OUT_FREQ + 100.000 + + + C_CLKOUT5_OUT_FREQ + 100.000 + + + C_CLKOUT6_OUT_FREQ + 100.000 + + + C_CLKOUT7_OUT_FREQ + 100.000 + + + C_CLKOUT1_PHASE + 0.000 + + + C_CLKOUT2_PHASE + 0.000 + + + C_CLKOUT3_PHASE + 0.000 + + + C_CLKOUT4_PHASE + 0.000 + + + C_CLKOUT5_PHASE + 0.000 + + + C_CLKOUT6_PHASE + 0.000 + + + C_CLKOUT7_PHASE + 0.000 + + + C_CLKOUT1_DUTY_CYCLE + 50.0 + + + C_CLKOUT2_DUTY_CYCLE + 50.000 + + + C_CLKOUT3_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_DUTY_CYCLE + 50.000 + + + C_USE_SAFE_CLOCK_STARTUP + 0 + + + C_USE_CLOCK_SEQUENCING + 0 + + + C_CLKOUT1_SEQUENCE_NUMBER + 1 + + + C_CLKOUT2_SEQUENCE_NUMBER + 1 + + + C_CLKOUT3_SEQUENCE_NUMBER + 1 + + + C_CLKOUT4_SEQUENCE_NUMBER + 1 + + + C_CLKOUT5_SEQUENCE_NUMBER + 1 + + + C_CLKOUT6_SEQUENCE_NUMBER + 1 + + + C_CLKOUT7_SEQUENCE_NUMBER + 1 + + + C_MMCM_NOTES + None + + + C_MMCM_BANDWIDTH + OPTIMIZED + + + C_MMCM_CLKFBOUT_MULT_F + 50.375 + + + C_MMCM_CLKIN1_PERIOD + 10.000 + + + C_MMCM_CLKIN2_PERIOD + 10.000 + + + C_MMCM_CLKOUT4_CASCADE + FALSE + + + C_MMCM_CLOCK_HOLD + FALSE + + + C_MMCM_COMPENSATION + ZHOLD + + + C_MMCM_DIVCLK_DIVIDE + 5 + + + C_MMCM_REF_JITTER1 + 0.010 + + + C_MMCM_REF_JITTER2 + 0.010 + + + C_MMCM_STARTUP_WAIT + FALSE + + + C_MMCM_CLKOUT0_DIVIDE_F + 15.500 + + + C_MMCM_CLKOUT1_DIVIDE + 1 + + + C_MMCM_CLKOUT2_DIVIDE + 1 + + + C_MMCM_CLKOUT3_DIVIDE + 1 + + + C_MMCM_CLKOUT4_DIVIDE + 1 + + + C_MMCM_CLKOUT5_DIVIDE + 1 + + + C_MMCM_CLKOUT6_DIVIDE + 1 + + + C_MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKFBOUT_PHASE + 0.000 + + + C_MMCM_CLKOUT0_PHASE + 0.000 + + + C_MMCM_CLKOUT1_PHASE + 0.000 + + + C_MMCM_CLKOUT2_PHASE + 0.000 + + + C_MMCM_CLKOUT3_PHASE + 0.000 + + + C_MMCM_CLKOUT4_PHASE + 0.000 + + + C_MMCM_CLKOUT5_PHASE + 0.000 + + + C_MMCM_CLKOUT6_PHASE + 0.000 + + + C_MMCM_CLKFBOUT_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT0_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT1_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT2_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT3_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT4_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT5_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT6_USE_FINE_PS + FALSE + + + C_PLL_NOTES + No notes + + + C_PLL_BANDWIDTH + OPTIMIZED + + + C_PLL_CLK_FEEDBACK + CLKFBOUT + + + C_PLL_CLKFBOUT_MULT + 1 + + + C_PLL_CLKIN_PERIOD + 1.000 + + + C_PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + C_PLL_DIVCLK_DIVIDE + 1 + + + C_PLL_REF_JITTER + 0.010 + + + C_PLL_CLKOUT0_DIVIDE + 1 + + + C_PLL_CLKOUT1_DIVIDE + 1 + + + C_PLL_CLKOUT2_DIVIDE + 1 + + + C_PLL_CLKOUT3_DIVIDE + 1 + + + C_PLL_CLKOUT4_DIVIDE + 1 + + + C_PLL_CLKOUT5_DIVIDE + 1 + + + C_PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_PLL_CLKFBOUT_PHASE + 0.000 + + + C_PLL_CLKOUT0_PHASE + 0.000 + + + C_PLL_CLKOUT1_PHASE + 0.000 + + + C_PLL_CLKOUT2_PHASE + 0.000 + + + C_PLL_CLKOUT3_PHASE + 0.000 + + + C_PLL_CLKOUT4_PHASE + 0.000 + + + C_PLL_CLKOUT5_PHASE + 0.000 + + + C_CLOCK_MGR_TYPE + NA + + + C_OVERRIDE_MMCM + 0 + + + C_OVERRIDE_PLL + 0 + + + C_PRIMARY_PORT + clk_in1 + + + C_SECONDARY_PORT + clk_in2 + + + C_CLK_OUT1_PORT + clk_out1 + + + C_CLK_OUT2_PORT + clk_out2 + + + C_CLK_OUT3_PORT + clk_out3 + + + C_CLK_OUT4_PORT + clk_out4 + + + C_CLK_OUT5_PORT + clk_out5 + + + C_CLK_OUT6_PORT + clk_out6 + + + C_CLK_OUT7_PORT + clk_out7 + + + C_RESET_PORT + reset + + + C_LOCKED_PORT + locked + + + C_CLKFB_IN_PORT + clkfb_in + + + C_CLKFB_IN_P_PORT + clkfb_in_p + + + C_CLKFB_IN_N_PORT + clkfb_in_n + + + C_CLKFB_OUT_PORT + clkfb_out + + + C_CLKFB_OUT_P_PORT + clkfb_out_p + + + C_CLKFB_OUT_N_PORT + clkfb_out_n + + + C_POWER_DOWN_PORT + power_down + + + C_DADDR_PORT + daddr + + + C_DCLK_PORT + dclk + + + C_DRDY_PORT + drdy + + + C_DWE_PORT + dwe + + + C_DIN_PORT + din + + + C_DOUT_PORT + dout + + + C_DEN_PORT + den + + + C_PSCLK_PORT + psclk + + + C_PSEN_PORT + psen + + + C_PSINCDEC_PORT + psincdec + + + C_PSDONE_PORT + psdone + + + C_CLK_VALID_PORT + CLK_VALID + + + C_STATUS_PORT + STATUS + + + C_CLK_IN_SEL_PORT + clk_in_sel + + + C_INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + C_CLKFB_STOPPED_PORT + clkfb_stopped + + + C_CLKIN1_JITTER_PS + 100.0 + + + C_CLKIN2_JITTER_PS + 100.0 + + + C_PRIMITIVE + MMCM + + + C_SS_MODE + CENTER_HIGH + + + C_SS_MOD_PERIOD + 4000 + + + C_SS_MOD_TIME + 0.004 + + + C_HAS_CDDC + 0 + + + C_CDDCDONE_PORT + cddcdone + + + C_CDDCREQ_PORT + cddcreq + + + C_CLKOUTPHY_MODE + VCO + + + C_ENABLE_CLKOUTPHY + 0 + + + C_INTERFACE_SELECTION + 0 + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 11 + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + C_POWER_REG + 0000 + + + C_CLKOUT0_1 + 0000 + + + C_CLKOUT0_2 + 0000 + + + C_CLKOUT1_1 + 0000 + + + C_CLKOUT1_2 + 0000 + + + C_CLKOUT2_1 + 0000 + + + C_CLKOUT2_2 + 0000 + + + C_CLKOUT3_1 + 0000 + + + C_CLKOUT3_2 + 0000 + + + C_CLKOUT4_1 + 0000 + + + C_CLKOUT4_2 + 0000 + + + C_CLKOUT5_1 + 0000 + + + C_CLKOUT5_2 + 0000 + + + C_CLKOUT6_1 + 0000 + + + C_CLKOUT6_2 + 0000 + + + C_CLKFBOUT_1 + 0000 + + + C_CLKFBOUT_2 + 0000 + + + C_DIVCLK + 0000 + + + C_LOCK_1 + 0000 + + + C_LOCK_2 + 0000 + + + C_LOCK_3 + 0000 + + + C_FILTER_1 + 0000 + + + C_FILTER_2 + 0000 + + + C_DIVIDE1_AUTO + 1 + + + C_DIVIDE2_AUTO + 0.65 + + + C_DIVIDE3_AUTO + 0.65 + + + C_DIVIDE4_AUTO + 0.65 + + + C_DIVIDE5_AUTO + 0.65 + + + C_DIVIDE6_AUTO + 0.65 + + + C_DIVIDE7_AUTO + 0.65 + + + C_PLLBUFGCEDIV + false + + + C_MMCMBUFGCEDIV + false + + + C_PLLBUFGCEDIV1 + false + + + C_PLLBUFGCEDIV2 + false + + + C_PLLBUFGCEDIV3 + false + + + C_PLLBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV1 + false + + + C_MMCMBUFGCEDIV2 + false + + + C_MMCMBUFGCEDIV3 + false + + + C_MMCMBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV5 + false + + + C_MMCMBUFGCEDIV6 + false + + + C_MMCMBUFGCEDIV7 + false + + + C_CLKOUT1_MATCHED_ROUTING + false + + + C_CLKOUT2_MATCHED_ROUTING + false + + + C_CLKOUT3_MATCHED_ROUTING + false + + + C_CLKOUT4_MATCHED_ROUTING + false + + + C_CLKOUT5_MATCHED_ROUTING + false + + + C_CLKOUT6_MATCHED_ROUTING + false + + + C_CLKOUT7_MATCHED_ROUTING + false + + + C_CLKOUT0_ACTUAL_FREQ + 65.000 + + + C_CLKOUT1_ACTUAL_FREQ + 100.000 + + + C_CLKOUT2_ACTUAL_FREQ + 100.000 + + + C_CLKOUT3_ACTUAL_FREQ + 100.000 + + + C_CLKOUT4_ACTUAL_FREQ + 100.000 + + + C_CLKOUT5_ACTUAL_FREQ + 100.000 + + + C_CLKOUT6_ACTUAL_FREQ + 100.000 + + + + + + choice_list_1d3de01d + WAVEFORM + LATENCY + + + choice_list_876bfc32 + UI + PS + + + choice_list_a9bdfce0 + LOW + HIGH + OPTIMIZED + + + choice_list_b9d38208 + CLKFBOUT + CLKOUT0 + + + choice_list_ce26ebdb + Custom + reset + + + choice_list_e099fe6c + MMCM + PLL + + + choice_pairs_035ca1c3 + SYSTEM_SYNCHRONOUS + SOURCE_SYNCHRONOUS + INTERNAL + EXTERNAL + + + choice_pairs_0920eb1b + Custom + sys_diff_clock + + + choice_pairs_11d71346 + Single_ended_clock_capable_pin + Differential_clock_capable_pin + Global_buffer + No_buffer + + + choice_pairs_15c806d5 + FDBK_AUTO + FDBK_AUTO_OFFCHIP + FDBK_ONCHIP + FDBK_OFFCHIP + + + choice_pairs_3c2d3ec7 + SINGLE + DIFF + + + choice_pairs_502d9f23 + ZHOLD + EXTERNAL + INTERNAL + BUF_IN + + + choice_pairs_66e4c81f + BUFG + BUFH + BUFGCE + BUFHCE + No_buffer + + + choice_pairs_77d3d587 + MMCM + PLL + BUFGCE_DIV + + + choice_pairs_8b28f1f7 + Enable_AXI + Enable_DRP + + + choice_pairs_8eea9b32 + Units_MHz + Units_ns + + + choice_pairs_a4fbc00c + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_a8642b4c + No_Jitter + Min_O_Jitter + Max_I_Jitter + + + choice_pairs_c5ef7212 + Units_UI + Units_ps + + + choice_pairs_c6542ce1 + Custom + sys_clock + + + choice_pairs_e1c87518 + REL_PRIMARY + REL_SECONDARY + + + choice_pairs_f4e10086 + CENTER_HIGH + CENTER_LOW + DOWN_HIGH + DOWN_LOW + + + choice_pairs_f669c2f5 + frequency + Time + + + + + xilinx_vhdlinstantiationtemplate_view_fileset + + clk_wiz_0.vho + vhdlTemplate + + + + xilinx_anylanguagesynthesis_view_fileset + + clk_wiz_0.xdc + xdc + + processing_order + early + + + + clk_wiz_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + mmcm_pll_drp_func_7s_mmcm.vh + verilogSource + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_7s_pll.vh + verilogSource + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_us_mmcm.vh + verilogSource + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_us_pll.vh + verilogSource + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_us_plus_pll.vh + verilogSource + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_us_plus_mmcm.vh + verilogSource + true + clk_wiz_v6_0_3 + + + clk_wiz_0_clk_wiz.v + verilogSource + + + + xilinx_anylanguagesynthesiswrapper_view_fileset + + clk_wiz_0.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + mmcm_pll_drp_func_7s_mmcm.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_7s_pll.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_us_mmcm.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_us_pll.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_us_plus_pll.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_us_plus_mmcm.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_3 + + + clk_wiz_0_clk_wiz.v + verilogSource + + + + xilinx_anylanguagesimulationwrapper_view_fileset + + clk_wiz_0.v + verilogSource + + + + xilinx_implementation_view_fileset + + clk_wiz_0_board.xdc + xdc + USED_IN_board + USED_IN_implementation + USED_IN_synthesis + + + + xilinx_versioninformation_view_fileset + + doc/clk_wiz_v6_0_changelog.txt + text + + + + xilinx_externalfiles_view_fileset + + clk_wiz_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + clk_wiz_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + clk_wiz_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + clk_wiz_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + clk_wiz_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. + + + Component_Name + clk_wiz_0 + + + USER_CLK_FREQ0 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ1 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ2 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ3 + User Frequency(MHz) + 100.0 + + + ENABLE_CLOCK_MONITOR + Enable Clock Monitoring + false + + + ENABLE_USER_CLOCK0 + User Clock + false + + + ENABLE_USER_CLOCK1 + User Clock + false + + + ENABLE_USER_CLOCK2 + User Clock + false + + + ENABLE_USER_CLOCK3 + User Clock + false + + + Enable_PLL0 + User Clock + false + + + Enable_PLL1 + User Clock + false + + + REF_CLK_FREQ + Reference Frequency(MHz) + 100.0 + + + PRECISION + Tolerance(MHz) + 1 + + + PRIMITIVE + Primitive + MMCM + + + PRIMTYPE_SEL + Primtype Sel + mmcm_adv + + + CLOCK_MGR_TYPE + Clock Mgr Type + auto + + + USE_FREQ_SYNTH + true + + + USE_SPREAD_SPECTRUM + false + + + USE_PHASE_ALIGNMENT + true + + + USE_MIN_POWER + false + + + USE_DYN_PHASE_SHIFT + false + + + USE_DYN_RECONFIG + false + + + JITTER_SEL + No_Jitter + + + PRIM_IN_FREQ + 100.000 + + + PRIM_IN_TIMEPERIOD + 10.000 + + + IN_FREQ_UNITS + Units_MHz + + + PHASESHIFT_MODE + WAVEFORM + + + IN_JITTER_UNITS + Units_UI + + + RELATIVE_INCLK + REL_PRIMARY + + + USE_INCLK_SWITCHOVER + false + + + SECONDARY_IN_FREQ + 100.000 + + + SECONDARY_IN_TIMEPERIOD + 10.000 + + + SECONDARY_PORT + clk_in2 + + + SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + JITTER_OPTIONS + UI + + + CLKIN1_UI_JITTER + 0.010 + + + CLKIN2_UI_JITTER + 0.010 + + + PRIM_IN_JITTER + 0.010 + + + SECONDARY_IN_JITTER + 0.010 + + + CLKIN1_JITTER_PS + 100.0 + + + CLKIN2_JITTER_PS + 100.0 + + + CLKOUT1_USED + true + + + CLKOUT2_USED + false + + + CLKOUT3_USED + false + + + CLKOUT4_USED + false + + + CLKOUT5_USED + false + + + CLKOUT6_USED + false + + + CLKOUT7_USED + false + + + NUM_OUT_CLKS + 1 + + + CLK_OUT1_USE_FINE_PS_GUI + false + + + CLK_OUT2_USE_FINE_PS_GUI + false + + + CLK_OUT3_USE_FINE_PS_GUI + false + + + CLK_OUT4_USE_FINE_PS_GUI + false + + + CLK_OUT5_USE_FINE_PS_GUI + false + + + CLK_OUT6_USE_FINE_PS_GUI + false + + + CLK_OUT7_USE_FINE_PS_GUI + false + + + PRIMARY_PORT + clk_in1 + + + CLK_OUT1_PORT + clk_out1 + + + CLK_OUT2_PORT + clk_out2 + + + CLK_OUT3_PORT + clk_out3 + + + CLK_OUT4_PORT + clk_out4 + + + CLK_OUT5_PORT + clk_out5 + + + CLK_OUT6_PORT + clk_out6 + + + CLK_OUT7_PORT + clk_out7 + + + DADDR_PORT + daddr + + + DCLK_PORT + dclk + + + DRDY_PORT + drdy + + + DWE_PORT + dwe + + + DIN_PORT + din + + + DOUT_PORT + dout + + + DEN_PORT + den + + + PSCLK_PORT + psclk + + + PSEN_PORT + psen + + + PSINCDEC_PORT + psincdec + + + PSDONE_PORT + psdone + + + CLKOUT1_REQUESTED_OUT_FREQ + 65.000 + + + CLKOUT1_REQUESTED_PHASE + 0.000 + + + CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT2_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT2_REQUESTED_PHASE + 0.000 + + + CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT3_REQUESTED_PHASE + 0.000 + + + CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT4_REQUESTED_PHASE + 0.000 + + + CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT5_REQUESTED_PHASE + 0.000 + + + CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT6_REQUESTED_PHASE + 0.000 + + + CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT7_REQUESTED_PHASE + 0.000 + + + CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + USE_MAX_I_JITTER + false + + + USE_MIN_O_JITTER + false + + + CLKOUT1_MATCHED_ROUTING + false + + + CLKOUT2_MATCHED_ROUTING + false + + + CLKOUT3_MATCHED_ROUTING + false + + + CLKOUT4_MATCHED_ROUTING + false + + + CLKOUT5_MATCHED_ROUTING + false + + + CLKOUT6_MATCHED_ROUTING + false + + + CLKOUT7_MATCHED_ROUTING + false + + + PRIM_SOURCE + Single_ended_clock_capable_pin + + + CLKOUT1_DRIVES + BUFG + + + CLKOUT2_DRIVES + BUFG + + + CLKOUT3_DRIVES + BUFG + + + CLKOUT4_DRIVES + BUFG + + + CLKOUT5_DRIVES + BUFG + + + CLKOUT6_DRIVES + BUFG + + + CLKOUT7_DRIVES + BUFG + + + FEEDBACK_SOURCE + FDBK_AUTO + + + CLKFB_IN_SIGNALING + SINGLE + + + CLKFB_IN_PORT + clkfb_in + + + CLKFB_IN_P_PORT + clkfb_in_p + + + CLKFB_IN_N_PORT + clkfb_in_n + + + CLKFB_OUT_PORT + clkfb_out + + + CLKFB_OUT_P_PORT + clkfb_out_p + + + CLKFB_OUT_N_PORT + clkfb_out_n + + + PLATFORM + UNKNOWN + + + SUMMARY_STRINGS + empty + + + USE_LOCKED + false + + + CALC_DONE + empty + + + USE_RESET + false + + + USE_POWER_DOWN + false + + + USE_STATUS + false + + + USE_FREEZE + false + + + USE_CLK_VALID + false + + + USE_INCLK_STOPPED + false + + + USE_CLKFB_STOPPED + false + + + RESET_PORT + reset + + + LOCKED_PORT + locked + + + POWER_DOWN_PORT + power_down + + + CLK_VALID_PORT + CLK_VALID + + + STATUS_PORT + STATUS + + + CLK_IN_SEL_PORT + clk_in_sel + + + INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + CLKFB_STOPPED_PORT + clkfb_stopped + + + SS_MODE + CENTER_HIGH + + + SS_MOD_FREQ + 250 + + + SS_MOD_TIME + 0.004 + + + OVERRIDE_MMCM + false + + + MMCM_NOTES + None + + + MMCM_DIVCLK_DIVIDE + 5 + + + MMCM_BANDWIDTH + OPTIMIZED + + + MMCM_CLKFBOUT_MULT_F + 50.375 + + + MMCM_CLKFBOUT_PHASE + 0.000 + + + MMCM_CLKFBOUT_USE_FINE_PS + false + + + MMCM_CLKIN1_PERIOD + 10.000 + + + MMCM_CLKIN2_PERIOD + 10.000 + + + MMCM_CLKOUT4_CASCADE + false + + + MMCM_CLOCK_HOLD + false + + + MMCM_COMPENSATION + ZHOLD + + + MMCM_REF_JITTER1 + 0.010 + + + MMCM_REF_JITTER2 + 0.010 + + + MMCM_STARTUP_WAIT + false + + + MMCM_CLKOUT0_DIVIDE_F + 15.500 + + + MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT0_PHASE + 0.000 + + + MMCM_CLKOUT0_USE_FINE_PS + false + + + MMCM_CLKOUT1_DIVIDE + 1 + + + MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT1_PHASE + 0.000 + + + MMCM_CLKOUT1_USE_FINE_PS + false + + + MMCM_CLKOUT2_DIVIDE + 1 + + + MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT2_PHASE + 0.000 + + + MMCM_CLKOUT2_USE_FINE_PS + false + + + MMCM_CLKOUT3_DIVIDE + 1 + + + MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT3_PHASE + 0.000 + + + MMCM_CLKOUT3_USE_FINE_PS + false + + + MMCM_CLKOUT4_DIVIDE + 1 + + + MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT4_PHASE + 0.000 + + + MMCM_CLKOUT4_USE_FINE_PS + false + + + MMCM_CLKOUT5_DIVIDE + 1 + + + MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT5_PHASE + 0.000 + + + MMCM_CLKOUT5_USE_FINE_PS + false + + + MMCM_CLKOUT6_DIVIDE + 1 + + + MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT6_PHASE + 0.000 + + + MMCM_CLKOUT6_USE_FINE_PS + false + + + OVERRIDE_PLL + false + + + PLL_NOTES + None + + + PLL_BANDWIDTH + OPTIMIZED + + + PLL_CLKFBOUT_MULT + 4 + + + PLL_CLKFBOUT_PHASE + 0.000 + + + PLL_CLK_FEEDBACK + CLKFBOUT + + + PLL_DIVCLK_DIVIDE + 1 + + + PLL_CLKIN_PERIOD + 10.000 + + + PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + PLL_REF_JITTER + 0.010 + + + PLL_CLKOUT0_DIVIDE + 1 + + + PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT0_PHASE + 0.000 + + + PLL_CLKOUT1_DIVIDE + 1 + + + PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT1_PHASE + 0.000 + + + PLL_CLKOUT2_DIVIDE + 1 + + + PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT2_PHASE + 0.000 + + + PLL_CLKOUT3_DIVIDE + 1 + + + PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT3_PHASE + 0.000 + + + PLL_CLKOUT4_DIVIDE + 1 + + + PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT4_PHASE + 0.000 + + + PLL_CLKOUT5_DIVIDE + 1 + + + PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT5_PHASE + 0.000 + + + RESET_TYPE + Reset Type + ACTIVE_HIGH + + + USE_SAFE_CLOCK_STARTUP + false + + + USE_CLOCK_SEQUENCING + false + + + CLKOUT1_SEQUENCE_NUMBER + 1 + + + CLKOUT2_SEQUENCE_NUMBER + 1 + + + CLKOUT3_SEQUENCE_NUMBER + 1 + + + CLKOUT4_SEQUENCE_NUMBER + 1 + + + CLKOUT5_SEQUENCE_NUMBER + 1 + + + CLKOUT6_SEQUENCE_NUMBER + 1 + + + CLKOUT7_SEQUENCE_NUMBER + 1 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + CLK_IN1_BOARD_INTERFACE + Custom + + + CLK_IN2_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN1_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN2_BOARD_INTERFACE + Custom + + + AUTO_PRIMITIVE + MMCM + + + RESET_BOARD_INTERFACE + Custom + + + ENABLE_CDDC + false + + + CDDCDONE_PORT + cddcdone + + + CDDCREQ_PORT + cddcreq + + + ENABLE_CLKOUTPHY + false + + + CLKOUTPHY_REQUESTED_FREQ + 600.000 + + + CLKOUT1_JITTER + Clkout1 Jitter + 254.866 + + + CLKOUT1_PHASE_ERROR + Clkout1 Phase + 297.890 + + + CLKOUT2_JITTER + Clkout2 Jitter + 0.0 + + + CLKOUT2_PHASE_ERROR + Clkout2 Phase + 0.0 + + + CLKOUT3_JITTER + Clkout3 Jitter + 0.0 + + + CLKOUT3_PHASE_ERROR + Clkout3 Phase + 0.0 + + + CLKOUT4_JITTER + Clkout4 Jitter + 0.0 + + + CLKOUT4_PHASE_ERROR + Clkout4 Phase + 0.0 + + + CLKOUT5_JITTER + Clkout5 Jitter + 0.0 + + + CLKOUT5_PHASE_ERROR + Clkout5 Phase + 0.0 + + + CLKOUT6_JITTER + Clkout6 Jitter + 0.0 + + + CLKOUT6_PHASE_ERROR + Clkout6 Phase + 0.0 + + + CLKOUT7_JITTER + Clkout7 Jitter + 0.0 + + + CLKOUT7_PHASE_ERROR + Clkout7 Phase + 0.0 + + + INPUT_MODE + frequency + + + INTERFACE_SELECTION + Enable_AXI + + + AXI_DRP + Write DRP registers + false + + + PHASE_DUTY_CONFIG + Phase Duty Cycle Config + false + + + + + Clocking Wizard + + XPM_CDC + + 3 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.1 + + + + + + + + diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc new file mode 100755 index 0000000..3422a8e --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc @@ -0,0 +1,2 @@ +#--------------------Physical Constraints----------------- + diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v new file mode 100755 index 0000000..d108906 --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v @@ -0,0 +1,198 @@ + +// file: clk_wiz_0.v +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1____65.000______0.000______50.0______254.866____297.890 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________100.000____________0.010 + +`timescale 1ps/1ps + +module clk_wiz_0_clk_wiz + + (// Clock in ports + // Clock out ports + output clk_out1, + input clk_in1 + ); + // Input buffering + //------------------------------------ +wire clk_in1_clk_wiz_0; +wire clk_in2_clk_wiz_0; + IBUF clkin1_ibufg + (.O (clk_in1_clk_wiz_0), + .I (clk_in1)); + + + + + // Clocking PRIMITIVE + //------------------------------------ + + // Instantiation of the MMCM PRIMITIVE + // * Unused inputs are tied off + // * Unused outputs are labeled unused + + wire clk_out1_clk_wiz_0; + wire clk_out2_clk_wiz_0; + wire clk_out3_clk_wiz_0; + wire clk_out4_clk_wiz_0; + wire clk_out5_clk_wiz_0; + wire clk_out6_clk_wiz_0; + wire clk_out7_clk_wiz_0; + + wire [15:0] do_unused; + wire drdy_unused; + wire psdone_unused; + wire locked_int; + wire clkfbout_clk_wiz_0; + wire clkfbout_buf_clk_wiz_0; + wire clkfboutb_unused; + wire clkout0b_unused; + wire clkout1_unused; + wire clkout1b_unused; + wire clkout2_unused; + wire clkout2b_unused; + wire clkout3_unused; + wire clkout3b_unused; + wire clkout4_unused; + wire clkout5_unused; + wire clkout6_unused; + wire clkfbstopped_unused; + wire clkinstopped_unused; + + MMCME2_ADV + #(.BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (5), + .CLKFBOUT_MULT_F (50.375), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (15.500), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (10.000)) + mmcm_adv_inst + // Output clocks + ( + .CLKFBOUT (clkfbout_clk_wiz_0), + .CLKFBOUTB (clkfboutb_unused), + .CLKOUT0 (clk_out1_clk_wiz_0), + .CLKOUT0B (clkout0b_unused), + .CLKOUT1 (clkout1_unused), + .CLKOUT1B (clkout1b_unused), + .CLKOUT2 (clkout2_unused), + .CLKOUT2B (clkout2b_unused), + .CLKOUT3 (clkout3_unused), + .CLKOUT3B (clkout3b_unused), + .CLKOUT4 (clkout4_unused), + .CLKOUT5 (clkout5_unused), + .CLKOUT6 (clkout6_unused), + // Input clock control + .CLKFBIN (clkfbout_buf_clk_wiz_0), + .CLKIN1 (clk_in1_clk_wiz_0), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (do_unused), + .DRDY (drdy_unused), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (psdone_unused), + // Other control and status signals + .LOCKED (locked_int), + .CLKINSTOPPED (clkinstopped_unused), + .CLKFBSTOPPED (clkfbstopped_unused), + .PWRDWN (1'b0), + .RST (1'b0)); + +// Clock Monitor clock assigning +//-------------------------------------- + // Output buffering + //----------------------------------- + + BUFG clkf_buf + (.O (clkfbout_buf_clk_wiz_0), + .I (clkfbout_clk_wiz_0)); + + + + + + + BUFG clkout1_buf + (.O (clk_out1), + .I (clk_out1_clk_wiz_0)); + + + + +endmodule diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc new file mode 100755 index 0000000..9305712 --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc @@ -0,0 +1,58 @@ + +# file: clk_wiz_0_ooc.xdc +# +# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +################# +#DEFAULT CLOCK CONSTRAINTS + +############################################################ +# Clock Period Constraints # +############################################################ +#create_clock -period 10.000 [get_ports clk_in1] + diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v new file mode 100755 index 0000000..658b9d9 --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v @@ -0,0 +1,232 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed Oct 4 16:31:39 2023 +// Host : WIN10-TP running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v +// Design : clk_wiz_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7a35tcpg236-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module clk_wiz_0 + (clk_out1, + clk_in1); + output clk_out1; + input clk_in1; + + (* IBUF_LOW_PWR *) wire clk_in1; + wire clk_out1; + + clk_wiz_0_clk_wiz_0_clk_wiz inst + (.clk_in1(clk_in1), + .clk_out1(clk_out1)); +endmodule + +(* ORIG_REF_NAME = "clk_wiz_0_clk_wiz" *) +module clk_wiz_0_clk_wiz_0_clk_wiz + (clk_out1, + clk_in1); + output clk_out1; + input clk_in1; + + wire clk_in1; + wire clk_in1_clk_wiz_0; + wire clk_out1; + wire clk_out1_clk_wiz_0; + wire clkfbout_buf_clk_wiz_0; + wire clkfbout_clk_wiz_0; + wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED; + wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED; + wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED; + wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED; + wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkf_buf + (.I(clkfbout_clk_wiz_0), + .O(clkfbout_buf_clk_wiz_0)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF #( + .IOSTANDARD("DEFAULT")) + clkin1_ibufg + (.I(clk_in1), + .O(clk_in1_clk_wiz_0)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkout1_buf + (.I(clk_out1_clk_wiz_0), + .O(clk_out1)); + (* BOX_TYPE = "PRIMITIVE" *) + MMCME2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT_F(50.375000), + .CLKFBOUT_PHASE(0.000000), + .CLKFBOUT_USE_FINE_PS("FALSE"), + .CLKIN1_PERIOD(10.000000), + .CLKIN2_PERIOD(0.000000), + .CLKOUT0_DIVIDE_F(15.500000), + .CLKOUT0_DUTY_CYCLE(0.500000), + .CLKOUT0_PHASE(0.000000), + .CLKOUT0_USE_FINE_PS("FALSE"), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.500000), + .CLKOUT1_PHASE(0.000000), + .CLKOUT1_USE_FINE_PS("FALSE"), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.500000), + .CLKOUT2_PHASE(0.000000), + .CLKOUT2_USE_FINE_PS("FALSE"), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.500000), + .CLKOUT3_PHASE(0.000000), + .CLKOUT3_USE_FINE_PS("FALSE"), + .CLKOUT4_CASCADE("FALSE"), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.500000), + .CLKOUT4_PHASE(0.000000), + .CLKOUT4_USE_FINE_PS("FALSE"), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.500000), + .CLKOUT5_PHASE(0.000000), + .CLKOUT5_USE_FINE_PS("FALSE"), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.500000), + .CLKOUT6_PHASE(0.000000), + .CLKOUT6_USE_FINE_PS("FALSE"), + .COMPENSATION("ZHOLD"), + .DIVCLK_DIVIDE(5), + .IS_CLKINSEL_INVERTED(1'b0), + .IS_PSEN_INVERTED(1'b0), + .IS_PSINCDEC_INVERTED(1'b0), + .IS_PWRDWN_INVERTED(1'b0), + .IS_RST_INVERTED(1'b0), + .REF_JITTER1(0.010000), + .REF_JITTER2(0.010000), + .SS_EN("FALSE"), + .SS_MODE("CENTER_HIGH"), + .SS_MOD_PERIOD(10000), + .STARTUP_WAIT("FALSE")) + mmcm_adv_inst + (.CLKFBIN(clkfbout_buf_clk_wiz_0), + .CLKFBOUT(clkfbout_clk_wiz_0), + .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED), + .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED), + .CLKIN1(clk_in1_clk_wiz_0), + .CLKIN2(1'b0), + .CLKINSEL(1'b1), + .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), + .CLKOUT0(clk_out1_clk_wiz_0), + .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), + .CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED), + .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), + .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED), + .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), + .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED), + .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED), + .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED), + .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED), + .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED), + .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DCLK(1'b0), + .DEN(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]), + .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED), + .DWE(1'b0), + .LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED), + .PSCLK(1'b0), + .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .PWRDWN(1'b0), + .RST(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl new file mode 100755 index 0000000..dfa0d90 --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl @@ -0,0 +1,185 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed Oct 4 16:31:39 2023 +-- Host : WIN10-TP running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl +-- Design : clk_wiz_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7a35tcpg236-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity clk_wiz_0_clk_wiz_0_clk_wiz is + port ( + clk_out1 : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of clk_wiz_0_clk_wiz_0_clk_wiz : entity is "clk_wiz_0_clk_wiz"; +end clk_wiz_0_clk_wiz_0_clk_wiz; + +architecture STRUCTURE of clk_wiz_0_clk_wiz_0_clk_wiz is + signal clk_in1_clk_wiz_0 : STD_LOGIC; + signal clk_out1_clk_wiz_0 : STD_LOGIC; + signal clkfbout_buf_clk_wiz_0 : STD_LOGIC; + signal clkfbout_clk_wiz_0 : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; + attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; +begin +clkf_buf: unisim.vcomponents.BUFG + port map ( + I => clkfbout_clk_wiz_0, + O => clkfbout_buf_clk_wiz_0 + ); +clkin1_ibufg: unisim.vcomponents.IBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => clk_in1, + O => clk_in1_clk_wiz_0 + ); +clkout1_buf: unisim.vcomponents.BUFG + port map ( + I => clk_out1_clk_wiz_0, + O => clk_out1 + ); +mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV + generic map( + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT_F => 50.375000, + CLKFBOUT_PHASE => 0.000000, + CLKFBOUT_USE_FINE_PS => false, + CLKIN1_PERIOD => 10.000000, + CLKIN2_PERIOD => 0.000000, + CLKOUT0_DIVIDE_F => 15.500000, + CLKOUT0_DUTY_CYCLE => 0.500000, + CLKOUT0_PHASE => 0.000000, + CLKOUT0_USE_FINE_PS => false, + CLKOUT1_DIVIDE => 1, + CLKOUT1_DUTY_CYCLE => 0.500000, + CLKOUT1_PHASE => 0.000000, + CLKOUT1_USE_FINE_PS => false, + CLKOUT2_DIVIDE => 1, + CLKOUT2_DUTY_CYCLE => 0.500000, + CLKOUT2_PHASE => 0.000000, + CLKOUT2_USE_FINE_PS => false, + CLKOUT3_DIVIDE => 1, + CLKOUT3_DUTY_CYCLE => 0.500000, + CLKOUT3_PHASE => 0.000000, + CLKOUT3_USE_FINE_PS => false, + CLKOUT4_CASCADE => false, + CLKOUT4_DIVIDE => 1, + CLKOUT4_DUTY_CYCLE => 0.500000, + CLKOUT4_PHASE => 0.000000, + CLKOUT4_USE_FINE_PS => false, + CLKOUT5_DIVIDE => 1, + CLKOUT5_DUTY_CYCLE => 0.500000, + CLKOUT5_PHASE => 0.000000, + CLKOUT5_USE_FINE_PS => false, + CLKOUT6_DIVIDE => 1, + CLKOUT6_DUTY_CYCLE => 0.500000, + CLKOUT6_PHASE => 0.000000, + CLKOUT6_USE_FINE_PS => false, + COMPENSATION => "ZHOLD", + DIVCLK_DIVIDE => 5, + IS_CLKINSEL_INVERTED => '0', + IS_PSEN_INVERTED => '0', + IS_PSINCDEC_INVERTED => '0', + IS_PWRDWN_INVERTED => '0', + IS_RST_INVERTED => '0', + REF_JITTER1 => 0.010000, + REF_JITTER2 => 0.010000, + SS_EN => "FALSE", + SS_MODE => "CENTER_HIGH", + SS_MOD_PERIOD => 10000, + STARTUP_WAIT => false + ) + port map ( + CLKFBIN => clkfbout_buf_clk_wiz_0, + CLKFBOUT => clkfbout_clk_wiz_0, + CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, + CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, + CLKIN1 => clk_in1_clk_wiz_0, + CLKIN2 => '0', + CLKINSEL => '1', + CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, + CLKOUT0 => clk_out1_clk_wiz_0, + CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, + CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, + CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, + CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, + CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, + CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, + CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, + CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, + CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, + CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, + DADDR(6 downto 0) => B"0000000", + DCLK => '0', + DEN => '0', + DI(15 downto 0) => B"0000000000000000", + DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), + DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, + DWE => '0', + LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED, + PSCLK => '0', + PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, + PSEN => '0', + PSINCDEC => '0', + PWRDWN => '0', + RST => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity clk_wiz_0 is + port ( + clk_out1 : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of clk_wiz_0 : entity is true; +end clk_wiz_0; + +architecture STRUCTURE of clk_wiz_0 is +begin +inst: entity work.clk_wiz_0_clk_wiz_0_clk_wiz + port map ( + clk_in1 => clk_in1, + clk_out1 => clk_out1 + ); +end STRUCTURE; diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v new file mode 100755 index 0000000..626c381 --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -0,0 +1,20 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Wed Oct 4 16:31:39 2023 +// Host : WIN10-TP running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +// Design : clk_wiz_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7a35tcpg236-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module clk_wiz_0(clk_out1, clk_in1) +/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_in1" */; + output clk_out1; + input clk_in1; +endmodule diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl new file mode 100755 index 0000000..7166d8c --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -0,0 +1,29 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Wed Oct 4 16:31:39 2023 +-- Host : WIN10-TP running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub +-- c:/Users/profil/Desktop/SeanceTP2_VHDL/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +-- Design : clk_wiz_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7a35tcpg236-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_wiz_0 is + Port ( + clk_out1 : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + +end clk_wiz_0; + +architecture stub of clk_wiz_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_in1"; +begin +end; diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt new file mode 100755 index 0000000..7cc5208 --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt @@ -0,0 +1,194 @@ +2019.1: + * Version 6.0 (Rev. 3) + * Bug Fix: Internal GUI fixes + * Other: New family support added + +2018.3.1: + * Version 6.0 (Rev. 2) + * No changes + +2018.3: + * Version 6.0 (Rev. 2) + * Bug Fix: Made input source independent for primary and secondary clock + * Other: New family support added + +2018.2: + * Version 6.0 (Rev. 1) + * Bug Fix: Removed vco freq check when Primitive is None + * Other: New family support added + +2018.1: + * Version 6.0 + * Bug Fix: Bug fixes in Dynamic Reconfiguration feature and Write DRP feature + * Bug Fix: Bug fixes for connection issue for s_axi_aresetn pin in IPI + * Feature Enhancement: The default value of USE_PHASE_ALIGMENT is updated to false for UltraScale and UltraScale+ devices. Phase Alignment feature uses extra clock routes in UltraScale and UltraScale+ designs when MMCMs are used. These routing resources are wasted when user do not understand when phase alignment is really needed. Now, implementation tools can use these extra clock routing resources for high fanout signals. + * Feature Enhancement: A column "Max. freq of buffer" is added in the Output Clock table which shows the maximum frequency that the selected output buffer can support + * Other: DRCs added for invalid input values in Override mode + +2017.4: + * Version 5.4 (Rev. 3) + * Bug Fix: Internal GUI issues are fixed for COMPENSATION mode as INTERNAL + * Bug Fix: Fixed issue in dynamic reconfiguration of fractional values of M in MMCME3, MMCME4 + +2017.3: + * Version 5.4 (Rev. 2) + * General: Internal GUI changes. No effect on the customer design. Added support for aspartan7 devices + +2017.2: + * Version 5.4 (Rev. 1) + * General: Internal GUI changes. No effect on the customer design. + +2017.1: + * Version 5.4 + * Port Change: Minor version upgrade. CLR pins are added to the pin list when selected buffer is BUFGCEDIV for ultrascale and ultrascale plus devices. + * Other: Added support for new zynq ultrascale plus devices. + +2016.4: + * Version 5.3 (Rev. 3) + * Bug Fix: Internal GUI issues are fixed. + +2016.3: + * Version 5.3 (Rev. 2) + * Feature Enhancement: Added new option "Auto" under PRIMITIVE selection for ultrascale and above devices. This option allows the Wizard to instantiate appropriate primitive for the user inputs. + * Feature Enhancement: Added Matched Routing Option for better timing solutions. + * Feature Enhancement: Options 'Buffer' and 'Buffer_with_CE' are added to the buffer selection list. + * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user + * Other: Added support for Spartan7 devices. + +2016.2: + * Version 5.3 (Rev. 1) + * Internal register bit update, no effect on customer designs. + +2016.1: + * Version 5.3 + * Added Clock Monitor Feature as part of clocking wizard + * DRP registers can be directly written through AXI without resource utilization + * Changes to HDL library management to support Vivado IP simulation library + +2015.4.2: + * Version 5.2 (Rev. 1) + * No changes + +2015.4.1: + * Version 5.2 (Rev. 1) + * No changes + +2015.4: + * Version 5.2 (Rev. 1) + * Internal device family change, no functional changes + +2015.3: + * Version 5.2 + * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances + * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported + * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature + * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format + * Example design and simulation files are delivered in verilog only + +2015.2.1: + * Version 5.1 (Rev. 6) + * No changes + +2015.2: + * Version 5.1 (Rev. 6) + * No changes + +2015.1: + * Version 5.1 (Rev. 6) + * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices + * Supported devices and production status are now determined automatically, to simplify support for future devices + +2014.4.1: + * Version 5.1 (Rev. 5) + * No changes + +2014.4: + * Version 5.1 (Rev. 5) + * Internal device family change, no functional changes + * updates related to the source selection based on board interface for zed board + +2014.3: + * Version 5.1 (Rev. 4) + * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface + +2014.2: + * Version 5.1 (Rev. 3) + * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065 + +2014.1: + * Version 5.1 (Rev. 2) + * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock + * Internal device family name change, no functional changes + +2013.4: + * Version 5.1 (Rev. 1) + * Added support for Ultrascale devices + * Updated Board Flow GUI to select the clock interfaces + * Fixed issue with Stub file parameter error for BUFR output driver + +2013.3: + * Version 5.1 + * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL + * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies + * Fixed precision issues between displayed and actual frequencies + * Added tool tips to GUI + * Added Jitter and Phase error values to IP properties + * Added support for Cadence IES and Synopsys VCS simulators + * Reduced warnings in synthesis and simulation + * Enhanced support for IP Integrator + +2013.2: + * Version 5.0 (Rev. 1) + * Fixed issue with clock constraints for multiple instances of clocking wizard + * Updated Life-Cycle status of devices + +2013.1: + * Version 5.0 + * Lower case ports for Verilog + * Added Safe Clock Startup and Clock Sequencing + +(c) Copyright 2008 - 2019 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh new file mode 100755 index 0000000..481cd2d --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh @@ -0,0 +1,671 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing +// Date: 7/30/2014 +// Design Name: MMCME2 DRP +// Module Name: mmcme2_drp_func.h +// Version: 1.04 +// Target Devices: 7 Series || MMCM +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 MMCM. +// +// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1011_00, + 10'b0010_1101_00, + 10'b0010_0011_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0100_1111_00, + 10'b0101_1011_00, + 10'b0111_0111_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_1001_00, + 10'b1101_0001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0111_0001_00, + 10'b0111_0001_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0110_0001_00, + 10'b0110_0001_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0100_1010_00, + 10'b0011_1100_00, + 10'b0011_1100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh new file mode 100755 index 0000000..d34dbe7 --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh @@ -0,0 +1,531 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing +// Date: 7/30/2014 +// Design Name: PLLE2 DRP +// Module Name: plle2_drp_func.h +// Version: 2.00 +// Target Devices: 7 Series || PLL +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// Updated for CR663854. +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + +`ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); +`endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end +`ifdef DEBUG + $display("round_frac: %h", round_frac); +`endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + +`ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); +`endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + +`ifdef DEBUG + $display("temp: %h", temp); +`endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1101_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0011_0111_00, + 10'b0011_0111_00, + 10'b0101_1111_00, + 10'b0111_1111_00, + 10'b0111_1011_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_1101_00, + 10'b1111_0111_00, + 10'b1111_1011_00, + 10'b1111_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); +`endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + +`ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); +`endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh new file mode 100755 index 0000000..811d433 --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh @@ -0,0 +1,671 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa +// Date: 7/30/2014 +// Design Name: MMCME2 DRP +// Module Name: mmcme2_drp_func.h +// Version: 1.04 +// Target Devices: UltraScale Architecture || MMCM +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 MMCM. +// +// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_0011_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_1001_11, + 10'b0010_1001_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1011_11, + 10'b0011_1111_11, + 10'b0100_1111_11, + 10'b0100_1111_11, + 10'b0101_1111_11, + 10'b0110_1111_11, + 10'b0111_1111_11, + 10'b0111_1111_11, + 10'b1100_1111_11, + 10'b1101_1111_11, + 10'b1110_1111_11, + 10'b1111_1111_11, + 10'b1111_1111_11, + 10'b1110_0111_11, + 10'b1110_1011_11, + 10'b1111_0111_11, + 10'b1111_1011_11, + 10'b1111_1011_11, + 10'b1110_1101_11, + 10'b1111_1101_11, + 10'b1111_1101_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh new file mode 100755 index 0000000..9439f23 --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh @@ -0,0 +1,530 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa +// Date: 6/15/2015 +// Design Name: PLLE3 DRP +// Module Name: plle3_drp_func.h +// Version: 1.10 +// Target Devices: UltraScale Architecture +// Tool versions: 2015.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// +// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 +// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 +// PM_Rise bits have been removed for PLLE3 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [759:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, //1 + 40'b00110_00110_1111101000_1111101001_0000000001, //2 + 40'b01000_01000_1111101000_1111101001_0000000001, //3 + 40'b01011_01011_1111101000_1111101001_0000000001, //4 + 40'b01110_01110_1111101000_1111101001_0000000001, //5 + 40'b10001_10001_1111101000_1111101001_0000000001, //6 + 40'b10011_10011_1111101000_1111101001_0000000001, //7 + 40'b10110_10110_1111101000_1111101001_0000000001, //8 + 40'b11001_11001_1111101000_1111101001_0000000001, //9 + 40'b11100_11100_1111101000_1111101001_0000000001, //10 + 40'b11111_11111_1110000100_1111101001_0000000001, //11 + 40'b11111_11111_1100111001_1111101001_0000000001, //12 + 40'b11111_11111_1011101110_1111101001_0000000001, //13 + 40'b11111_11111_1010111100_1111101001_0000000001, //14 + 40'b11111_11111_1010001010_1111101001_0000000001, //15 + 40'b11111_11111_1001110001_1111101001_0000000001, //16 + 40'b11111_11111_1000111111_1111101001_0000000001, //17 + 40'b11111_11111_1000100110_1111101001_0000000001, //18 + 40'b11111_11111_1000001101_1111101001_0000000001 //19 + + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide // Max divide is 19 + ); + + reg [639:0] lookup; + reg [9:0] lookup_entry; + + begin + + lookup = { + // CP_RES_LFHF + 10'b0010_1111_01, //1 + 10'b0010_0011_11, //2 + 10'b0011_0011_11, //3 + 10'b0010_0001_11, //4 + 10'b0010_0110_11, //5 + 10'b0010_1010_11, //6 + 10'b0010_1010_11, //7 + 10'b0011_0110_11, //8 + 10'b0010_1100_11, //9 + 10'b0010_1100_11, //10 + 10'b0010_1100_11, //11 + 10'b0010_0010_11, //12 + 10'b0011_1100_11, //13 + 10'b0011_1100_11, //14 + 10'b0011_1100_11, //15 + 10'b0011_1100_11, //16 + 10'b0011_0010_11, //17 + 10'b0011_0010_11, //18 + 10'b0011_0010_11 //19 + }; + + mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10]; + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function set the CLKOUTPHY divide settings to match +// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then +// the CLKOUTPHY will be set to 2'b00 since the VCO is internally +// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10 +function [9:0] mmcm_pll_clkoutphy_calc + ( + input [8*9:0] CLKOUTPHY_MODE + ); + + if(CLKOUTPHY_MODE == "VCO_X2") begin + mmcm_pll_clkoutphy_calc= 2'b00; + end else if(CLKOUTPHY_MODE == "VCO") begin + mmcm_pll_clkoutphy_calc= 2'b01; + end else if(CLKOUTPHY_MODE == "CLKIN") begin + mmcm_pll_clkoutphy_calc= 2'b11; + end else begin // Assume "VCO_HALF" + mmcm_pll_clkoutphy_calc= 2'b10; + end + +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_pll_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_pll_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits +// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); + `endif + + end +endfunction + + diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh new file mode 100755 index 0000000..ebf87be --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh @@ -0,0 +1,861 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa. Updated by Ralf Krueger +// Date: 7/30/2014 +// Design Name: MMCME4 DRP +// Module Name: mmcme4_drp_func.h +// Version: 1.31 +// Target Devices: UltraScale Plus Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for UltraScal+ MMCM. +// +// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function +// 2/28/17 - Updated for Ultrascale Plus +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2017 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages during elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_phase-divide:%d,phase:%d", divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [7:0] divide // Max M divide is 128 in UltrascalePlus + ); + + reg [5119:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed) + 40'b00110_00110_1111101000_1111101001_0000000001, // M=2 + 40'b01000_01000_1111101000_1111101001_0000000001, // M=3 + 40'b01011_01011_1111101000_1111101001_0000000001, // M=4 + 40'b01110_01110_1111101000_1111101001_0000000001, // M=5 + 40'b10001_10001_1111101000_1111101001_0000000001, // M=6 + 40'b10011_10011_1111101000_1111101001_0000000001, // M=7 + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, // M=127 + 40'b11111_11111_0011111010_1111101001_0000000001 // M=128 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus + input [8*9:0] BANDWIDTH + ); + + reg [1279:0] lookup_low; + reg [1279:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0011_1111_11, // M=1 - not legal + 10'b0011_1111_11, // M=2 + 10'b0011_1101_11, // M=3 + 10'b0011_0101_11, // M=4 + 10'b0011_1001_11, // M=5 + 10'b0011_1110_11, // M=6 + 10'b0011_1110_11, // M=7 + 10'b0011_0001_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0100_0110_11, + 10'b0011_1100_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, // M=127 + 10'b1101_1000_11 // M=128 +}; + + lookup_high = { + // CP_RES_LFHF + 10'b0111_1111_11, // M=1 - not legal + 10'b0111_1111_11, // M=2 + 10'b1110_1111_11, // M=3 + 10'b1111_1111_11, // M=4 + 10'b1111_1011_11, // M=5 + 10'b1111_1101_11, // M=6 + 10'b1111_0011_11, // M=7 + 10'b1110_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1110_0110_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11 // M=128 +}; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh new file mode 100755 index 0000000..1d2dc69 --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh @@ -0,0 +1,536 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+ +// Date: 6/15/2015 +// Design Name: PLLE4 DRP +// Module Name: plle4_drp_func.h +// Version: 2.0 +// Target Devices: UltraScale+ Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// +// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 +// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 +// M_Rise bits have been removed for PLLE3 +// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for +// Ultrascale+ and for max M of 21 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2017 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); +`endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 21 + ); + + reg [839:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+ + 40'b00110_00110_1111101000_1111101001_0000000001, //2 + 40'b01000_01000_1111101000_1111101001_0000000001, //3 + 40'b01011_01011_1111101000_1111101001_0000000001, //4 + 40'b01110_01110_1111101000_1111101001_0000000001, //5 + 40'b10001_10001_1111101000_1111101001_0000000001, //6 + 40'b10011_10011_1111101000_1111101001_0000000001, //7 + 40'b10110_10110_1111101000_1111101001_0000000001, //8 + 40'b11001_11001_1111101000_1111101001_0000000001, //9 + 40'b11100_11100_1111101000_1111101001_0000000001, //10 + 40'b11111_11111_1110000100_1111101001_0000000001, //11 + 40'b11111_11111_1100111001_1111101001_0000000001, //12 + 40'b11111_11111_1011101110_1111101001_0000000001, //13 + 40'b11111_11111_1010111100_1111101001_0000000001, //14 + 40'b11111_11111_1010001010_1111101001_0000000001, //15 + 40'b11111_11111_1001110001_1111101001_0000000001, //16 + 40'b11111_11111_1000111111_1111101001_0000000001, //17 + 40'b11111_11111_1000100110_1111101001_0000000001, //18 + 40'b11111_11111_1000001101_1111101001_0000000001, //19 + 40'b11111_11111_0111110100_1111101001_0000000001, //20 + 40'b11111_11111_0111011011_1111101001_0000000001 //21 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide // Max divide is 21 + ); + + reg [209:0] lookup; + reg [9:0] lookup_entry; + + begin + + lookup = { + // CP_RES_LFHF + 10'b0011_0111_11, //1 not legal in Ultrascale+ + 10'b0011_0111_11, //2 + 10'b0011_0011_11, //3 + 10'b0011_1001_11, //4 + 10'b0011_0001_11, //5 + 10'b0100_1110_11, //6 + 10'b0011_0110_11, //7 + 10'b0011_1010_11, //8 + 10'b0111_1001_11, //9 + 10'b0111_1001_11, //10 + 10'b0101_0110_11, //11 + 10'b1100_0101_11, //12 + 10'b0101_1010_11, //13 + 10'b0110_0110_11, //14 + 10'b0110_1010_11, //15 + 10'b0111_0110_11, //16 + 10'b1111_0101_11, //17 + 10'b1100_0110_11, //18 + 10'b1110_0001_11, //19 + 10'b1101_0110_11, //20 + 10'b1111_0001_11 //21 + }; + + mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10]; + + `ifdef DEBUG + $display("filter_lookup: %b", pll_filter_lookup); + `endif + end +endfunction + +// This function set the CLKOUTPHY divide settings to match +// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then +// the CLKOUTPHY will be set to 2'b00 since the VCO is internally +// doubled and 2'b00 will represent divide by 1. Similarly "VCO" +// will need to divide the doubled clock VCO clock frequency by +// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will +// need to divide the doubled VCO by 4, therefore 2'b10 +function [9:0] mmcm_pll_clkoutphy_calc + ( + input [8*9:0] CLKOUTPHY_MODE + ); + + if(CLKOUTPHY_MODE == "VCO_X2") begin + mmcm_pll_clkoutphy_calc= 2'b00; + end else if(CLKOUTPHY_MODE == "VCO") begin + mmcm_pll_clkoutphy_calc= 2'b01; + end else if(CLKOUTPHY_MODE == "CLKIN") begin + mmcm_pll_clkoutphy_calc= 2'b11; + end else begin // Assume "VCO_HALF" + mmcm_pll_clkoutphy_calc= 2'b10; + end + +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_pll_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_pll_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/TP_VGA/TP_VGA.srcs/sources_1/new/VGA_vhdl.v b/TP_VGA/TP_VGA.srcs/sources_1/new/VGA_vhdl.v new file mode 100755 index 0000000..df9d8e3 --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/new/VGA_vhdl.v @@ -0,0 +1,30 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 04.10.2023 16:23:46 +// Design Name: +// Module Name: VGA_vhdl +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module VGA_vhdl( + input Clk_sys, + input Reset, + input B1, + input B2, + input B3 + ); +endmodule diff --git a/TP_VGA/TP_VGA.srcs/sources_1/new/VGA_vhdl.vhd b/TP_VGA/TP_VGA.srcs/sources_1/new/VGA_vhdl.vhd new file mode 100755 index 0000000..67aed8a --- /dev/null +++ b/TP_VGA/TP_VGA.srcs/sources_1/new/VGA_vhdl.vhd @@ -0,0 +1,115 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04.10.2023 16:25:02 +-- Design Name: +-- Module Name: VGA_vhdl - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity VGA_vhdl is + Port ( Clk_sys : in STD_LOGIC; + b1 : in STD_LOGIC; + b2 : in STD_LOGIC; + b3 : in STD_LOGIC; + Reset : in STD_LOGIC; + HS : out std_logic; + HV : out std_logic; + R : out std_logic_vector(3 downto 0); + G : out std_logic_vector(3 downto 0); + B : out std_logic_vector(3 downto 0) + ); +end VGA_vhdl; + +architecture Behavioral of VGA_vhdl is + +signal pixel_clk : std_logic := '0'; +signal CompteurHS: std_logic_vector(11 downto 0); -- Generation du signal VH +signal CompteurVS: std_logic_vector(9 downto 0); +------------------- +-- CLOCK 65 MHZ -- +------------------- +component clk_wiz_0 +port + (-- Clock in ports + -- Clock out ports + clk_out1 : out std_logic; + clk_in1 : in std_logic + ); +end component; + +begin +---------- +-- Compteur Horizental -- +------------ +Compteur_HS: process(pixel_clk) +begin + if rising_edge(pixel_clk) then + if CompteurHS < 1344 then + CompteurHS <= CompteurHS +1; + HS <= '1'; + if CompteurHS = 1048 then + HS <= '0'; + elsif CompteurHS = 1184 then + HS <= '1'; + end if; + else CompteurHS <= (others => '0'); + end if; + end if; +end process; +---------- +-- Compteur Vertical -- +------------ +Compteur_VS: process(pixel_clk) +begin + if rising_edge(pixel_clk) then + if CompteurVS < 806 then + CompteurHS <= CompteurHS +1; + HS <= '1'; + if CompteurVS = 771 then + HS <= '0'; + elsif CompteurVS = 777 then + HS <= '1'; + end if; + else CompteurVS <= (others => '0'); + end if; + end if; +end process; +------------ + +your_instance_name : clk_wiz_0 + port map ( + -- Clock out ports + clk_out1 => pixel_clk, + -- Clock in ports + clk_in1 => Clk_sys + ); + ---------------- + + +end Behavioral; diff --git a/TP_VGA/TP_VGA.xpr b/TP_VGA/TP_VGA.xpr new file mode 100755 index 0000000..e37133b --- /dev/null +++ b/TP_VGA/TP_VGA.xpr @@ -0,0 +1,254 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- libgit2 0.21.2