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7Segment_display readme
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7Segment_display/README.md
... | ... | @@ -117,7 +117,44 @@ end display; |
117 | 117 | - seg* : attribue chaque segment à une valeur constante. |
118 | 118 | - chiffre* : variable représentant le chiffre en * position |
119 | 119 | - numbers : associe la représentation logique d'un chiffre à un entier. |
120 | - | |
120 | + | |
121 | + | |
122 | + Les process | |
123 | + | |
124 | + 1er process : | |
125 | + | |
126 | + ``` | |
127 | + begin | |
128 | + | |
129 | + -- process d'affichage | |
130 | + process(clk_fpga) | |
131 | + begin | |
132 | + if clk_fpga'event and clk_fpga = '1' then | |
133 | + if clk_enable = 4999 then | |
134 | + clk_enable <= 0; | |
135 | + if count_an = 0 then | |
136 | + aff <= numbers(chiffre4); | |
137 | + an <= seg0; | |
138 | + count_an <= count_an + 1; | |
139 | + elsif count_an = 1 then | |
140 | + aff <= numbers(chiffre3); | |
141 | + an <= seg1; | |
142 | + count_an <= count_an + 1; | |
143 | + elsif count_an = 2 then | |
144 | + aff <= numbers(chiffre2); | |
145 | + an <= seg2; | |
146 | + count_an <= count_an + 1; | |
147 | + elsif count_an = 3 then | |
148 | + aff <= numbers(chiffre1); | |
149 | + an <= seg3; | |
150 | + count_an <= 0; | |
151 | + end if; | |
152 | + else | |
153 | + clk_enable <= clk_enable + 1; | |
154 | + end if; | |
155 | + end if; | |
156 | + end process; | |
157 | + ``` | |
121 | 158 | ## Résultats |
122 | 159 | |
123 | 160 | - Nous avons dans un premier temps essayer d'afficher sur les 4 afficheurs sans recouvrement. C'est pour cela qu'il a fallu baisser la clock. | ... | ... |
7Segment_display/display.vhd
... | ... | @@ -71,10 +71,10 @@ signal numbers : mynumbers := (nb9,nb8,nb7,nb6,nb5,nb4,nb3,nb2,nb1,nb0); |
71 | 71 | |
72 | 72 | begin |
73 | 73 | |
74 | +-- process d'affichage | |
74 | 75 | process(clk_fpga) |
75 | 76 | begin |
76 | 77 | if clk_fpga'event and clk_fpga = '1' then |
77 | - -- clock d'affichage | |
78 | 78 | if clk_enable = 4999 then |
79 | 79 | clk_enable <= 0; |
80 | 80 | if count_an = 0 then |
... | ... | @@ -96,8 +96,14 @@ begin |
96 | 96 | end if; |
97 | 97 | else |
98 | 98 | clk_enable <= clk_enable + 1; |
99 | - end if; | |
100 | - -- clock de compteur | |
99 | + end if; | |
100 | + end if; | |
101 | +end process; | |
102 | + | |
103 | +-- process counter | |
104 | +process(clk_fpga) | |
105 | +begin | |
106 | + if clk_fpga'event and clk_fpga = '1' then | |
101 | 107 | if clk_counter = 2999999 then |
102 | 108 | clk_counter <= 0; |
103 | 109 | if reset = '1' then | ... | ... |