From cdbcafa7c48d25326c802c970f46a54659c59bba Mon Sep 17 00:00:00 2001
From: rduhr <romain.duhr@polytech-lille.net>
Date: Tue, 31 Oct 2023 14:42:12 +0100
Subject: [PATCH] 7Segment_display readme

---
 7Segment_display/README.md   | 39 ++++++++++++++++++++++++++++++++++++++-
 7Segment_display/display.vhd | 12 +++++++++---
 2 files changed, 47 insertions(+), 4 deletions(-)

diff --git a/7Segment_display/README.md b/7Segment_display/README.md
index 4310835..3ed5dfc 100644
--- a/7Segment_display/README.md
+++ b/7Segment_display/README.md
@@ -117,7 +117,44 @@ end display;
    - seg* : attribue chaque segment à une valeur constante.
    - chiffre* : variable représentant le chiffre en * position
    - numbers : associe la représentation logique d'un chiffre à un entier.
-   
+
+
+   Les process
+
+   1er process : 
+
+   ```
+   begin
+
+   -- process d'affichage
+   process(clk_fpga)
+   begin
+      if clk_fpga'event and clk_fpga = '1' then
+         if clk_enable = 4999 then
+            clk_enable <= 0;
+            if count_an = 0 then
+               aff <= numbers(chiffre4); 
+               an <= seg0;
+               count_an <= count_an + 1;
+            elsif count_an = 1 then
+               aff <= numbers(chiffre3); 
+               an <= seg1;
+               count_an <= count_an + 1;
+            elsif count_an = 2 then
+                aff <= numbers(chiffre2);
+               an <= seg2;       
+               count_an <= count_an + 1;
+            elsif count_an = 3 then 
+                aff <= numbers(chiffre1);
+               an <= seg3;
+               count_an <= 0;
+            end if;
+         else
+            clk_enable <= clk_enable + 1;
+        end if;   
+      end if;    
+   end process; 
+   ```
 ## Résultats
 
 - Nous avons dans un premier temps essayer d'afficher sur les 4 afficheurs sans recouvrement. C'est pour cela qu'il a fallu baisser la clock.
diff --git a/7Segment_display/display.vhd b/7Segment_display/display.vhd
index 900e87b..450c2fb 100755
--- a/7Segment_display/display.vhd
+++ b/7Segment_display/display.vhd
@@ -71,10 +71,10 @@ signal numbers : mynumbers := (nb9,nb8,nb7,nb6,nb5,nb4,nb3,nb2,nb1,nb0);
 
 begin
 
+-- process d'affichage
 process(clk_fpga)
 begin
     if clk_fpga'event and clk_fpga = '1' then
-        -- clock d'affichage
         if clk_enable = 4999 then
             clk_enable <= 0;
             if count_an = 0 then
@@ -96,8 +96,14 @@ begin
             end if;
         else
             clk_enable <= clk_enable + 1;
-        end if;        
-        -- clock de compteur 
+        end if;   
+    end if;    
+end process; 
+
+-- process counter
+process(clk_fpga)
+begin
+    if clk_fpga'event and clk_fpga = '1' then
         if clk_counter = 2999999 then 
             clk_counter <= 0; 
             if reset = '1' then 
--
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