rduhr / TP-CN_rduhr_scruchet

Commit 4873ae75eb1ff630a2f173764122fbf8e1b22422

Authored by rduhr
1 parent 2424e7ea

vga Readme

Showing 1 changed file with 193 additions and 0 deletions   Show diff stats
Inline Side-by-side
Vga_display/vga_controller.vhd 0 → 100755
  Show/Hide comments   View file @4873ae7
@@ -0,0 +1,193 @@ @@ -0,0 +1,193 @@
  1 +----------------------------------------------------------------------------------
  2 +-- Company:
  3 +-- Engineer:
  4 +--
  5 +-- Create Date: 04.10.2023 10:40:26
  6 +-- Design Name:
  7 +-- Module Name: vga_controller - Behavioral
  8 +-- Project Name:
  9 +-- Target Devices:
  10 +-- Tool Versions:
  11 +-- Description:
  12 +--
  13 +-- Dependencies:
  14 +--
  15 +-- Revision:
  16 +-- Revision 0.01 - File Created
  17 +-- Additional Comments:
  18 +--
  19 +----------------------------------------------------------------------------------
  20 +
  21 +
  22 +library IEEE;
  23 +use IEEE.STD_LOGIC_1164.ALL;
  24 +use IEEE.STD_LOGIC_ARITH.ALL;
  25 +use IEEE.STD_LOGIC_UNSIGNED.ALL;
  26 +
  27 +-- Uncomment the following library declaration if using
  28 +-- arithmetic functions with Signed or Unsigned values
  29 +--use IEEE.NUMERIC_STD.ALL;
  30 +
  31 +-- Uncomment the following library declaration if instantiating
  32 +-- any Xilinx leaf cells in this code.
  33 +--library UNISIM;
  34 +--use UNISIM.VComponents.all;
  35 +
  36 +entity vga_controller is
  37 + Port (clk_fpga : in std_logic;
  38 + sw : in std_logic_vector(15 downto 0);
  39 + vgaRed : out std_logic_vector(3 downto 0);
  40 + vgaGreen : out std_logic_vector(3 downto 0);
  41 + vgaBlue : out std_logic_vector(3 downto 0);
  42 + Hsync : out std_logic;
  43 + Vsync : out std_logic);
  44 +end vga_controller;
  45 +
  46 +architecture Behavioral of vga_controller is
  47 +
  48 +component clk_wiz_0
  49 + port (clk_out1 : out std_logic;
  50 + clk_in1 : in std_logic);
  51 +end component;
  52 +
  53 +signal clk_65MHz : std_logic;
  54 +signal Hcount : integer range 1344 downto 1 := 1;
  55 +signal Vcount : integer range 1083264 downto 1 := 1;
  56 +signal myRed: std_logic_vector(3 downto 0);
  57 +signal myBlue: std_logic_vector(3 downto 0);
  58 +signal myGreen: std_logic_vector(3 downto 0);
  59 +
  60 +signal leftLimit: integer range 1025 downto 0:= 0;
  61 +signal rightLimit: integer range 1025 downto 0:= 100;
  62 +signal upLimit: integer range 768 downto 0:= 0;
  63 +signal downLimit: integer range 768 downto 0:= 100;
  64 +signal pixelX: integer range 1344 downto 1:= 1;
  65 +signal pixelY: integer range 768 downto 1;
  66 +
  67 +begin
  68 +
  69 +clk_65MHz_1 : clk_wiz_0 port map (clk_out1 => clk_65MHz,
  70 + clk_in1 => clk_fpga);
  71 +
  72 +myRed(0) <= sw(0);
  73 +myRed(1) <= sw(1);
  74 +myRed(2) <= sw(2);
  75 +myRed(3) <= sw(3);
  76 +myBlue(0) <= sw(4);
  77 +myBlue(1) <= sw(5);
  78 +myBlue(2) <= sw(6);
  79 +myBlue(3) <= sw(7);
  80 +myGreen(0) <= sw(8);
  81 +myGreen(1) <= sw(9);
  82 +myGreen(2) <= sw(10);
  83 +myGreen(3) <= sw(11);
  84 +
  85 +pixelX <= Hcount;
  86 +
  87 +process(clk_65MHz)
  88 +begin
  89 +if clk_65MHz'event and clk_65MHz = '1' then
  90 + if Vcount = 1032193 then
  91 + if rightLimit > 1024 and downLimit > 768 then
  92 + leftLimit <= 0;
  93 + rightLimit <= 100;
  94 + upLimit <= 0;
  95 + downLimit <= 100;
  96 + elsif rightLimit > 1024 then
  97 + leftLimit <= 0;
  98 + rightLimit <= 100;
  99 + upLimit <= upLimit + 1;
  100 + downLimit <= downLimit + 1;
  101 + else
  102 + leftLimit <= leftLimit + 1;
  103 + rightLimit <= rightLimit +1;
  104 + end if;
  105 + end if;
  106 +end if;
  107 +end process;
  108 +
  109 +process(clk_65MHz)
  110 +-- Simplification des valeurs d'écran
  111 +begin
  112 +if clk_65MHz'event and clk_65MHz = '1' then
  113 + if Vcount = 1 then
  114 + pixelY <= 1;
  115 + elsif Hcount = 1025 then
  116 + pixelY <= pixelY + 1;
  117 + end if;
  118 +end if;
  119 +end process;
  120 +
  121 +process(clk_65MHz)
  122 +-- Gestion de l'affichage
  123 +begin
  124 +if clk_65MHz'event and clk_65MHz = '1' then
  125 + if pixelX > leftLimit and pixelX < rightLimit and pixelY > upLimit and pixelY < downLimit then
  126 + -- Carré
  127 + vgaRed <= myRed;
  128 + vgaBlue <= myBlue;
  129 + vgaGreen <= myGreen;
  130 + elsif Hcount < 1025 and pixelY < 769 then
  131 + -- Background
  132 + vgaRed <= (others => '1');
  133 + vgaBlue <= (others => '1');
  134 + vgaGreen <= (others => '1');
  135 + else
  136 + -- Hors pixel
  137 + vgaRed <= (others => '0');
  138 + vgaBlue <= (others => '0');
  139 + vgaGreen <= (others => '0');
  140 + end if;
  141 +end if;
  142 +end process;
  143 +
  144 +process(clk_65MHz)
  145 +begin
  146 +if clk_65MHz'event and clk_65MHz = '1' then
  147 +
  148 +-- Gestion du vga
  149 +
  150 + -- Syncro horizontale
  151 + if Hcount < 1025 then
  152 + -- affichage
  153 + Hsync <= '1';
  154 + Hcount <= Hcount + 1;
  155 + elsif Hcount < 1049 then
  156 + -- Fp
  157 + Hsync <= '1';
  158 + Hcount <= Hcount + 1;
  159 + elsif Hcount < 1185 then
  160 + -- Pw
  161 + Hsync <= '0';
  162 + Hcount <= Hcount + 1;
  163 + elsif Hcount < 1344 then
  164 + -- Bp
  165 + Hsync <= '1';
  166 + Hcount <= Hcount + 1;
  167 + else
  168 + Hcount <= 1;
  169 + end if;
  170 +
  171 + -- Synchro vertical
  172 + if Vcount < 1032193 then
  173 + -- Affichage de toutes les lignes
  174 + Vsync <= '1';
  175 + Vcount <= Vcount + 1;
  176 + elsif Vcount < (1032193 + 4032) then
  177 + --Fp
  178 + Vsync <= '1';
  179 + Vcount <= Vcount + 1;
  180 + elsif Vcount < (1032193 + 4032 + 8064) then
  181 + --Pw
  182 + Vsync <= '0';
  183 + Vcount <= Vcount + 1;
  184 + elsif Vcount < (1032192 + 4032 + 8064 + 38976) then
  185 + --Bp
  186 + Vsync <= '1';
  187 + Vcount <= Vcount + 1;
  188 + else
  189 + Vcount <= 1;
  190 + end if;
  191 +end if;
  192 +end process;
  193 +end Behavioral;