From 4873ae75eb1ff630a2f173764122fbf8e1b22422 Mon Sep 17 00:00:00 2001 From: rduhr Date: Tue, 31 Oct 2023 15:20:11 +0100 Subject: [PATCH] vga Readme --- Vga_display/vga_controller.vhd | 193 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 193 insertions(+), 0 deletions(-) create mode 100755 Vga_display/vga_controller.vhd diff --git a/Vga_display/vga_controller.vhd b/Vga_display/vga_controller.vhd new file mode 100755 index 0000000..169788d --- /dev/null +++ b/Vga_display/vga_controller.vhd @@ -0,0 +1,193 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04.10.2023 10:40:26 +-- Design Name: +-- Module Name: vga_controller - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity vga_controller is + Port (clk_fpga : in std_logic; + sw : in std_logic_vector(15 downto 0); + vgaRed : out std_logic_vector(3 downto 0); + vgaGreen : out std_logic_vector(3 downto 0); + vgaBlue : out std_logic_vector(3 downto 0); + Hsync : out std_logic; + Vsync : out std_logic); +end vga_controller; + +architecture Behavioral of vga_controller is + +component clk_wiz_0 + port (clk_out1 : out std_logic; + clk_in1 : in std_logic); +end component; + +signal clk_65MHz : std_logic; +signal Hcount : integer range 1344 downto 1 := 1; +signal Vcount : integer range 1083264 downto 1 := 1; +signal myRed: std_logic_vector(3 downto 0); +signal myBlue: std_logic_vector(3 downto 0); +signal myGreen: std_logic_vector(3 downto 0); + +signal leftLimit: integer range 1025 downto 0:= 0; +signal rightLimit: integer range 1025 downto 0:= 100; +signal upLimit: integer range 768 downto 0:= 0; +signal downLimit: integer range 768 downto 0:= 100; +signal pixelX: integer range 1344 downto 1:= 1; +signal pixelY: integer range 768 downto 1; + +begin + +clk_65MHz_1 : clk_wiz_0 port map (clk_out1 => clk_65MHz, + clk_in1 => clk_fpga); + +myRed(0) <= sw(0); +myRed(1) <= sw(1); +myRed(2) <= sw(2); +myRed(3) <= sw(3); +myBlue(0) <= sw(4); +myBlue(1) <= sw(5); +myBlue(2) <= sw(6); +myBlue(3) <= sw(7); +myGreen(0) <= sw(8); +myGreen(1) <= sw(9); +myGreen(2) <= sw(10); +myGreen(3) <= sw(11); + +pixelX <= Hcount; + +process(clk_65MHz) +begin +if clk_65MHz'event and clk_65MHz = '1' then + if Vcount = 1032193 then + if rightLimit > 1024 and downLimit > 768 then + leftLimit <= 0; + rightLimit <= 100; + upLimit <= 0; + downLimit <= 100; + elsif rightLimit > 1024 then + leftLimit <= 0; + rightLimit <= 100; + upLimit <= upLimit + 1; + downLimit <= downLimit + 1; + else + leftLimit <= leftLimit + 1; + rightLimit <= rightLimit +1; + end if; + end if; +end if; +end process; + +process(clk_65MHz) +-- Simplification des valeurs d'écran +begin +if clk_65MHz'event and clk_65MHz = '1' then + if Vcount = 1 then + pixelY <= 1; + elsif Hcount = 1025 then + pixelY <= pixelY + 1; + end if; +end if; +end process; + +process(clk_65MHz) +-- Gestion de l'affichage +begin +if clk_65MHz'event and clk_65MHz = '1' then + if pixelX > leftLimit and pixelX < rightLimit and pixelY > upLimit and pixelY < downLimit then + -- Carré + vgaRed <= myRed; + vgaBlue <= myBlue; + vgaGreen <= myGreen; + elsif Hcount < 1025 and pixelY < 769 then + -- Background + vgaRed <= (others => '1'); + vgaBlue <= (others => '1'); + vgaGreen <= (others => '1'); + else + -- Hors pixel + vgaRed <= (others => '0'); + vgaBlue <= (others => '0'); + vgaGreen <= (others => '0'); + end if; +end if; +end process; + +process(clk_65MHz) +begin +if clk_65MHz'event and clk_65MHz = '1' then + +-- Gestion du vga + + -- Syncro horizontale + if Hcount < 1025 then + -- affichage + Hsync <= '1'; + Hcount <= Hcount + 1; + elsif Hcount < 1049 then + -- Fp + Hsync <= '1'; + Hcount <= Hcount + 1; + elsif Hcount < 1185 then + -- Pw + Hsync <= '0'; + Hcount <= Hcount + 1; + elsif Hcount < 1344 then + -- Bp + Hsync <= '1'; + Hcount <= Hcount + 1; + else + Hcount <= 1; + end if; + + -- Synchro vertical + if Vcount < 1032193 then + -- Affichage de toutes les lignes + Vsync <= '1'; + Vcount <= Vcount + 1; + elsif Vcount < (1032193 + 4032) then + --Fp + Vsync <= '1'; + Vcount <= Vcount + 1; + elsif Vcount < (1032193 + 4032 + 8064) then + --Pw + Vsync <= '0'; + Vcount <= Vcount + 1; + elsif Vcount < (1032192 + 4032 + 8064 + 38976) then + --Bp + Vsync <= '1'; + Vcount <= Vcount + 1; + else + Vcount <= 1; + end if; +end if; +end process; +end Behavioral; -- libgit2 0.21.2