bilalelhasnaoui / Travaux_pratiques_VHDL

Commit d329d9f24c4093a1b5e972e3f1817609ea591205

Authored by bilalelhasnaoui
1 parent 2ceacc81

Code VHDL pour le control VGA

Showing 1 changed file with 81 additions and 107 deletions   Show diff stats
Inline Side-by-side
TP_VGA/TP_VGA.srcs/sources_1/new/VGA_vhdl.vhd
  Show/Hide comments   View file @d329d9f
1 -----------------------------------------------------------------------------------  
2 --- Company:  
3 --- Engineer:  
4 ---  
5 --- Create Date: 04.10.2023 16:25:02  
6 --- Design Name:  
7 --- Module Name: VGA_vhdl - Behavioral  
8 --- Project Name:  
9 --- Target Devices:  
10 --- Tool Versions:  
11 --- Description:  
12 ---  
13 --- Dependencies:  
14 ---  
15 --- Revision:  
16 --- Revision 0.01 - File Created  
17 --- Additional Comments:  
18 ---  
19 ----------------------------------------------------------------------------------- 1 +library IEEE;
  2 +use IEEE.STD_LOGIC_1164.ALL;
  3 +use IEEE.STD_LOGIC_ARITH.ALL;
  4 +use IEEE.STD_LOGIC_UNSIGNED.ALL;
20 5
21 -library ieee;  
22 -use ieee.std_logic_unsigned.all;  
23 -use ieee.numeric_std.all;  
24 -use ieee.std_logic_1164.all; 6 +entity VGA_Rectangle is
  7 + Port ( Clk_sys: in STD_LOGIC;
  8 + Rst: in STD_LOGIC;
  9 + vga_hsync: out STD_LOGIC;
  10 + vga_vsync: out STD_LOGIC;
  11 + Vga_red, Vga_green, Vga_blue: out STD_LOGIC_VECTOR (3 downto 0)
  12 + );
  13 +end VGA_Rectangle;
25 14
26 --- Uncomment the following library declaration if using  
27 ---use IEEE.NUMERIC_STD.ALL; 15 +architecture Behavioral of VGA_Rectangle is
  16 + -- Définition des pixels de la zone visible, front porche, back et synchronisation horizontale.
  17 + -- Zone de synchronisation horizontale de 136 Pixels, Tpw
  18 + constant H_SYNC_CYC : integer := 136;
  19 + -- Zone horizontale arrière de 160 Pixels, Tbp.
  20 + constant H_SYNC_BACK: integer := 160;
  21 + -- Zone active d’affichage horizontale de 1024 pixels
  22 + constant H_SYNC_ACT : integer := 1024;
  23 + -- Zone horizontale avant.
  24 + constant H_SYNC_FRONT: integer := 24;
  25 + constant H_SYNC_TOTAL: integer := 1344;
  26 +
  27 + -- Définition des pixels de la zone visible, front porche, back et synchronisation Verticale.
  28 + -- Zone de synchronisation verticale de 6 Pixels, Tpw
  29 + constant V_SYNC_CYC : integer := 6;
  30 + -- Zone horizontale arrière de 29 Pixels, Tbp.
  31 + constant V_SYNC_BACK: integer := 29;
  32 + -- Zone active d’affichage horizontale de 768 pixels.
  33 + constant V_SYNC_ACT : integer := 768;
  34 + -- Zone horizontale avant.
  35 + constant V_SYNC_FRONT: integer := 3;
28 36
29 --- Uncomment the following library declaration if instantiating  
30 ---library UNISIM;  
31 ---use UNISIM.VComponents.all; 37 + signal h_counter: integer range 0 to 1343 := 0;
  38 + signal v_counter: integer range 0 to 805 := 0;
32 39
33 -entity VGA_vhdl is  
34 - Port ( Clk_sys : in STD_LOGIC;  
35 - b1 : in STD_LOGIC;  
36 - b2 : in STD_LOGIC;  
37 - b3 : in STD_LOGIC;  
38 - Reset : in STD_LOGIC;  
39 - HS : out std_logic;  
40 - HV : out std_logic;  
41 - R : out std_logic_vector(3 downto 0);  
42 - G : out std_logic_vector(3 downto 0);  
43 - B : out std_logic_vector(3 downto 0)  
44 - );  
45 -end VGA_vhdl;  
46 -  
47 -architecture Behavioral of VGA_vhdl is  
48 -  
49 -signal pixel_clk : std_logic := '0';  
50 -signal CompteurHS: std_logic_vector(11 downto 0); -- Generation du signal VH  
51 -signal CompteurVS: std_logic_vector(9 downto 0);  
52 --------------------  
53 --- CLOCK 65 MHZ --  
54 --------------------  
55 -component clk_wiz_0  
56 -port  
57 - (-- Clock in ports  
58 - -- Clock out ports  
59 - clk_out1 : out std_logic;  
60 - clk_in1 : in std_logic  
61 - );  
62 -end component;  
63 -  
64 -begin  
65 -----------  
66 --- Compteur Horizental --  
67 -------------  
68 -Compteur_HS: process(pixel_clk) 40 + constant RECTANGLE_WIDTH: integer := 200; -- Rectangle width
  41 + constant RECTANGLE_HEIGHT: integer := 200; -- Rectangle height
  42 + signal pixel_clk : std_logic;
  43 + -- Pour faire la division de fréquence d'FPGA de 100Mhz a 63 MHz.
  44 + component clk_wiz_0 port(
  45 + clk_out1 : out std_logic;
  46 + clk_in1 : in std_logic
  47 + );
69 begin 48 begin
70 - if rising_edge(pixel_clk) then  
71 - if CompteurHS < 1344 then  
72 - CompteurHS <= CompteurHS +1;  
73 - HS <= '1';  
74 - if CompteurHS = 1048 then  
75 - HS <= '0';  
76 - elsif CompteurHS = 1184 then  
77 - HS <= '1'; 49 + Clk_divide: clk_wizard_0 port map(
  50 + clk_ou1 => pixel_clk;
  51 + clk_in1 => Clk_sys
  52 + );
  53 + -- Le première processus pour faire le balayage des pixels d'image.
  54 + Blayage :process(pixel_clk, Rst)
  55 + begin
  56 + if Rst = '1' then
  57 + h_counter <= 0;
  58 + v_counter <= 0;
  59 + elsif rising_edge(clk) then
  60 + if h_counter = 1343 then
  61 + h_counter <= 0;
  62 + if v_counter = 805 then
  63 + v_counter <= 0;
  64 + else
  65 + v_counter <= v_counter + 1;
  66 + end if;
  67 + else
  68 + h_counter <= h_counter + 1;
78 end if; 69 end if;
79 - else CompteurHS <= (others => '0');  
80 - end if;  
81 - end if;  
82 -end process;  
83 -----------  
84 --- Compteur Vertical --  
85 -------------  
86 -Compteur_VS: process(pixel_clk)  
87 -begin  
88 - if rising_edge(pixel_clk) then  
89 - if CompteurVS < 806 then  
90 - CompteurHS <= CompteurHS +1;  
91 - HS <= '1';  
92 - if CompteurVS = 771 then  
93 - HS <= '0';  
94 - elsif CompteurVS = 777 then  
95 - HS <= '1';  
96 - end if;  
97 - else CompteurVS <= (others => '0');  
98 end if; 70 end if;
99 - end if;  
100 -end process;  
101 -------------  
102 -  
103 -your_instance_name : clk_wiz_0  
104 - port map (  
105 - -- Clock out ports  
106 - clk_out1 => pixel_clk,  
107 - -- Clock in ports  
108 - clk_in1 => Clk_sys  
109 - );  
110 - ----------------  
111 -  
112 - 71 + end process;
  72 +
  73 + Afficheur : process(h_counyter, v_counter)
  74 + begin
  75 + vga_hsync <= '1' when (h_counter < H_SYNC_CYC) else '0';
  76 + vga_vsync <= '1' when (v_counter < V_SYNC_CYC) else '0';
  77 + -- Afficher le rectangle.
  78 + if (h_counter >= H_SYNC_BACK + 200) and (h_counter < H_SYNC_BACK + 600)
  79 + and (v_counter >= V_SYNC_BACK 200) and (v_counter < V_SYNC_BACK + 600) then
  80 + vga_red <= "1111";
  81 + vga_green <= "0000";
  82 + vga_blue <= "0000";
  83 + else
  84 + vga_red <= "0000";
  85 + vga_green <= "0000";
  86 + vga_blue <= "0000";
  87 + end if;
  88 + end process;
113 end Behavioral; 89 end Behavioral;