From d329d9f24c4093a1b5e972e3f1817609ea591205 Mon Sep 17 00:00:00 2001 From: bilalelhasnaoui Date: Mon, 30 Oct 2023 00:54:29 +0100 Subject: [PATCH] Code VHDL pour le control VGA --- TP_VGA/TP_VGA.srcs/sources_1/new/VGA_vhdl.vhd | 188 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----------------------------------------------------------------------------------------------------------- 1 file changed, 81 insertions(+), 107 deletions(-) diff --git a/TP_VGA/TP_VGA.srcs/sources_1/new/VGA_vhdl.vhd b/TP_VGA/TP_VGA.srcs/sources_1/new/VGA_vhdl.vhd index 67aed8a..344a5a4 100755 --- a/TP_VGA/TP_VGA.srcs/sources_1/new/VGA_vhdl.vhd +++ b/TP_VGA/TP_VGA.srcs/sources_1/new/VGA_vhdl.vhd @@ -1,115 +1,89 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 04.10.2023 16:25:02 --- Design Name: --- Module Name: VGA_vhdl - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; -library ieee; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.all; -use ieee.std_logic_1164.all; +entity VGA_Rectangle is + Port ( Clk_sys: in STD_LOGIC; + Rst: in STD_LOGIC; + vga_hsync: out STD_LOGIC; + vga_vsync: out STD_LOGIC; + Vga_red, Vga_green, Vga_blue: out STD_LOGIC_VECTOR (3 downto 0) + ); +end VGA_Rectangle; --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; +architecture Behavioral of VGA_Rectangle is + -- Définition des pixels de la zone visible, front porche, back et synchronisation horizontale. + -- Zone de synchronisation horizontale de 136 Pixels, Tpw + constant H_SYNC_CYC : integer := 136; + -- Zone horizontale arrière de 160 Pixels, Tbp. + constant H_SYNC_BACK: integer := 160; + -- Zone active d’affichage horizontale de 1024 pixels + constant H_SYNC_ACT : integer := 1024; + -- Zone horizontale avant. + constant H_SYNC_FRONT: integer := 24; + constant H_SYNC_TOTAL: integer := 1344; + + -- Définition des pixels de la zone visible, front porche, back et synchronisation Verticale. + -- Zone de synchronisation verticale de 6 Pixels, Tpw + constant V_SYNC_CYC : integer := 6; + -- Zone horizontale arrière de 29 Pixels, Tbp. + constant V_SYNC_BACK: integer := 29; + -- Zone active d’affichage horizontale de 768 pixels. + constant V_SYNC_ACT : integer := 768; + -- Zone horizontale avant. + constant V_SYNC_FRONT: integer := 3; --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; + signal h_counter: integer range 0 to 1343 := 0; + signal v_counter: integer range 0 to 805 := 0; -entity VGA_vhdl is - Port ( Clk_sys : in STD_LOGIC; - b1 : in STD_LOGIC; - b2 : in STD_LOGIC; - b3 : in STD_LOGIC; - Reset : in STD_LOGIC; - HS : out std_logic; - HV : out std_logic; - R : out std_logic_vector(3 downto 0); - G : out std_logic_vector(3 downto 0); - B : out std_logic_vector(3 downto 0) - ); -end VGA_vhdl; - -architecture Behavioral of VGA_vhdl is - -signal pixel_clk : std_logic := '0'; -signal CompteurHS: std_logic_vector(11 downto 0); -- Generation du signal VH -signal CompteurVS: std_logic_vector(9 downto 0); -------------------- --- CLOCK 65 MHZ -- -------------------- -component clk_wiz_0 -port - (-- Clock in ports - -- Clock out ports - clk_out1 : out std_logic; - clk_in1 : in std_logic - ); -end component; - -begin ----------- --- Compteur Horizental -- ------------- -Compteur_HS: process(pixel_clk) + constant RECTANGLE_WIDTH: integer := 200; -- Rectangle width + constant RECTANGLE_HEIGHT: integer := 200; -- Rectangle height + signal pixel_clk : std_logic; + -- Pour faire la division de fréquence d'FPGA de 100Mhz a 63 MHz. + component clk_wiz_0 port( + clk_out1 : out std_logic; + clk_in1 : in std_logic + ); begin - if rising_edge(pixel_clk) then - if CompteurHS < 1344 then - CompteurHS <= CompteurHS +1; - HS <= '1'; - if CompteurHS = 1048 then - HS <= '0'; - elsif CompteurHS = 1184 then - HS <= '1'; + Clk_divide: clk_wizard_0 port map( + clk_ou1 => pixel_clk; + clk_in1 => Clk_sys + ); + -- Le première processus pour faire le balayage des pixels d'image. + Blayage :process(pixel_clk, Rst) + begin + if Rst = '1' then + h_counter <= 0; + v_counter <= 0; + elsif rising_edge(clk) then + if h_counter = 1343 then + h_counter <= 0; + if v_counter = 805 then + v_counter <= 0; + else + v_counter <= v_counter + 1; + end if; + else + h_counter <= h_counter + 1; end if; - else CompteurHS <= (others => '0'); - end if; - end if; -end process; ----------- --- Compteur Vertical -- ------------- -Compteur_VS: process(pixel_clk) -begin - if rising_edge(pixel_clk) then - if CompteurVS < 806 then - CompteurHS <= CompteurHS +1; - HS <= '1'; - if CompteurVS = 771 then - HS <= '0'; - elsif CompteurVS = 777 then - HS <= '1'; - end if; - else CompteurVS <= (others => '0'); end if; - end if; -end process; ------------- - -your_instance_name : clk_wiz_0 - port map ( - -- Clock out ports - clk_out1 => pixel_clk, - -- Clock in ports - clk_in1 => Clk_sys - ); - ---------------- - - + end process; + + Afficheur : process(h_counyter, v_counter) + begin + vga_hsync <= '1' when (h_counter < H_SYNC_CYC) else '0'; + vga_vsync <= '1' when (v_counter < V_SYNC_CYC) else '0'; + -- Afficher le rectangle. + if (h_counter >= H_SYNC_BACK + 200) and (h_counter < H_SYNC_BACK + 600) + and (v_counter >= V_SYNC_BACK 200) and (v_counter < V_SYNC_BACK + 600) then + vga_red <= "1111"; + vga_green <= "0000"; + vga_blue <= "0000"; + else + vga_red <= "0000"; + vga_green <= "0000"; + vga_blue <= "0000"; + end if; + end process; end Behavioral; -- libgit2 0.21.2