bilalelhasnaoui / Travaux_pratiques_VHDL

Commit 93a347e976e277b05ecd87c51ca6009c00b12b2a

Authored by bilalelhasnaoui
1 parent d329d9f2

Fichier source VHDL pour control écran par VGA

Showing 1 changed file with 5 additions and 7 deletions   Show diff stats
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TP_VGA/TP_VGA.srcs/sources_1/new/VGA_vhdl.vhd
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@@ -6,8 +6,8 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL; @@ -6,8 +6,8 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
6 entity VGA_Rectangle is 6 entity VGA_Rectangle is
7 Port ( Clk_sys: in STD_LOGIC; 7 Port ( Clk_sys: in STD_LOGIC;
8 Rst: in STD_LOGIC; 8 Rst: in STD_LOGIC;
9 - vga_hsync: out STD_LOGIC;  
10 - vga_vsync: out STD_LOGIC; 9 + h_sync: out STD_LOGIC;
  10 + v_sync: out STD_LOGIC;
11 Vga_red, Vga_green, Vga_blue: out STD_LOGIC_VECTOR (3 downto 0) 11 Vga_red, Vga_green, Vga_blue: out STD_LOGIC_VECTOR (3 downto 0)
12 ); 12 );
13 end VGA_Rectangle; 13 end VGA_Rectangle;
@@ -37,8 +37,6 @@ architecture Behavioral of VGA_Rectangle is @@ -37,8 +37,6 @@ architecture Behavioral of VGA_Rectangle is
37 signal h_counter: integer range 0 to 1343 := 0; 37 signal h_counter: integer range 0 to 1343 := 0;
38 signal v_counter: integer range 0 to 805 := 0; 38 signal v_counter: integer range 0 to 805 := 0;
39 39
40 - constant RECTANGLE_WIDTH: integer := 200; -- Rectangle width  
41 - constant RECTANGLE_HEIGHT: integer := 200; -- Rectangle height  
42 signal pixel_clk : std_logic; 40 signal pixel_clk : std_logic;
43 -- Pour faire la division de fréquence d'FPGA de 100Mhz a 63 MHz. 41 -- Pour faire la division de fréquence d'FPGA de 100Mhz a 63 MHz.
44 component clk_wiz_0 port( 42 component clk_wiz_0 port(
@@ -72,8 +70,8 @@ begin @@ -72,8 +70,8 @@ begin
72 70
73 Afficheur : process(h_counyter, v_counter) 71 Afficheur : process(h_counyter, v_counter)
74 begin 72 begin
75 - vga_hsync <= '1' when (h_counter < H_SYNC_CYC) else '0';  
76 - vga_vsync <= '1' when (v_counter < V_SYNC_CYC) else '0'; 73 + h_sync <= '1' when (h_counter < H_SYNC_CYC) else '0';
  74 + v_sync <= '1' when (v_counter < V_SYNC_CYC) else '0';
77 -- Afficher le rectangle. 75 -- Afficher le rectangle.
78 if (h_counter >= H_SYNC_BACK + 200) and (h_counter < H_SYNC_BACK + 600) 76 if (h_counter >= H_SYNC_BACK + 200) and (h_counter < H_SYNC_BACK + 600)
79 and (v_counter >= V_SYNC_BACK 200) and (v_counter < V_SYNC_BACK + 600) then 77 and (v_counter >= V_SYNC_BACK 200) and (v_counter < V_SYNC_BACK + 600) then
@@ -86,4 +84,4 @@ begin @@ -86,4 +84,4 @@ begin
86 vga_blue <= "0000"; 84 vga_blue <= "0000";
87 end if; 85 end if;
88 end process; 86 end process;
89 -end Behavioral; 87 -end Behavioral;
  88 +end Behavioral;
90 \ No newline at end of file 89 \ No newline at end of file