diff --git a/TP_VGA/TP_VGA.srcs/sources_1/new/VGA_vhdl.vhd b/TP_VGA/TP_VGA.srcs/sources_1/new/VGA_vhdl.vhd
index 344a5a4..8322677 100755
--- a/TP_VGA/TP_VGA.srcs/sources_1/new/VGA_vhdl.vhd
+++ b/TP_VGA/TP_VGA.srcs/sources_1/new/VGA_vhdl.vhd
@@ -6,8 +6,8 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
 entity VGA_Rectangle is
     Port ( Clk_sys: in STD_LOGIC;
            Rst: in STD_LOGIC;
-           vga_hsync: out STD_LOGIC;
-           vga_vsync: out STD_LOGIC;
+           h_sync: out STD_LOGIC;
+           v_sync: out STD_LOGIC;
            Vga_red, Vga_green, Vga_blue: out STD_LOGIC_VECTOR (3 downto 0)
          );
 end VGA_Rectangle;
@@ -37,8 +37,6 @@ architecture Behavioral of VGA_Rectangle is
     signal h_counter: integer range 0 to 1343 := 0;
     signal v_counter: integer range 0 to 805 := 0;
 
-    constant RECTANGLE_WIDTH: integer := 200;       -- Rectangle width
-    constant RECTANGLE_HEIGHT: integer := 200;      -- Rectangle height
     signal pixel_clk : std_logic;
     -- Pour faire la division de fréquence d'FPGA de 100Mhz a 63 MHz.
     component clk_wiz_0 port(
@@ -72,8 +70,8 @@ begin
     
     Afficheur : process(h_counyter, v_counter)
     begin
-        vga_hsync <= '1' when (h_counter < H_SYNC_CYC) else '0';
-        vga_vsync <= '1' when (v_counter < V_SYNC_CYC) else '0';
+        h_sync <= '1' when (h_counter < H_SYNC_CYC) else '0';
+        v_sync <= '1' when (v_counter < V_SYNC_CYC) else '0';
         -- Afficher le rectangle.
         if (h_counter >= H_SYNC_BACK + 200) and (h_counter < H_SYNC_BACK + 600)
             and (v_counter >= V_SYNC_BACK 200) and (v_counter < V_SYNC_BACK + 600) then
@@ -86,4 +84,4 @@ begin
             vga_blue <= "0000";
         end if;
     end process;
-end Behavioral;
+end Behavioral;
\ No newline at end of file
--
libgit2 0.21.2