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vga Readme
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1 | +## This file is a general .xdc for the Basys3 rev B board | ||
2 | +## To use it in a project: | ||
3 | +## - uncomment the lines corresponding to used pins | ||
4 | +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project | ||
5 | + | ||
6 | +## Clock signal | ||
7 | +set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports clk_fpga] | ||
8 | +#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] | ||
9 | + | ||
10 | + | ||
11 | +## Switches | ||
12 | +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {sw[0]}] | ||
13 | +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {sw[1]}] | ||
14 | +set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {sw[2]}] | ||
15 | +set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}] | ||
16 | +set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}] | ||
17 | +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {sw[5]}] | ||
18 | +set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports {sw[6]}] | ||
19 | +set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports {sw[7]}] | ||
20 | +set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports {sw[8]}] | ||
21 | +set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {sw[9]}] | ||
22 | +set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {sw[10]}] | ||
23 | +set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {sw[11]}] | ||
24 | +set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {sw[12]}] | ||
25 | +set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {sw[13]}] | ||
26 | +set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {sw[14]}] | ||
27 | +set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {sw[14]}] | ||
28 | + | ||
29 | + | ||
30 | +## LEDs | ||
31 | +#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports {led[0]}] | ||
32 | +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports {led[1]}] | ||
33 | +#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports {led[2]}] | ||
34 | +#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports {led[3]}] | ||
35 | +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports {led[4]}] | ||
36 | +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports {led[5]}] | ||
37 | +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports {led[6]}] | ||
38 | +#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports output] | ||
39 | +#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports {led[8]}] | ||
40 | +#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports {led[9]}] | ||
41 | +#set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports {led[10]}] | ||
42 | +#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports {led[11]}] | ||
43 | +#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports {led[12]}] | ||
44 | +#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports {led[13]}] | ||
45 | +#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports {led[14]}] | ||
46 | +#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports {led[15]}] | ||
47 | + | ||
48 | + | ||
49 | +##7 Segment Display | ||
50 | +#set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports {aff[0]}] | ||
51 | +#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports {aff[1]}] | ||
52 | +#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports {aff[2]}] | ||
53 | +#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports {aff[3]}] | ||
54 | +#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports {aff[4]}] | ||
55 | +#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports {aff[5]}] | ||
56 | +#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports {aff[6]}] | ||
57 | + | ||
58 | +#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports {aff[7]}] | ||
59 | + | ||
60 | +#set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports {an[0]}] | ||
61 | +#set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports {an[1]}] | ||
62 | +#set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports {an[2]}] | ||
63 | +#set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {an[3]}] | ||
64 | + | ||
65 | + | ||
66 | +##Buttons | ||
67 | +#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC] | ||
68 | +#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports btnU] | ||
69 | +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports btnL] | ||
70 | +#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports btnR] | ||
71 | +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports btnD] | ||
72 | + | ||
73 | + | ||
74 | +##Pmod Header JA | ||
75 | +#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports {JA[0]];#Sch name = JA1 | ||
76 | +#set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports {JA[1]}];#Sch name = JA2 | ||
77 | +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports {JA[2]}];#Sch name = JA3 | ||
78 | +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports {JA[3]}];#Sch name = JA4 | ||
79 | +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports {JA[4]}];#Sch name = JA7 | ||
80 | +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports {JA[5]}];#Sch name = JA8 | ||
81 | +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports {JA[6]}];#Sch name = JA9 | ||
82 | +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports {JA[7]}];#Sch name = JA10 | ||
83 | + | ||
84 | +##Pmod Header JB | ||
85 | +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports clock_int_visu];#Sch name = JB1 | ||
86 | +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports sortie_visu];#Sch name = JB2 | ||
87 | +#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports {JB[2]}];#Sch name = JB3 | ||
88 | +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports {JB[3]}];#Sch name = JB4 | ||
89 | +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports {JB[4]}];#Sch name = JB7 | ||
90 | +#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports {JB[5]}];#Sch name = JB8 | ||
91 | +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports {JB[6]}];#Sch name = JB9 | ||
92 | +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports {JB[7]}];#Sch name = JB10 | ||
93 | + | ||
94 | +##Pmod Header JC | ||
95 | +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports {JC[0]}];#Sch name = JC1 | ||
96 | +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports {JC[1]}];#Sch name = JC2 | ||
97 | +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports {JC[2]}];#Sch name = JC3 | ||
98 | +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports {JC[3]}];#Sch name = JC4 | ||
99 | +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports {JC[4]}];#Sch name = JC7 | ||
100 | +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports {JC[5]}];#Sch name = JC8 | ||
101 | +#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports {JC[6]}];#Sch name = JC9 | ||
102 | +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports {JC[7]}];#Sch name = JC10 | ||
103 | + | ||
104 | +##Pmod Header JXADC | ||
105 | +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[0]}];#Sch name = XA1_P | ||
106 | +#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[1]}];#Sch name = XA2_P | ||
107 | +#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[2]}];#Sch name = XA3_P | ||
108 | +#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[3]}];#Sch name = XA4_P | ||
109 | +#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[4]}];#Sch name = XA1_N | ||
110 | +#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[5]}];#Sch name = XA2_N | ||
111 | +#set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[6]}];#Sch name = XA3_N | ||
112 | +#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[7]}];#Sch name = XA4_N | ||
113 | + | ||
114 | + | ||
115 | +##VGA Connector | ||
116 | +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[0]}] | ||
117 | +#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[1]}] | ||
118 | +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[2]}] | ||
119 | +#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[3]}] | ||
120 | +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[0]}] | ||
121 | +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[1]}] | ||
122 | +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[2]}] | ||
123 | +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[3]}] | ||
124 | +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[0]}] | ||
125 | +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[1]}] | ||
126 | +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[2]}] | ||
127 | +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[3]}] | ||
128 | +#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports Hsync] | ||
129 | +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports Vsync] | ||
130 | + | ||
131 | + | ||
132 | +##USB-RS232 Interface | ||
133 | +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports RsRx] | ||
134 | +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports RsTx] | ||
135 | + | ||
136 | + | ||
137 | +##USB HID (PS/2) | ||
138 | +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Clk] | ||
139 | +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Data] | ||
140 | + | ||
141 | + | ||
142 | +##Quad SPI Flash | ||
143 | +##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the | ||
144 | +##STARTUPE2 primitive. | ||
145 | +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[0]}] | ||
146 | +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[1]}] | ||
147 | +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[2]}] | ||
148 | +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[3]}] | ||
149 | +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports QspiCSn] | ||
150 | + | ||
151 | + | ||
152 | +## Configuration options, can be used for all designs | ||
153 | +set_property CONFIG_VOLTAGE 3.3 [current_design] | ||
154 | +set_property CFGBVS VCCO [current_design] | ||
155 | + | ||
156 | +## SPI configuration mode options for QSPI boot, can be used for all designs | ||
157 | +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] | ||
158 | +set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] | ||
159 | +set_property CONFIG_MODE SPIx4 [current_design] | ||
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