Commit 122d531c6125d6d7360c75c963609ef785d8b785

Authored by rduhr
1 parent fa17553e

7Segment_display readme

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7Segment_display/README.md
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  1 +## 7 Segments display
  2 +
  3 +```vhdl
  4 +entity display is
  5 + port {
  6 + clk_fpga : in STD_LOGIC;
  7 + reset : in STD_LOGIC;
  8 + aff : out STD_LOGIC_VECTOR{7 downto 0};
  9 + };
  10 +end display;
  11 +```
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