rcavalie / PFE

Commit 64abd45dda854fe8221f783a9733a2627dbc06cd

Authored by rcavalie
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emetteur/SX1276Lib/LICENSE.txt 0 → 100644
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  1 +--- Revised BSD License ---
  2 +Copyright (c) 2013, SEMTECH S.A.
  3 +All rights reserved.
  4 +
  5 +Redistribution and use in source and binary forms, with or without
  6 +modification, are permitted provided that the following conditions are met:
  7 + * Redistributions of source code must retain the above copyright
  8 + notice, this list of conditions and the following disclaimer.
  9 + * Redistributions in binary form must reproduce the above copyright
  10 + notice, this list of conditions and the following disclaimer in the
  11 + documentation and/or other materials provided with the distribution.
  12 + * Neither the name of the Semtech corporation nor the
  13 + names of its contributors may be used to endorse or promote products
  14 + derived from this software without specific prior written permission.
  15 +
  16 +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  17 +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  18 +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  19 +DISCLAIMED. IN NO EVENT SHALL SEMTECH S.A. BE LIABLE FOR ANY
  20 +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21 +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22 +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23 +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25 +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0 26 \ No newline at end of file
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emetteur/SX1276Lib/debug/debug.h 0 → 100644
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  1 +/* Copyright (c) 2012 mbed.org, MIT License
  2 + *
  3 + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
  4 + * and associated documentation files (the "Software"), to deal in the Software without restriction,
  5 + * including without limitation the rights to use, copy, modify, merge, publish, distribute,
  6 + * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
  7 + * furnished to do so, subject to the following conditions:
  8 + *
  9 + * The above copyright notice and this permission notice shall be included in all copies or
  10 + * substantial portions of the Software.
  11 + *
  12 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  13 + * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  14 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
  15 + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  16 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  17 + */
  18 +
  19 +#ifndef DEBUG_H
  20 +#define DEBUG_H
  21 +
  22 +/** @file debug.h */
  23 +
  24 +#ifndef NDEBUG
  25 +
  26 +#include <stdarg.h>
  27 +#include <stdio.h>
  28 +
  29 +/** Output a debug message
  30 + *
  31 + * @param format printf-style format string, followed by variables
  32 + */
  33 +static inline void debug(const char *format, ...) {
  34 + va_list args;
  35 + va_start(args, format);
  36 + vfprintf(stderr, format, args);
  37 + va_end(args);
  38 +}
  39 +
  40 +/** Conditionally output a debug message
  41 + *
  42 + * @param condition output only if condition is true
  43 + * @param format printf-style format string, followed by variables
  44 + */
  45 +static inline void debug_if(bool condition, const char *format, ...) {
  46 + if(condition) {
  47 + va_list args;
  48 + va_start(args, format);
  49 + vfprintf(stderr, format, args);
  50 + va_end(args);
  51 + }
  52 +}
  53 +
  54 +#else
  55 +
  56 +static inline void debug(const char *format, ...) {}
  57 +static inline void debug(bool condition, const char *format, ...) {}
  58 +
  59 +#endif
  60 +
  61 +#endif
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emetteur/SX1276Lib/enums/enums.h 0 → 100644
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  1 +/*
  2 + / _____) _ | |
  3 +( (____ _____ ____ _| |_ _____ ____| |__
  4 + \____ \| ___ | (_ _) ___ |/ ___) _ \
  5 + _____) ) ____| | | || |_| ____( (___| | | |
  6 +(______/|_____)_|_|_| \__)_____)\____)_| |_|
  7 + (C) 2014 Semtech
  8 +
  9 +Description: -
  10 +
  11 +License: Revised BSD License, see LICENSE.TXT file include in the project
  12 +
  13 +Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
  14 +*/
  15 +#ifndef __ENUMS_H__
  16 +#define __ENUMS_H__
  17 +
  18 +/*!
  19 + * Radio driver internal state machine states definition
  20 + */
  21 +typedef enum RadioState
  22 +{
  23 + RF_IDLE = 0,
  24 + RF_RX_RUNNING,
  25 + RF_TX_RUNNING,
  26 + RF_CAD,
  27 +}RadioState_t;
  28 +
  29 +/*!
  30 + * Type of the modem. [LORA / FSK]
  31 + */
  32 +typedef enum ModemType
  33 +{
  34 + MODEM_FSK = 0,
  35 + MODEM_LORA
  36 +}RadioModems_t;
  37 +
  38 +/*!
  39 + * Type of the supported board. [SX1276MB1MAS / SX1276MB1LAS]
  40 + */
  41 +typedef enum BoardType
  42 +{
  43 + SX1276MB1MAS = 0,
  44 + SX1276MB1LAS,
  45 + UNKNOWN
  46 +}BoardType_t;
  47 +
  48 +/*!
  49 + * Radio FSK modem parameters
  50 + */
  51 +typedef struct
  52 +{
  53 + int8_t Power;
  54 + uint32_t Fdev;
  55 + uint32_t Bandwidth;
  56 + uint32_t BandwidthAfc;
  57 + uint32_t Datarate;
  58 + uint16_t PreambleLen;
  59 + bool FixLen;
  60 + uint8_t PayloadLen;
  61 + bool CrcOn;
  62 + bool IqInverted;
  63 + bool RxContinuous;
  64 + uint32_t TxTimeout;
  65 + uint32_t RxSingleTimeout;
  66 +}RadioFskSettings_t;
  67 +
  68 +/*!
  69 + * Radio FSK packet handler state
  70 + */
  71 +typedef struct
  72 +{
  73 + uint8_t PreambleDetected;
  74 + uint8_t SyncWordDetected;
  75 + int8_t RssiValue;
  76 + int32_t AfcValue;
  77 + uint8_t RxGain;
  78 + uint16_t Size;
  79 + uint16_t NbBytes;
  80 + uint8_t FifoThresh;
  81 + uint8_t ChunkSize;
  82 +}RadioFskPacketHandler_t;
  83 +
  84 +/*!
  85 + * Radio LoRa modem parameters
  86 + */
  87 +typedef struct
  88 +{
  89 + int8_t Power;
  90 + uint32_t Bandwidth;
  91 + uint32_t Datarate;
  92 + bool LowDatarateOptimize;
  93 + uint8_t Coderate;
  94 + uint16_t PreambleLen;
  95 + bool FixLen;
  96 + uint8_t PayloadLen;
  97 + bool CrcOn;
  98 + bool FreqHopOn;
  99 + uint8_t HopPeriod;
  100 + bool IqInverted;
  101 + bool RxContinuous;
  102 + uint32_t TxTimeout;
  103 + bool PublicNetwork;
  104 +}RadioLoRaSettings_t;
  105 +
  106 +/*!
  107 + * Radio LoRa packet handler state
  108 + */
  109 +typedef struct
  110 +{
  111 + int8_t SnrValue;
  112 + int8_t RssiValue;
  113 + uint8_t Size;
  114 +}RadioLoRaPacketHandler_t;
  115 +
  116 +/*!
  117 + * Radio Settings
  118 + */
  119 +typedef struct
  120 +{
  121 + RadioState State;
  122 + ModemType Modem;
  123 + uint32_t Channel;
  124 + RadioFskSettings_t Fsk;
  125 + RadioFskPacketHandler_t FskPacketHandler;
  126 + RadioLoRaSettings_t LoRa;
  127 + RadioLoRaPacketHandler_t LoRaPacketHandler;
  128 +}RadioSettings_t;
  129 +
  130 +
  131 +#endif //__ENUMS_H__
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emetteur/SX1276Lib/radio/radio.cpp 0 → 100644
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  1 +/*
  2 + / _____) _ | |
  3 +( (____ _____ ____ _| |_ _____ ____| |__
  4 + \____ \| ___ | (_ _) ___ |/ ___) _ \
  5 + _____) ) ____| | | || |_| ____( (___| | | |
  6 +(______/|_____)_|_|_| \__)_____)\____)_| |_|
  7 + (C) 2014 Semtech
  8 +
  9 +Description: Interface for the radios, contains the main functions that a radio needs, and 5 callback functions
  10 +
  11 +License: Revised BSD License, see LICENSE.TXT file include in the project
  12 +
  13 +Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
  14 +*/
  15 +#include "radio.h"
  16 +
  17 +Radio::Radio( RadioEvents_t *events )
  18 +{
  19 + this->RadioEvents = events;
  20 +}
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emetteur/SX1276Lib/radio/radio.h 0 → 100644
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  1 +/*
  2 + / _____) _ | |
  3 +( (____ _____ ____ _| |_ _____ ____| |__
  4 + \____ \| ___ | (_ _) ___ |/ ___) _ \
  5 + _____) ) ____| | | || |_| ____( (___| | | |
  6 +(______/|_____)_|_|_| \__)_____)\____)_| |_|
  7 + (C) 2014 Semtech
  8 +
  9 +Description: Interface for the radios, contains the main functions that a radio needs, and 5 callback functions
  10 +
  11 +License: Revised BSD License, see LICENSE.TXT file include in the project
  12 +
  13 +Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
  14 +*/
  15 +#ifndef __RADIO_H__
  16 +#define __RADIO_H__
  17 +
  18 +#include "mbed.h"
  19 +
  20 +#include "./enums/enums.h"
  21 +
  22 +/*!
  23 + * @brief Radio driver callback functions
  24 + */
  25 +typedef struct
  26 +{
  27 + /*!
  28 + * @brief Tx Done callback prototype.
  29 + */
  30 + void ( *TxDone )( void );
  31 + /*!
  32 + * @brief Tx Timeout callback prototype.
  33 + */
  34 + void ( *TxTimeout )( void );
  35 + /*!
  36 + * @brief Rx Done callback prototype.
  37 + *
  38 + * @param [IN] payload Received buffer pointer
  39 + * @param [IN] size Received buffer size
  40 + * @param [IN] rssi RSSI value computed while receiving the frame [dBm]
  41 + * @param [IN] snr Raw SNR value given by the radio hardware
  42 + * FSK : N/A ( set to 0 )
  43 + * LoRa: SNR value in dB
  44 + */
  45 + void ( *RxDone )( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr );
  46 + /*!
  47 + * @brief Rx Timeout callback prototype.
  48 + */
  49 + void ( *RxTimeout )( void );
  50 + /*!
  51 + * @brief Rx Error callback prototype.
  52 + */
  53 + void ( *RxError )( void );
  54 + /*!
  55 + * \brief FHSS Change Channel callback prototype.
  56 + *
  57 + * \param [IN] currentChannel Index number of the current channel
  58 + */
  59 + void ( *FhssChangeChannel )( uint8_t currentChannel );
  60 + /*!
  61 + * @brief CAD Done callback prototype.
  62 + *
  63 + * @param [IN] channelDetected Channel Activity detected during the CAD
  64 + */
  65 + void ( *CadDone ) ( bool channelActivityDetected );
  66 +}RadioEvents_t;
  67 +
  68 +/*!
  69 + * Interface for the radios, contains the main functions that a radio needs, and 5 callback functions
  70 + */
  71 +class Radio
  72 +{
  73 +protected:
  74 + RadioEvents_t* RadioEvents;
  75 +
  76 +public:
  77 + //-------------------------------------------------------------------------
  78 + // Constructor
  79 + //-------------------------------------------------------------------------
  80 + /*!
  81 + * @brief Constructor of the radio object, the parameters are the callback functions described in the header.
  82 + *
  83 + * @param [IN] events Structure containing the driver callback functions
  84 + */
  85 + Radio( RadioEvents_t *events );
  86 + virtual ~Radio( ) {};
  87 +
  88 + //-------------------------------------------------------------------------
  89 + // Pure virtual functions
  90 + //-------------------------------------------------------------------------
  91 + /*!
  92 + * @brief Initializes the radio
  93 + *
  94 + * @param [IN] events Structure containing the driver callback functions
  95 + */
  96 + virtual void Init( RadioEvents_t *events ) = 0;
  97 + /*!
  98 + * @brief Return current radio status
  99 + *
  100 + * @param status Radio status.[RF_IDLE, RF_RX_RUNNING, RF_TX_RUNNING]
  101 + */
  102 + virtual RadioState GetStatus( void ) = 0;
  103 + /*!
  104 + * @brief Configures the radio with the given modem
  105 + *
  106 + * @param [IN] modem Modem to be used [0: FSK, 1: LoRa]
  107 + */
  108 + virtual void SetModem( RadioModems_t modem ) = 0;
  109 + /*!
  110 + * @brief Sets the channel frequency
  111 + *
  112 + * @param [IN] freq Channel RF frequency
  113 + */
  114 + virtual void SetChannel( uint32_t freq ) = 0;
  115 + /*!
  116 + * @brief Sets the channels configuration
  117 + *
  118 + * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
  119 + * @param [IN] freq Channel RF frequency
  120 + * @param [IN] rssiThresh RSSI threshold
  121 + *
  122 + * @retval isFree [true: Channel is free, false: Channel is not free]
  123 + */
  124 + virtual bool IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh ) = 0;
  125 + /*!
  126 + * @brief Generates a 32 bits random value based on the RSSI readings
  127 + *
  128 + * \remark This function sets the radio in LoRa modem mode and disables
  129 + * all interrupts.
  130 + * After calling this function either Radio.SetRxConfig or
  131 + * Radio.SetTxConfig functions must be called.
  132 + *
  133 + * @retval randomValue 32 bits random value
  134 + */
  135 + virtual uint32_t Random( void )= 0;
  136 + /*!
  137 + * @brief Sets the reception parameters
  138 + *
  139 + * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
  140 + * @param [IN] bandwidth Sets the bandwidth
  141 + * FSK : >= 2600 and <= 250000 Hz
  142 + * LoRa: [0: 125 kHz, 1: 250 kHz,
  143 + * 2: 500 kHz, 3: Reserved]
  144 + * @param [IN] datarate Sets the Datarate
  145 + * FSK : 600..300000 bits/s
  146 + * LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
  147 + * 10: 1024, 11: 2048, 12: 4096 chips]
  148 + * @param [IN] coderate Sets the coding rate ( LoRa only )
  149 + * FSK : N/A ( set to 0 )
  150 + * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
  151 + * @param [IN] bandwidthAfc Sets the AFC Bandwidth ( FSK only )
  152 + * FSK : >= 2600 and <= 250000 Hz
  153 + * LoRa: N/A ( set to 0 )
  154 + * @param [IN] preambleLen Sets the Preamble length ( LoRa only )
  155 + * FSK : N/A ( set to 0 )
  156 + * LoRa: Length in symbols ( the hardware adds 4 more symbols )
  157 + * @param [IN] symbTimeout Sets the RxSingle timeout value
  158 + * FSK : timeout number of bytes
  159 + * LoRa: timeout in symbols
  160 + * @param [IN] fixLen Fixed length packets [0: variable, 1: fixed]
  161 + * @param [IN] payloadLen Sets payload length when fixed lenght is used
  162 + * @param [IN] crcOn Enables/Disables the CRC [0: OFF, 1: ON]
  163 + * @param [IN] freqHopOn Enables disables the intra-packet frequency hopping [0: OFF, 1: ON] (LoRa only)
  164 + * @param [IN] hopPeriod Number of symbols bewteen each hop (LoRa only)
  165 + * @param [IN] iqInverted Inverts IQ signals ( LoRa only )
  166 + * FSK : N/A ( set to 0 )
  167 + * LoRa: [0: not inverted, 1: inverted]
  168 + * @param [IN] rxContinuous Sets the reception in continuous mode
  169 + * [false: single mode, true: continuous mode]
  170 + */
  171 + virtual void SetRxConfig ( RadioModems_t modem, uint32_t bandwidth,
  172 + uint32_t datarate, uint8_t coderate,
  173 + uint32_t bandwidthAfc, uint16_t preambleLen,
  174 + uint16_t symbTimeout, bool fixLen,
  175 + uint8_t payloadLen,
  176 + bool crcOn, bool freqHopOn, uint8_t hopPeriod,
  177 + bool iqInverted, bool rxContinuous ) = 0;
  178 + /*!
  179 + * @brief Sets the transmission parameters
  180 + *
  181 + * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
  182 + * @param [IN] power Sets the output power [dBm]
  183 + * @param [IN] fdev Sets the frequency deviation ( FSK only )
  184 + * FSK : [Hz]
  185 + * LoRa: 0
  186 + * @param [IN] bandwidth Sets the bandwidth ( LoRa only )
  187 + * FSK : 0
  188 + * LoRa: [0: 125 kHz, 1: 250 kHz,
  189 + * 2: 500 kHz, 3: Reserved]
  190 + * @param [IN] datarate Sets the Datarate
  191 + * FSK : 600..300000 bits/s
  192 + * LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
  193 + * 10: 1024, 11: 2048, 12: 4096 chips]
  194 + * @param [IN] coderate Sets the coding rate ( LoRa only )
  195 + * FSK : N/A ( set to 0 )
  196 + * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
  197 + * @param [IN] preambleLen Sets the preamble length
  198 + * @param [IN] fixLen Fixed length packets [0: variable, 1: fixed]
  199 + * @param [IN] crcOn Enables disables the CRC [0: OFF, 1: ON]
  200 + * @param [IN] freqHopOn Enables disables the intra-packet frequency hopping [0: OFF, 1: ON] (LoRa only)
  201 + * @param [IN] hopPeriod Number of symbols bewteen each hop (LoRa only)
  202 + * @param [IN] iqInverted Inverts IQ signals ( LoRa only )
  203 + * FSK : N/A ( set to 0 )
  204 + * LoRa: [0: not inverted, 1: inverted]
  205 + * @param [IN] timeout Transmission timeout [us]
  206 + */
  207 + virtual void SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
  208 + uint32_t bandwidth, uint32_t datarate,
  209 + uint8_t coderate, uint16_t preambleLen,
  210 + bool fixLen, bool crcOn, bool freqHopOn,
  211 + uint8_t hopPeriod, bool iqInverted, uint32_t timeout ) = 0;
  212 + /*!
  213 + * @brief Checks if the given RF frequency is supported by the hardware
  214 + *
  215 + * @param [IN] frequency RF frequency to be checked
  216 + * @retval isSupported [true: supported, false: unsupported]
  217 + */
  218 + virtual bool CheckRfFrequency( uint32_t frequency ) = 0;
  219 + /*!
  220 + * @brief Computes the packet time on air for the given payload
  221 + *
  222 + * \Remark Can only be called once SetRxConfig or SetTxConfig have been called
  223 + *
  224 + * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
  225 + * @param [IN] pktLen Packet payload length
  226 + *
  227 + * @retval airTime Computed airTime for the given packet payload length
  228 + */
  229 + virtual uint32_t TimeOnAir ( RadioModems_t modem, uint8_t pktLen ) = 0;
  230 + /*!
  231 + * @brief Sends the buffer of size. Prepares the packet to be sent and sets
  232 + * the radio in transmission
  233 + *
  234 + * @param [IN]: buffer Buffer pointer
  235 + * @param [IN]: size Buffer size
  236 + */
  237 + virtual void Send( uint8_t *buffer, uint8_t size ) = 0;
  238 + /*!
  239 + * @brief Sets the radio in sleep mode
  240 + */
  241 + virtual void Sleep( void ) = 0;
  242 + /*!
  243 + * @brief Sets the radio in standby mode
  244 + */
  245 + virtual void Standby( void ) = 0;
  246 + /*!
  247 + * @brief Sets the radio in CAD mode
  248 + */
  249 + virtual void StartCad( void ) = 0;
  250 + /*!
  251 + * @brief Sets the radio in reception mode for the given time
  252 + * @param [IN] timeout Reception timeout [us]
  253 + * [0: continuous, others timeout]
  254 + */
  255 + virtual void Rx( uint32_t timeout ) = 0;
  256 + /*!
  257 + * @brief Sets the radio in transmission mode for the given time
  258 + * @param [IN] timeout Transmission timeout [us]
  259 + * [0: continuous, others timeout]
  260 + */
  261 + virtual void Tx( uint32_t timeout ) = 0;
  262 + /*!
  263 + * @brief Sets the radio in continuous wave transmission mode
  264 + *
  265 + * @param [IN]: freq Channel RF frequency
  266 + * @param [IN]: power Sets the output power [dBm]
  267 + * @param [IN]: time Transmission mode timeout [s]
  268 + */
  269 + virtual void SetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time ) = 0;
  270 + /*!
  271 + * @brief Reads the current RSSI value
  272 + *
  273 + * @retval rssiValue Current RSSI value in [dBm]
  274 + */
  275 + virtual int16_t GetRssi ( RadioModems_t modem ) = 0;
  276 + /*!
  277 + * @brief Writes the radio register at the specified address
  278 + *
  279 + * @param [IN]: addr Register address
  280 + * @param [IN]: data New register value
  281 + */
  282 + virtual void Write ( uint8_t addr, uint8_t data ) = 0;
  283 + /*!
  284 + * @brief Reads the radio register at the specified address
  285 + *
  286 + * @param [IN]: addr Register address
  287 + * @retval data Register value
  288 + */
  289 + virtual uint8_t Read ( uint8_t addr ) = 0;
  290 + /*!
  291 + * @brief Writes multiple radio registers starting at address
  292 + *
  293 + * @param [IN] addr First Radio register address
  294 + * @param [IN] buffer Buffer containing the new register's values
  295 + * @param [IN] size Number of registers to be written
  296 + */
  297 + virtual void Write( uint8_t addr, uint8_t *buffer, uint8_t size ) = 0;
  298 + /*!
  299 + * @brief Reads multiple radio registers starting at address
  300 + *
  301 + * @param [IN] addr First Radio register address
  302 + * @param [OUT] buffer Buffer where to copy the registers data
  303 + * @param [IN] size Number of registers to be read
  304 + */
  305 + virtual void Read ( uint8_t addr, uint8_t *buffer, uint8_t size ) = 0;
  306 + /*!
  307 + * @brief Writes the buffer contents to the Radio FIFO
  308 + *
  309 + * @param [IN] buffer Buffer containing data to be put on the FIFO.
  310 + * @param [IN] size Number of bytes to be written to the FIFO
  311 + */
  312 + virtual void WriteFifo( uint8_t *buffer, uint8_t size ) = 0;
  313 + /*!
  314 + * @brief Reads the contents of the Radio FIFO
  315 + *
  316 + * @param [OUT] buffer Buffer where to copy the FIFO read data.
  317 + * @param [IN] size Number of bytes to be read from the FIFO
  318 + */
  319 + virtual void ReadFifo( uint8_t *buffer, uint8_t size ) = 0;
  320 + /*!
  321 + * @brief Sets the maximum payload length.
  322 + *
  323 + * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
  324 + * @param [IN] max Maximum payload length in bytes
  325 + */
  326 + virtual void SetMaxPayloadLength( RadioModems_t modem, uint8_t max ) = 0;
  327 + /*!
  328 + * @brief Sets the network to public or private. Updates the sync byte.
  329 + *
  330 + * @remark Applies to LoRa modem only
  331 + *
  332 + * @param [IN] enable if true, it enables a public network
  333 + */
  334 + virtual void SetPublicNetwork( bool enable ) = 0;
  335 +};
  336 +
  337 +#endif // __RADIO_H__
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emetteur/SX1276Lib/registers/sx1276Regs-Fsk.h 0 → 100644
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  1 +/*
  2 + / _____) _ | |
  3 +( (____ _____ ____ _| |_ _____ ____| |__
  4 + \____ \| ___ | (_ _) ___ |/ ___) _ \
  5 + _____) ) ____| | | || |_| ____( (___| | | |
  6 +(______/|_____)_|_|_| \__)_____)\____)_| |_|
  7 + (C) 2014 Semtech
  8 +
  9 +Description: SX1276 FSK modem registers and bits definitions
  10 +
  11 +License: Revised BSD License, see LICENSE.TXT file include in the project
  12 +
  13 +Maintainer: Miguel Luis and Gregory Cristian
  14 +*/
  15 +#ifndef __SX1276_REGS_FSK_H__
  16 +#define __SX1276_REGS_FSK_H__
  17 +
  18 +/*!
  19 + * ============================================================================
  20 + * SX1276 Internal registers Address
  21 + * ============================================================================
  22 + */
  23 +#define REG_FIFO 0x00
  24 +// Common settings
  25 +#define REG_OPMODE 0x01
  26 +#define REG_BITRATEMSB 0x02
  27 +#define REG_BITRATELSB 0x03
  28 +#define REG_FDEVMSB 0x04
  29 +#define REG_FDEVLSB 0x05
  30 +#define REG_FRFMSB 0x06
  31 +#define REG_FRFMID 0x07
  32 +#define REG_FRFLSB 0x08
  33 +// Tx settings
  34 +#define REG_PACONFIG 0x09
  35 +#define REG_PARAMP 0x0A
  36 +#define REG_OCP 0x0B
  37 +// Rx settings
  38 +#define REG_LNA 0x0C
  39 +#define REG_RXCONFIG 0x0D
  40 +#define REG_RSSICONFIG 0x0E
  41 +#define REG_RSSICOLLISION 0x0F
  42 +#define REG_RSSITHRESH 0x10
  43 +#define REG_RSSIVALUE 0x11
  44 +#define REG_RXBW 0x12
  45 +#define REG_AFCBW 0x13
  46 +#define REG_OOKPEAK 0x14
  47 +#define REG_OOKFIX 0x15
  48 +#define REG_OOKAVG 0x16
  49 +#define REG_RES17 0x17
  50 +#define REG_RES18 0x18
  51 +#define REG_RES19 0x19
  52 +#define REG_AFCFEI 0x1A
  53 +#define REG_AFCMSB 0x1B
  54 +#define REG_AFCLSB 0x1C
  55 +#define REG_FEIMSB 0x1D
  56 +#define REG_FEILSB 0x1E
  57 +#define REG_PREAMBLEDETECT 0x1F
  58 +#define REG_RXTIMEOUT1 0x20
  59 +#define REG_RXTIMEOUT2 0x21
  60 +#define REG_RXTIMEOUT3 0x22
  61 +#define REG_RXDELAY 0x23
  62 +// Oscillator settings
  63 +#define REG_OSC 0x24
  64 +// Packet handler settings
  65 +#define REG_PREAMBLEMSB 0x25
  66 +#define REG_PREAMBLELSB 0x26
  67 +#define REG_SYNCCONFIG 0x27
  68 +#define REG_SYNCVALUE1 0x28
  69 +#define REG_SYNCVALUE2 0x29
  70 +#define REG_SYNCVALUE3 0x2A
  71 +#define REG_SYNCVALUE4 0x2B
  72 +#define REG_SYNCVALUE5 0x2C
  73 +#define REG_SYNCVALUE6 0x2D
  74 +#define REG_SYNCVALUE7 0x2E
  75 +#define REG_SYNCVALUE8 0x2F
  76 +#define REG_PACKETCONFIG1 0x30
  77 +#define REG_PACKETCONFIG2 0x31
  78 +#define REG_PAYLOADLENGTH 0x32
  79 +#define REG_NODEADRS 0x33
  80 +#define REG_BROADCASTADRS 0x34
  81 +#define REG_FIFOTHRESH 0x35
  82 +// SM settings
  83 +#define REG_SEQCONFIG1 0x36
  84 +#define REG_SEQCONFIG2 0x37
  85 +#define REG_TIMERRESOL 0x38
  86 +#define REG_TIMER1COEF 0x39
  87 +#define REG_TIMER2COEF 0x3A
  88 +// Service settings
  89 +#define REG_IMAGECAL 0x3B
  90 +#define REG_TEMP 0x3C
  91 +#define REG_LOWBAT 0x3D
  92 +// Status
  93 +#define REG_IRQFLAGS1 0x3E
  94 +#define REG_IRQFLAGS2 0x3F
  95 +// I/O settings
  96 +#define REG_DIOMAPPING1 0x40
  97 +#define REG_DIOMAPPING2 0x41
  98 +// Version
  99 +#define REG_VERSION 0x42
  100 +// Additional settings
  101 +#define REG_PLLHOP 0x44
  102 +#define REG_TCXO 0x4B
  103 +#define REG_PADAC 0x4D
  104 +#define REG_FORMERTEMP 0x5B
  105 +#define REG_BITRATEFRAC 0x5D
  106 +#define REG_AGCREF 0x61
  107 +#define REG_AGCTHRESH1 0x62
  108 +#define REG_AGCTHRESH2 0x63
  109 +#define REG_AGCTHRESH3 0x64
  110 +#define REG_PLL 0x70
  111 +
  112 +/*!
  113 + * ============================================================================
  114 + * SX1276 FSK bits control definition
  115 + * ============================================================================
  116 + */
  117 +
  118 +/*!
  119 + * RegFifo
  120 + */
  121 +
  122 +/*!
  123 + * RegOpMode
  124 + */
  125 +#define RF_OPMODE_LONGRANGEMODE_MASK 0x7F
  126 +#define RF_OPMODE_LONGRANGEMODE_OFF 0x00
  127 +#define RF_OPMODE_LONGRANGEMODE_ON 0x80
  128 +
  129 +#define RF_OPMODE_MODULATIONTYPE_MASK 0x9F
  130 +#define RF_OPMODE_MODULATIONTYPE_FSK 0x00 // Default
  131 +#define RF_OPMODE_MODULATIONTYPE_OOK 0x20
  132 +
  133 +#define RF_OPMODE_MODULATIONSHAPING_MASK 0xE7
  134 +#define RF_OPMODE_MODULATIONSHAPING_00 0x00 // Default
  135 +#define RF_OPMODE_MODULATIONSHAPING_01 0x08
  136 +#define RF_OPMODE_MODULATIONSHAPING_10 0x10
  137 +#define RF_OPMODE_MODULATIONSHAPING_11 0x18
  138 +
  139 +#define RF_OPMODE_MASK 0xF8
  140 +#define RF_OPMODE_SLEEP 0x00
  141 +#define RF_OPMODE_STANDBY 0x01 // Default
  142 +#define RF_OPMODE_SYNTHESIZER_TX 0x02
  143 +#define RF_OPMODE_TRANSMITTER 0x03
  144 +#define RF_OPMODE_SYNTHESIZER_RX 0x04
  145 +#define RF_OPMODE_RECEIVER 0x05
  146 +
  147 +/*!
  148 + * RegBitRate (bits/sec)
  149 + */
  150 +#define RF_BITRATEMSB_1200_BPS 0x68
  151 +#define RF_BITRATELSB_1200_BPS 0x2B
  152 +#define RF_BITRATEMSB_2400_BPS 0x34
  153 +#define RF_BITRATELSB_2400_BPS 0x15
  154 +#define RF_BITRATEMSB_4800_BPS 0x1A // Default
  155 +#define RF_BITRATELSB_4800_BPS 0x0B // Default
  156 +#define RF_BITRATEMSB_9600_BPS 0x0D
  157 +#define RF_BITRATELSB_9600_BPS 0x05
  158 +#define RF_BITRATEMSB_15000_BPS 0x08
  159 +#define RF_BITRATELSB_15000_BPS 0x55
  160 +#define RF_BITRATEMSB_19200_BPS 0x06
  161 +#define RF_BITRATELSB_19200_BPS 0x83
  162 +#define RF_BITRATEMSB_38400_BPS 0x03
  163 +#define RF_BITRATELSB_38400_BPS 0x41
  164 +#define RF_BITRATEMSB_76800_BPS 0x01
  165 +#define RF_BITRATELSB_76800_BPS 0xA1
  166 +#define RF_BITRATEMSB_153600_BPS 0x00
  167 +#define RF_BITRATELSB_153600_BPS 0xD0
  168 +#define RF_BITRATEMSB_57600_BPS 0x02
  169 +#define RF_BITRATELSB_57600_BPS 0x2C
  170 +#define RF_BITRATEMSB_115200_BPS 0x01
  171 +#define RF_BITRATELSB_115200_BPS 0x16
  172 +#define RF_BITRATEMSB_12500_BPS 0x0A
  173 +#define RF_BITRATELSB_12500_BPS 0x00
  174 +#define RF_BITRATEMSB_25000_BPS 0x05
  175 +#define RF_BITRATELSB_25000_BPS 0x00
  176 +#define RF_BITRATEMSB_50000_BPS 0x02
  177 +#define RF_BITRATELSB_50000_BPS 0x80
  178 +#define RF_BITRATEMSB_100000_BPS 0x01
  179 +#define RF_BITRATELSB_100000_BPS 0x40
  180 +#define RF_BITRATEMSB_150000_BPS 0x00
  181 +#define RF_BITRATELSB_150000_BPS 0xD5
  182 +#define RF_BITRATEMSB_200000_BPS 0x00
  183 +#define RF_BITRATELSB_200000_BPS 0xA0
  184 +#define RF_BITRATEMSB_250000_BPS 0x00
  185 +#define RF_BITRATELSB_250000_BPS 0x80
  186 +#define RF_BITRATEMSB_32768_BPS 0x03
  187 +#define RF_BITRATELSB_32768_BPS 0xD1
  188 +
  189 +/*!
  190 + * RegFdev (Hz)
  191 + */
  192 +#define RF_FDEVMSB_2000_HZ 0x00
  193 +#define RF_FDEVLSB_2000_HZ 0x21
  194 +#define RF_FDEVMSB_5000_HZ 0x00 // Default
  195 +#define RF_FDEVLSB_5000_HZ 0x52 // Default
  196 +#define RF_FDEVMSB_10000_HZ 0x00
  197 +#define RF_FDEVLSB_10000_HZ 0xA4
  198 +#define RF_FDEVMSB_15000_HZ 0x00
  199 +#define RF_FDEVLSB_15000_HZ 0xF6
  200 +#define RF_FDEVMSB_20000_HZ 0x01
  201 +#define RF_FDEVLSB_20000_HZ 0x48
  202 +#define RF_FDEVMSB_25000_HZ 0x01
  203 +#define RF_FDEVLSB_25000_HZ 0x9A
  204 +#define RF_FDEVMSB_30000_HZ 0x01
  205 +#define RF_FDEVLSB_30000_HZ 0xEC
  206 +#define RF_FDEVMSB_35000_HZ 0x02
  207 +#define RF_FDEVLSB_35000_HZ 0x3D
  208 +#define RF_FDEVMSB_40000_HZ 0x02
  209 +#define RF_FDEVLSB_40000_HZ 0x8F
  210 +#define RF_FDEVMSB_45000_HZ 0x02
  211 +#define RF_FDEVLSB_45000_HZ 0xE1
  212 +#define RF_FDEVMSB_50000_HZ 0x03
  213 +#define RF_FDEVLSB_50000_HZ 0x33
  214 +#define RF_FDEVMSB_55000_HZ 0x03
  215 +#define RF_FDEVLSB_55000_HZ 0x85
  216 +#define RF_FDEVMSB_60000_HZ 0x03
  217 +#define RF_FDEVLSB_60000_HZ 0xD7
  218 +#define RF_FDEVMSB_65000_HZ 0x04
  219 +#define RF_FDEVLSB_65000_HZ 0x29
  220 +#define RF_FDEVMSB_70000_HZ 0x04
  221 +#define RF_FDEVLSB_70000_HZ 0x7B
  222 +#define RF_FDEVMSB_75000_HZ 0x04
  223 +#define RF_FDEVLSB_75000_HZ 0xCD
  224 +#define RF_FDEVMSB_80000_HZ 0x05
  225 +#define RF_FDEVLSB_80000_HZ 0x1F
  226 +#define RF_FDEVMSB_85000_HZ 0x05
  227 +#define RF_FDEVLSB_85000_HZ 0x71
  228 +#define RF_FDEVMSB_90000_HZ 0x05
  229 +#define RF_FDEVLSB_90000_HZ 0xC3
  230 +#define RF_FDEVMSB_95000_HZ 0x06
  231 +#define RF_FDEVLSB_95000_HZ 0x14
  232 +#define RF_FDEVMSB_100000_HZ 0x06
  233 +#define RF_FDEVLSB_100000_HZ 0x66
  234 +#define RF_FDEVMSB_110000_HZ 0x07
  235 +#define RF_FDEVLSB_110000_HZ 0x0A
  236 +#define RF_FDEVMSB_120000_HZ 0x07
  237 +#define RF_FDEVLSB_120000_HZ 0xAE
  238 +#define RF_FDEVMSB_130000_HZ 0x08
  239 +#define RF_FDEVLSB_130000_HZ 0x52
  240 +#define RF_FDEVMSB_140000_HZ 0x08
  241 +#define RF_FDEVLSB_140000_HZ 0xF6
  242 +#define RF_FDEVMSB_150000_HZ 0x09
  243 +#define RF_FDEVLSB_150000_HZ 0x9A
  244 +#define RF_FDEVMSB_160000_HZ 0x0A
  245 +#define RF_FDEVLSB_160000_HZ 0x3D
  246 +#define RF_FDEVMSB_170000_HZ 0x0A
  247 +#define RF_FDEVLSB_170000_HZ 0xE1
  248 +#define RF_FDEVMSB_180000_HZ 0x0B
  249 +#define RF_FDEVLSB_180000_HZ 0x85
  250 +#define RF_FDEVMSB_190000_HZ 0x0C
  251 +#define RF_FDEVLSB_190000_HZ 0x29
  252 +#define RF_FDEVMSB_200000_HZ 0x0C
  253 +#define RF_FDEVLSB_200000_HZ 0xCD
  254 +
  255 +/*!
  256 + * RegFrf (MHz)
  257 + */
  258 +#define RF_FRFMSB_863_MHZ 0xD7
  259 +#define RF_FRFMID_863_MHZ 0xC0
  260 +#define RF_FRFLSB_863_MHZ 0x00
  261 +#define RF_FRFMSB_864_MHZ 0xD8
  262 +#define RF_FRFMID_864_MHZ 0x00
  263 +#define RF_FRFLSB_864_MHZ 0x00
  264 +#define RF_FRFMSB_865_MHZ 0xD8
  265 +#define RF_FRFMID_865_MHZ 0x40
  266 +#define RF_FRFLSB_865_MHZ 0x00
  267 +#define RF_FRFMSB_866_MHZ 0xD8
  268 +#define RF_FRFMID_866_MHZ 0x80
  269 +#define RF_FRFLSB_866_MHZ 0x00
  270 +#define RF_FRFMSB_867_MHZ 0xD8
  271 +#define RF_FRFMID_867_MHZ 0xC0
  272 +#define RF_FRFLSB_867_MHZ 0x00
  273 +#define RF_FRFMSB_868_MHZ 0xD9
  274 +#define RF_FRFMID_868_MHZ 0x00
  275 +#define RF_FRFLSB_868_MHZ 0x00
  276 +#define RF_FRFMSB_869_MHZ 0xD9
  277 +#define RF_FRFMID_869_MHZ 0x40
  278 +#define RF_FRFLSB_869_MHZ 0x00
  279 +#define RF_FRFMSB_870_MHZ 0xD9
  280 +#define RF_FRFMID_870_MHZ 0x80
  281 +#define RF_FRFLSB_870_MHZ 0x00
  282 +
  283 +#define RF_FRFMSB_902_MHZ 0xE1
  284 +#define RF_FRFMID_902_MHZ 0x80
  285 +#define RF_FRFLSB_902_MHZ 0x00
  286 +#define RF_FRFMSB_903_MHZ 0xE1
  287 +#define RF_FRFMID_903_MHZ 0xC0
  288 +#define RF_FRFLSB_903_MHZ 0x00
  289 +#define RF_FRFMSB_904_MHZ 0xE2
  290 +#define RF_FRFMID_904_MHZ 0x00
  291 +#define RF_FRFLSB_904_MHZ 0x00
  292 +#define RF_FRFMSB_905_MHZ 0xE2
  293 +#define RF_FRFMID_905_MHZ 0x40
  294 +#define RF_FRFLSB_905_MHZ 0x00
  295 +#define RF_FRFMSB_906_MHZ 0xE2
  296 +#define RF_FRFMID_906_MHZ 0x80
  297 +#define RF_FRFLSB_906_MHZ 0x00
  298 +#define RF_FRFMSB_907_MHZ 0xE2
  299 +#define RF_FRFMID_907_MHZ 0xC0
  300 +#define RF_FRFLSB_907_MHZ 0x00
  301 +#define RF_FRFMSB_908_MHZ 0xE3
  302 +#define RF_FRFMID_908_MHZ 0x00
  303 +#define RF_FRFLSB_908_MHZ 0x00
  304 +#define RF_FRFMSB_909_MHZ 0xE3
  305 +#define RF_FRFMID_909_MHZ 0x40
  306 +#define RF_FRFLSB_909_MHZ 0x00
  307 +#define RF_FRFMSB_910_MHZ 0xE3
  308 +#define RF_FRFMID_910_MHZ 0x80
  309 +#define RF_FRFLSB_910_MHZ 0x00
  310 +#define RF_FRFMSB_911_MHZ 0xE3
  311 +#define RF_FRFMID_911_MHZ 0xC0
  312 +#define RF_FRFLSB_911_MHZ 0x00
  313 +#define RF_FRFMSB_912_MHZ 0xE4
  314 +#define RF_FRFMID_912_MHZ 0x00
  315 +#define RF_FRFLSB_912_MHZ 0x00
  316 +#define RF_FRFMSB_913_MHZ 0xE4
  317 +#define RF_FRFMID_913_MHZ 0x40
  318 +#define RF_FRFLSB_913_MHZ 0x00
  319 +#define RF_FRFMSB_914_MHZ 0xE4
  320 +#define RF_FRFMID_914_MHZ 0x80
  321 +#define RF_FRFLSB_914_MHZ 0x00
  322 +#define RF_FRFMSB_915_MHZ 0xE4 // Default
  323 +#define RF_FRFMID_915_MHZ 0xC0 // Default
  324 +#define RF_FRFLSB_915_MHZ 0x00 // Default
  325 +#define RF_FRFMSB_916_MHZ 0xE5
  326 +#define RF_FRFMID_916_MHZ 0x00
  327 +#define RF_FRFLSB_916_MHZ 0x00
  328 +#define RF_FRFMSB_917_MHZ 0xE5
  329 +#define RF_FRFMID_917_MHZ 0x40
  330 +#define RF_FRFLSB_917_MHZ 0x00
  331 +#define RF_FRFMSB_918_MHZ 0xE5
  332 +#define RF_FRFMID_918_MHZ 0x80
  333 +#define RF_FRFLSB_918_MHZ 0x00
  334 +#define RF_FRFMSB_919_MHZ 0xE5
  335 +#define RF_FRFMID_919_MHZ 0xC0
  336 +#define RF_FRFLSB_919_MHZ 0x00
  337 +#define RF_FRFMSB_920_MHZ 0xE6
  338 +#define RF_FRFMID_920_MHZ 0x00
  339 +#define RF_FRFLSB_920_MHZ 0x00
  340 +#define RF_FRFMSB_921_MHZ 0xE6
  341 +#define RF_FRFMID_921_MHZ 0x40
  342 +#define RF_FRFLSB_921_MHZ 0x00
  343 +#define RF_FRFMSB_922_MHZ 0xE6
  344 +#define RF_FRFMID_922_MHZ 0x80
  345 +#define RF_FRFLSB_922_MHZ 0x00
  346 +#define RF_FRFMSB_923_MHZ 0xE6
  347 +#define RF_FRFMID_923_MHZ 0xC0
  348 +#define RF_FRFLSB_923_MHZ 0x00
  349 +#define RF_FRFMSB_924_MHZ 0xE7
  350 +#define RF_FRFMID_924_MHZ 0x00
  351 +#define RF_FRFLSB_924_MHZ 0x00
  352 +#define RF_FRFMSB_925_MHZ 0xE7
  353 +#define RF_FRFMID_925_MHZ 0x40
  354 +#define RF_FRFLSB_925_MHZ 0x00
  355 +#define RF_FRFMSB_926_MHZ 0xE7
  356 +#define RF_FRFMID_926_MHZ 0x80
  357 +#define RF_FRFLSB_926_MHZ 0x00
  358 +#define RF_FRFMSB_927_MHZ 0xE7
  359 +#define RF_FRFMID_927_MHZ 0xC0
  360 +#define RF_FRFLSB_927_MHZ 0x00
  361 +#define RF_FRFMSB_928_MHZ 0xE8
  362 +#define RF_FRFMID_928_MHZ 0x00
  363 +#define RF_FRFLSB_928_MHZ 0x00
  364 +
  365 +/*!
  366 + * RegPaConfig
  367 + */
  368 +#define RF_PACONFIG_PASELECT_MASK 0x7F
  369 +#define RF_PACONFIG_PASELECT_PABOOST 0x80
  370 +#define RF_PACONFIG_PASELECT_RFO 0x00 // Default
  371 +
  372 +#define RF_PACONFIG_MAX_POWER_MASK 0x8F
  373 +
  374 +#define RF_PACONFIG_OUTPUTPOWER_MASK 0xF0
  375 +
  376 +/*!
  377 + * RegPaRamp
  378 + */
  379 +#define RF_PARAMP_MODULATIONSHAPING_MASK 0x9F
  380 +#define RF_PARAMP_MODULATIONSHAPING_00 0x00 // Default
  381 +#define RF_PARAMP_MODULATIONSHAPING_01 0x20
  382 +#define RF_PARAMP_MODULATIONSHAPING_10 0x40
  383 +#define RF_PARAMP_MODULATIONSHAPING_11 0x60
  384 +
  385 +#define RF_PARAMP_LOWPNTXPLL_MASK 0xEF
  386 +#define RF_PARAMP_LOWPNTXPLL_OFF 0x10
  387 +#define RF_PARAMP_LOWPNTXPLL_ON 0x00 // Default
  388 +
  389 +#define RF_PARAMP_MASK 0xF0
  390 +#define RF_PARAMP_3400_US 0x00
  391 +#define RF_PARAMP_2000_US 0x01
  392 +#define RF_PARAMP_1000_US 0x02
  393 +#define RF_PARAMP_0500_US 0x03
  394 +#define RF_PARAMP_0250_US 0x04
  395 +#define RF_PARAMP_0125_US 0x05
  396 +#define RF_PARAMP_0100_US 0x06
  397 +#define RF_PARAMP_0062_US 0x07
  398 +#define RF_PARAMP_0050_US 0x08
  399 +#define RF_PARAMP_0040_US 0x09 // Default
  400 +#define RF_PARAMP_0031_US 0x0A
  401 +#define RF_PARAMP_0025_US 0x0B
  402 +#define RF_PARAMP_0020_US 0x0C
  403 +#define RF_PARAMP_0015_US 0x0D
  404 +#define RF_PARAMP_0012_US 0x0E
  405 +#define RF_PARAMP_0010_US 0x0F
  406 +
  407 +/*!
  408 + * RegOcp
  409 + */
  410 +#define RF_OCP_MASK 0xDF
  411 +#define RF_OCP_ON 0x20 // Default
  412 +#define RF_OCP_OFF 0x00
  413 +
  414 +#define RF_OCP_TRIM_MASK 0xE0
  415 +#define RF_OCP_TRIM_045_MA 0x00
  416 +#define RF_OCP_TRIM_050_MA 0x01
  417 +#define RF_OCP_TRIM_055_MA 0x02
  418 +#define RF_OCP_TRIM_060_MA 0x03
  419 +#define RF_OCP_TRIM_065_MA 0x04
  420 +#define RF_OCP_TRIM_070_MA 0x05
  421 +#define RF_OCP_TRIM_075_MA 0x06
  422 +#define RF_OCP_TRIM_080_MA 0x07
  423 +#define RF_OCP_TRIM_085_MA 0x08
  424 +#define RF_OCP_TRIM_090_MA 0x09
  425 +#define RF_OCP_TRIM_095_MA 0x0A
  426 +#define RF_OCP_TRIM_100_MA 0x0B // Default
  427 +#define RF_OCP_TRIM_105_MA 0x0C
  428 +#define RF_OCP_TRIM_110_MA 0x0D
  429 +#define RF_OCP_TRIM_115_MA 0x0E
  430 +#define RF_OCP_TRIM_120_MA 0x0F
  431 +#define RF_OCP_TRIM_130_MA 0x10
  432 +#define RF_OCP_TRIM_140_MA 0x11
  433 +#define RF_OCP_TRIM_150_MA 0x12
  434 +#define RF_OCP_TRIM_160_MA 0x13
  435 +#define RF_OCP_TRIM_170_MA 0x14
  436 +#define RF_OCP_TRIM_180_MA 0x15
  437 +#define RF_OCP_TRIM_190_MA 0x16
  438 +#define RF_OCP_TRIM_200_MA 0x17
  439 +#define RF_OCP_TRIM_210_MA 0x18
  440 +#define RF_OCP_TRIM_220_MA 0x19
  441 +#define RF_OCP_TRIM_230_MA 0x1A
  442 +#define RF_OCP_TRIM_240_MA 0x1B
  443 +
  444 +/*!
  445 + * RegLna
  446 + */
  447 +#define RF_LNA_GAIN_MASK 0x1F
  448 +#define RF_LNA_GAIN_G1 0x20 // Default
  449 +#define RF_LNA_GAIN_G2 0x40
  450 +#define RF_LNA_GAIN_G3 0x60
  451 +#define RF_LNA_GAIN_G4 0x80
  452 +#define RF_LNA_GAIN_G5 0xA0
  453 +#define RF_LNA_GAIN_G6 0xC0
  454 +
  455 +#define RF_LNA_BOOST_MASK 0xFC
  456 +#define RF_LNA_BOOST_OFF 0x00 // Default
  457 +#define RF_LNA_BOOST_ON 0x03
  458 +
  459 +/*!
  460 + * RegRxConfig
  461 + */
  462 +#define RF_RXCONFIG_RESTARTRXONCOLLISION_MASK 0x7F
  463 +#define RF_RXCONFIG_RESTARTRXONCOLLISION_ON 0x80
  464 +#define RF_RXCONFIG_RESTARTRXONCOLLISION_OFF 0x00 // Default
  465 +
  466 +#define RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK 0x40 // Write only
  467 +
  468 +#define RF_RXCONFIG_RESTARTRXWITHPLLLOCK 0x20 // Write only
  469 +
  470 +#define RF_RXCONFIG_AFCAUTO_MASK 0xEF
  471 +#define RF_RXCONFIG_AFCAUTO_ON 0x10
  472 +#define RF_RXCONFIG_AFCAUTO_OFF 0x00 // Default
  473 +
  474 +#define RF_RXCONFIG_AGCAUTO_MASK 0xF7
  475 +#define RF_RXCONFIG_AGCAUTO_ON 0x08 // Default
  476 +#define RF_RXCONFIG_AGCAUTO_OFF 0x00
  477 +
  478 +#define RF_RXCONFIG_RXTRIGER_MASK 0xF8
  479 +#define RF_RXCONFIG_RXTRIGER_OFF 0x00
  480 +#define RF_RXCONFIG_RXTRIGER_RSSI 0x01
  481 +#define RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT 0x06 // Default
  482 +#define RF_RXCONFIG_RXTRIGER_RSSI_PREAMBLEDETECT 0x07
  483 +
  484 +/*!
  485 + * RegRssiConfig
  486 + */
  487 +#define RF_RSSICONFIG_OFFSET_MASK 0x07
  488 +#define RF_RSSICONFIG_OFFSET_P_00_DB 0x00 // Default
  489 +#define RF_RSSICONFIG_OFFSET_P_01_DB 0x08
  490 +#define RF_RSSICONFIG_OFFSET_P_02_DB 0x10
  491 +#define RF_RSSICONFIG_OFFSET_P_03_DB 0x18
  492 +#define RF_RSSICONFIG_OFFSET_P_04_DB 0x20
  493 +#define RF_RSSICONFIG_OFFSET_P_05_DB 0x28
  494 +#define RF_RSSICONFIG_OFFSET_P_06_DB 0x30
  495 +#define RF_RSSICONFIG_OFFSET_P_07_DB 0x38
  496 +#define RF_RSSICONFIG_OFFSET_P_08_DB 0x40
  497 +#define RF_RSSICONFIG_OFFSET_P_09_DB 0x48
  498 +#define RF_RSSICONFIG_OFFSET_P_10_DB 0x50
  499 +#define RF_RSSICONFIG_OFFSET_P_11_DB 0x58
  500 +#define RF_RSSICONFIG_OFFSET_P_12_DB 0x60
  501 +#define RF_RSSICONFIG_OFFSET_P_13_DB 0x68
  502 +#define RF_RSSICONFIG_OFFSET_P_14_DB 0x70
  503 +#define RF_RSSICONFIG_OFFSET_P_15_DB 0x78
  504 +#define RF_RSSICONFIG_OFFSET_M_16_DB 0x80
  505 +#define RF_RSSICONFIG_OFFSET_M_15_DB 0x88
  506 +#define RF_RSSICONFIG_OFFSET_M_14_DB 0x90
  507 +#define RF_RSSICONFIG_OFFSET_M_13_DB 0x98
  508 +#define RF_RSSICONFIG_OFFSET_M_12_DB 0xA0
  509 +#define RF_RSSICONFIG_OFFSET_M_11_DB 0xA8
  510 +#define RF_RSSICONFIG_OFFSET_M_10_DB 0xB0
  511 +#define RF_RSSICONFIG_OFFSET_M_09_DB 0xB8
  512 +#define RF_RSSICONFIG_OFFSET_M_08_DB 0xC0
  513 +#define RF_RSSICONFIG_OFFSET_M_07_DB 0xC8
  514 +#define RF_RSSICONFIG_OFFSET_M_06_DB 0xD0
  515 +#define RF_RSSICONFIG_OFFSET_M_05_DB 0xD8
  516 +#define RF_RSSICONFIG_OFFSET_M_04_DB 0xE0
  517 +#define RF_RSSICONFIG_OFFSET_M_03_DB 0xE8
  518 +#define RF_RSSICONFIG_OFFSET_M_02_DB 0xF0
  519 +#define RF_RSSICONFIG_OFFSET_M_01_DB 0xF8
  520 +
  521 +#define RF_RSSICONFIG_SMOOTHING_MASK 0xF8
  522 +#define RF_RSSICONFIG_SMOOTHING_2 0x00
  523 +#define RF_RSSICONFIG_SMOOTHING_4 0x01
  524 +#define RF_RSSICONFIG_SMOOTHING_8 0x02 // Default
  525 +#define RF_RSSICONFIG_SMOOTHING_16 0x03
  526 +#define RF_RSSICONFIG_SMOOTHING_32 0x04
  527 +#define RF_RSSICONFIG_SMOOTHING_64 0x05
  528 +#define RF_RSSICONFIG_SMOOTHING_128 0x06
  529 +#define RF_RSSICONFIG_SMOOTHING_256 0x07
  530 +
  531 +/*!
  532 + * RegRssiCollision
  533 + */
  534 +#define RF_RSSICOLISION_THRESHOLD 0x0A // Default
  535 +
  536 +/*!
  537 + * RegRssiThresh
  538 + */
  539 +#define RF_RSSITHRESH_THRESHOLD 0xFF // Default
  540 +
  541 +/*!
  542 + * RegRssiValue (Read Only)
  543 + */
  544 +
  545 +/*!
  546 + * RegRxBw
  547 + */
  548 +#define RF_RXBW_MANT_MASK 0xE7
  549 +#define RF_RXBW_MANT_16 0x00
  550 +#define RF_RXBW_MANT_20 0x08
  551 +#define RF_RXBW_MANT_24 0x10 // Default
  552 +
  553 +#define RF_RXBW_EXP_MASK 0xF8
  554 +#define RF_RXBW_EXP_0 0x00
  555 +#define RF_RXBW_EXP_1 0x01
  556 +#define RF_RXBW_EXP_2 0x02
  557 +#define RF_RXBW_EXP_3 0x03
  558 +#define RF_RXBW_EXP_4 0x04
  559 +#define RF_RXBW_EXP_5 0x05 // Default
  560 +#define RF_RXBW_EXP_6 0x06
  561 +#define RF_RXBW_EXP_7 0x07
  562 +
  563 +/*!
  564 + * RegAfcBw
  565 + */
  566 +#define RF_AFCBW_MANTAFC_MASK 0xE7
  567 +#define RF_AFCBW_MANTAFC_16 0x00
  568 +#define RF_AFCBW_MANTAFC_20 0x08 // Default
  569 +#define RF_AFCBW_MANTAFC_24 0x10
  570 +
  571 +#define RF_AFCBW_EXPAFC_MASK 0xF8
  572 +#define RF_AFCBW_EXPAFC_0 0x00
  573 +#define RF_AFCBW_EXPAFC_1 0x01
  574 +#define RF_AFCBW_EXPAFC_2 0x02
  575 +#define RF_AFCBW_EXPAFC_3 0x03 // Default
  576 +#define RF_AFCBW_EXPAFC_4 0x04
  577 +#define RF_AFCBW_EXPAFC_5 0x05
  578 +#define RF_AFCBW_EXPAFC_6 0x06
  579 +#define RF_AFCBW_EXPAFC_7 0x07
  580 +
  581 +/*!
  582 + * RegOokPeak
  583 + */
  584 +#define RF_OOKPEAK_BITSYNC_MASK 0xDF // Default
  585 +#define RF_OOKPEAK_BITSYNC_ON 0x20 // Default
  586 +#define RF_OOKPEAK_BITSYNC_OFF 0x00
  587 +
  588 +#define RF_OOKPEAK_OOKTHRESHTYPE_MASK 0xE7
  589 +#define RF_OOKPEAK_OOKTHRESHTYPE_FIXED 0x00
  590 +#define RF_OOKPEAK_OOKTHRESHTYPE_PEAK 0x08 // Default
  591 +#define RF_OOKPEAK_OOKTHRESHTYPE_AVERAGE 0x10
  592 +
  593 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_MASK 0xF8
  594 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_0_5_DB 0x00 // Default
  595 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_0_DB 0x01
  596 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_5_DB 0x02
  597 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_2_0_DB 0x03
  598 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_3_0_DB 0x04
  599 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_4_0_DB 0x05
  600 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_5_0_DB 0x06
  601 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_6_0_DB 0x07
  602 +
  603 +/*!
  604 + * RegOokFix
  605 + */
  606 +#define RF_OOKFIX_OOKFIXEDTHRESHOLD 0x0C // Default
  607 +
  608 +/*!
  609 + * RegOokAvg
  610 + */
  611 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_MASK 0x1F
  612 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_000 0x00 // Default
  613 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_001 0x20
  614 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_010 0x40
  615 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_011 0x60
  616 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_100 0x80
  617 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_101 0xA0
  618 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_110 0xC0
  619 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_111 0xE0
  620 +
  621 +#define RF_OOKAVG_AVERAGEOFFSET_MASK 0xF3
  622 +#define RF_OOKAVG_AVERAGEOFFSET_0_DB 0x00 // Default
  623 +#define RF_OOKAVG_AVERAGEOFFSET_2_DB 0x04
  624 +#define RF_OOKAVG_AVERAGEOFFSET_4_DB 0x08
  625 +#define RF_OOKAVG_AVERAGEOFFSET_6_DB 0x0C
  626 +
  627 +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_MASK 0xFC
  628 +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_00 0x00
  629 +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_01 0x01
  630 +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_10 0x02 // Default
  631 +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_11 0x03
  632 +
  633 +/*!
  634 + * RegAfcFei
  635 + */
  636 +#define RF_AFCFEI_AGCSTART 0x10
  637 +
  638 +#define RF_AFCFEI_AFCCLEAR 0x02
  639 +
  640 +#define RF_AFCFEI_AFCAUTOCLEAR_MASK 0xFE
  641 +#define RF_AFCFEI_AFCAUTOCLEAR_ON 0x01
  642 +#define RF_AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default
  643 +
  644 +/*!
  645 + * RegAfcMsb (Read Only)
  646 + */
  647 +
  648 +/*!
  649 + * RegAfcLsb (Read Only)
  650 + */
  651 +
  652 +/*!
  653 + * RegFeiMsb (Read Only)
  654 + */
  655 +
  656 +/*!
  657 + * RegFeiLsb (Read Only)
  658 + */
  659 +
  660 +/*!
  661 + * RegPreambleDetect
  662 + */
  663 +#define RF_PREAMBLEDETECT_DETECTOR_MASK 0x7F
  664 +#define RF_PREAMBLEDETECT_DETECTOR_ON 0x80 // Default
  665 +#define RF_PREAMBLEDETECT_DETECTOR_OFF 0x00
  666 +
  667 +#define RF_PREAMBLEDETECT_DETECTORSIZE_MASK 0x9F
  668 +#define RF_PREAMBLEDETECT_DETECTORSIZE_1 0x00
  669 +#define RF_PREAMBLEDETECT_DETECTORSIZE_2 0x20 // Default
  670 +#define RF_PREAMBLEDETECT_DETECTORSIZE_3 0x40
  671 +#define RF_PREAMBLEDETECT_DETECTORSIZE_4 0x60
  672 +
  673 +#define RF_PREAMBLEDETECT_DETECTORTOL_MASK 0xE0
  674 +#define RF_PREAMBLEDETECT_DETECTORTOL_0 0x00
  675 +#define RF_PREAMBLEDETECT_DETECTORTOL_1 0x01
  676 +#define RF_PREAMBLEDETECT_DETECTORTOL_2 0x02
  677 +#define RF_PREAMBLEDETECT_DETECTORTOL_3 0x03
  678 +#define RF_PREAMBLEDETECT_DETECTORTOL_4 0x04
  679 +#define RF_PREAMBLEDETECT_DETECTORTOL_5 0x05
  680 +#define RF_PREAMBLEDETECT_DETECTORTOL_6 0x06
  681 +#define RF_PREAMBLEDETECT_DETECTORTOL_7 0x07
  682 +#define RF_PREAMBLEDETECT_DETECTORTOL_8 0x08
  683 +#define RF_PREAMBLEDETECT_DETECTORTOL_9 0x09
  684 +#define RF_PREAMBLEDETECT_DETECTORTOL_10 0x0A // Default
  685 +#define RF_PREAMBLEDETECT_DETECTORTOL_11 0x0B
  686 +#define RF_PREAMBLEDETECT_DETECTORTOL_12 0x0C
  687 +#define RF_PREAMBLEDETECT_DETECTORTOL_13 0x0D
  688 +#define RF_PREAMBLEDETECT_DETECTORTOL_14 0x0E
  689 +#define RF_PREAMBLEDETECT_DETECTORTOL_15 0x0F
  690 +#define RF_PREAMBLEDETECT_DETECTORTOL_16 0x10
  691 +#define RF_PREAMBLEDETECT_DETECTORTOL_17 0x11
  692 +#define RF_PREAMBLEDETECT_DETECTORTOL_18 0x12
  693 +#define RF_PREAMBLEDETECT_DETECTORTOL_19 0x13
  694 +#define RF_PREAMBLEDETECT_DETECTORTOL_20 0x14
  695 +#define RF_PREAMBLEDETECT_DETECTORTOL_21 0x15
  696 +#define RF_PREAMBLEDETECT_DETECTORTOL_22 0x16
  697 +#define RF_PREAMBLEDETECT_DETECTORTOL_23 0x17
  698 +#define RF_PREAMBLEDETECT_DETECTORTOL_24 0x18
  699 +#define RF_PREAMBLEDETECT_DETECTORTOL_25 0x19
  700 +#define RF_PREAMBLEDETECT_DETECTORTOL_26 0x1A
  701 +#define RF_PREAMBLEDETECT_DETECTORTOL_27 0x1B
  702 +#define RF_PREAMBLEDETECT_DETECTORTOL_28 0x1C
  703 +#define RF_PREAMBLEDETECT_DETECTORTOL_29 0x1D
  704 +#define RF_PREAMBLEDETECT_DETECTORTOL_30 0x1E
  705 +#define RF_PREAMBLEDETECT_DETECTORTOL_31 0x1F
  706 +
  707 +/*!
  708 + * RegRxTimeout1
  709 + */
  710 +#define RF_RXTIMEOUT1_TIMEOUTRXRSSI 0x00 // Default
  711 +
  712 +/*!
  713 + * RegRxTimeout2
  714 + */
  715 +#define RF_RXTIMEOUT2_TIMEOUTRXPREAMBLE 0x00 // Default
  716 +
  717 +/*!
  718 + * RegRxTimeout3
  719 + */
  720 +#define RF_RXTIMEOUT3_TIMEOUTSIGNALSYNC 0x00 // Default
  721 +
  722 +/*!
  723 + * RegRxDelay
  724 + */
  725 +#define RF_RXDELAY_INTERPACKETRXDELAY 0x00 // Default
  726 +
  727 +/*!
  728 + * RegOsc
  729 + */
  730 +#define RF_OSC_RCCALSTART 0x08
  731 +
  732 +#define RF_OSC_CLKOUT_MASK 0xF8
  733 +#define RF_OSC_CLKOUT_32_MHZ 0x00
  734 +#define RF_OSC_CLKOUT_16_MHZ 0x01
  735 +#define RF_OSC_CLKOUT_8_MHZ 0x02
  736 +#define RF_OSC_CLKOUT_4_MHZ 0x03
  737 +#define RF_OSC_CLKOUT_2_MHZ 0x04
  738 +#define RF_OSC_CLKOUT_1_MHZ 0x05 // Default
  739 +#define RF_OSC_CLKOUT_RC 0x06
  740 +#define RF_OSC_CLKOUT_OFF 0x07
  741 +
  742 +/*!
  743 + * RegPreambleMsb/RegPreambleLsb
  744 + */
  745 +#define RF_PREAMBLEMSB_SIZE 0x00 // Default
  746 +#define RF_PREAMBLELSB_SIZE 0x03 // Default
  747 +
  748 +/*!
  749 + * RegSyncConfig
  750 + */
  751 +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_MASK 0x3F
  752 +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_ON 0x80 // Default
  753 +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_OFF 0x40
  754 +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_OFF 0x00
  755 +
  756 +
  757 +#define RF_SYNCCONFIG_PREAMBLEPOLARITY_MASK 0xDF
  758 +#define RF_SYNCCONFIG_PREAMBLEPOLARITY_55 0x20
  759 +#define RF_SYNCCONFIG_PREAMBLEPOLARITY_AA 0x00 // Default
  760 +
  761 +#define RF_SYNCCONFIG_SYNC_MASK 0xEF
  762 +#define RF_SYNCCONFIG_SYNC_ON 0x10 // Default
  763 +#define RF_SYNCCONFIG_SYNC_OFF 0x00
  764 +
  765 +
  766 +#define RF_SYNCCONFIG_SYNCSIZE_MASK 0xF8
  767 +#define RF_SYNCCONFIG_SYNCSIZE_1 0x00
  768 +#define RF_SYNCCONFIG_SYNCSIZE_2 0x01
  769 +#define RF_SYNCCONFIG_SYNCSIZE_3 0x02
  770 +#define RF_SYNCCONFIG_SYNCSIZE_4 0x03 // Default
  771 +#define RF_SYNCCONFIG_SYNCSIZE_5 0x04
  772 +#define RF_SYNCCONFIG_SYNCSIZE_6 0x05
  773 +#define RF_SYNCCONFIG_SYNCSIZE_7 0x06
  774 +#define RF_SYNCCONFIG_SYNCSIZE_8 0x07
  775 +
  776 +/*!
  777 + * RegSyncValue1-8
  778 + */
  779 +#define RF_SYNCVALUE1_SYNCVALUE 0x01 // Default
  780 +#define RF_SYNCVALUE2_SYNCVALUE 0x01 // Default
  781 +#define RF_SYNCVALUE3_SYNCVALUE 0x01 // Default
  782 +#define RF_SYNCVALUE4_SYNCVALUE 0x01 // Default
  783 +#define RF_SYNCVALUE5_SYNCVALUE 0x01 // Default
  784 +#define RF_SYNCVALUE6_SYNCVALUE 0x01 // Default
  785 +#define RF_SYNCVALUE7_SYNCVALUE 0x01 // Default
  786 +#define RF_SYNCVALUE8_SYNCVALUE 0x01 // Default
  787 +
  788 +/*!
  789 + * RegPacketConfig1
  790 + */
  791 +#define RF_PACKETCONFIG1_PACKETFORMAT_MASK 0x7F
  792 +#define RF_PACKETCONFIG1_PACKETFORMAT_FIXED 0x00
  793 +#define RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE 0x80 // Default
  794 +
  795 +#define RF_PACKETCONFIG1_DCFREE_MASK 0x9F
  796 +#define RF_PACKETCONFIG1_DCFREE_OFF 0x00 // Default
  797 +#define RF_PACKETCONFIG1_DCFREE_MANCHESTER 0x20
  798 +#define RF_PACKETCONFIG1_DCFREE_WHITENING 0x40
  799 +
  800 +#define RF_PACKETCONFIG1_CRC_MASK 0xEF
  801 +#define RF_PACKETCONFIG1_CRC_ON 0x10 // Default
  802 +#define RF_PACKETCONFIG1_CRC_OFF 0x00
  803 +
  804 +#define RF_PACKETCONFIG1_CRCAUTOCLEAR_MASK 0xF7
  805 +#define RF_PACKETCONFIG1_CRCAUTOCLEAR_ON 0x00 // Default
  806 +#define RF_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08
  807 +
  808 +#define RF_PACKETCONFIG1_ADDRSFILTERING_MASK 0xF9
  809 +#define RF_PACKETCONFIG1_ADDRSFILTERING_OFF 0x00 // Default
  810 +#define RF_PACKETCONFIG1_ADDRSFILTERING_NODE 0x02
  811 +#define RF_PACKETCONFIG1_ADDRSFILTERING_NODEBROADCAST 0x04
  812 +
  813 +#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_MASK 0xFE
  814 +#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_CCITT 0x00 // Default
  815 +#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_IBM 0x01
  816 +
  817 +/*!
  818 + * RegPacketConfig2
  819 + */
  820 +
  821 +#define RF_PACKETCONFIG2_WMBUS_CRC_ENABLE_MASK 0x7F
  822 +#define RF_PACKETCONFIG2_WMBUS_CRC_ENABLE 0x80
  823 +#define RF_PACKETCONFIG2_WMBUS_CRC_DISABLE 0x00 // Default
  824 +
  825 +#define RF_PACKETCONFIG2_DATAMODE_MASK 0xBF
  826 +#define RF_PACKETCONFIG2_DATAMODE_CONTINUOUS 0x00
  827 +#define RF_PACKETCONFIG2_DATAMODE_PACKET 0x40 // Default
  828 +
  829 +#define RF_PACKETCONFIG2_IOHOME_MASK 0xDF
  830 +#define RF_PACKETCONFIG2_IOHOME_ON 0x20
  831 +#define RF_PACKETCONFIG2_IOHOME_OFF 0x00 // Default
  832 +
  833 +#define RF_PACKETCONFIG2_BEACON_MASK 0xF7
  834 +#define RF_PACKETCONFIG2_BEACON_ON 0x08
  835 +#define RF_PACKETCONFIG2_BEACON_OFF 0x00 // Default
  836 +
  837 +#define RF_PACKETCONFIG2_PAYLOADLENGTH_MSB_MASK 0xF8
  838 +
  839 +/*!
  840 + * RegPayloadLength
  841 + */
  842 +#define RF_PAYLOADLENGTH_LENGTH 0x40 // Default
  843 +
  844 +/*!
  845 + * RegNodeAdrs
  846 + */
  847 +#define RF_NODEADDRESS_ADDRESS 0x00
  848 +
  849 +/*!
  850 + * RegBroadcastAdrs
  851 + */
  852 +#define RF_BROADCASTADDRESS_ADDRESS 0x00
  853 +
  854 +/*!
  855 + * RegFifoThresh
  856 + */
  857 +#define RF_FIFOTHRESH_TXSTARTCONDITION_MASK 0x7F
  858 +#define RF_FIFOTHRESH_TXSTARTCONDITION_FIFOTHRESH 0x00 // Default
  859 +#define RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY 0x80
  860 +
  861 +#define RF_FIFOTHRESH_FIFOTHRESHOLD_MASK 0xC0
  862 +#define RF_FIFOTHRESH_FIFOTHRESHOLD_THRESHOLD 0x0F // Default
  863 +
  864 +/*!
  865 + * RegSeqConfig1
  866 + */
  867 +#define RF_SEQCONFIG1_SEQUENCER_START 0x80
  868 +
  869 +#define RF_SEQCONFIG1_SEQUENCER_STOP 0x40
  870 +
  871 +#define RF_SEQCONFIG1_IDLEMODE_MASK 0xDF
  872 +#define RF_SEQCONFIG1_IDLEMODE_SLEEP 0x20
  873 +#define RF_SEQCONFIG1_IDLEMODE_STANDBY 0x00 // Default
  874 +
  875 +#define RF_SEQCONFIG1_FROMSTART_MASK 0xE7
  876 +#define RF_SEQCONFIG1_FROMSTART_TOLPS 0x00 // Default
  877 +#define RF_SEQCONFIG1_FROMSTART_TORX 0x08
  878 +#define RF_SEQCONFIG1_FROMSTART_TOTX 0x10
  879 +#define RF_SEQCONFIG1_FROMSTART_TOTX_ONFIFOLEVEL 0x18
  880 +
  881 +#define RF_SEQCONFIG1_LPS_MASK 0xFB
  882 +#define RF_SEQCONFIG1_LPS_SEQUENCER_OFF 0x00 // Default
  883 +#define RF_SEQCONFIG1_LPS_IDLE 0x04
  884 +
  885 +#define RF_SEQCONFIG1_FROMIDLE_MASK 0xFD
  886 +#define RF_SEQCONFIG1_FROMIDLE_TOTX 0x00 // Default
  887 +#define RF_SEQCONFIG1_FROMIDLE_TORX 0x02
  888 +
  889 +#define RF_SEQCONFIG1_FROMTX_MASK 0xFE
  890 +#define RF_SEQCONFIG1_FROMTX_TOLPS 0x00 // Default
  891 +#define RF_SEQCONFIG1_FROMTX_TORX 0x01
  892 +
  893 +/*!
  894 + * RegSeqConfig2
  895 + */
  896 +#define RF_SEQCONFIG2_FROMRX_MASK 0x1F
  897 +#define RF_SEQCONFIG2_FROMRX_TOUNUSED_000 0x00 // Default
  898 +#define RF_SEQCONFIG2_FROMRX_TORXPKT_ONPLDRDY 0x20
  899 +#define RF_SEQCONFIG2_FROMRX_TOLPS_ONPLDRDY 0x40
  900 +#define RF_SEQCONFIG2_FROMRX_TORXPKT_ONCRCOK 0x60
  901 +#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONRSSI 0x80
  902 +#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONSYNC 0xA0
  903 +#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONPREAMBLE 0xC0
  904 +#define RF_SEQCONFIG2_FROMRX_TOUNUSED_111 0xE0
  905 +
  906 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_MASK 0xE7
  907 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TORXRESTART 0x00 // Default
  908 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOTX 0x08
  909 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOLPS 0x10
  910 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOSEQUENCEROFF 0x18
  911 +
  912 +#define RF_SEQCONFIG2_FROMRXPKT_MASK 0xF8
  913 +#define RF_SEQCONFIG2_FROMRXPKT_TOSEQUENCEROFF 0x00 // Default
  914 +#define RF_SEQCONFIG2_FROMRXPKT_TOTX_ONFIFOEMPTY 0x01
  915 +#define RF_SEQCONFIG2_FROMRXPKT_TOLPS 0x02
  916 +#define RF_SEQCONFIG2_FROMRXPKT_TOSYNTHESIZERRX 0x03
  917 +#define RF_SEQCONFIG2_FROMRXPKT_TORX 0x04
  918 +
  919 +/*!
  920 + * RegTimerResol
  921 + */
  922 +#define RF_TIMERRESOL_TIMER1RESOL_MASK 0xF3
  923 +#define RF_TIMERRESOL_TIMER1RESOL_OFF 0x00 // Default
  924 +#define RF_TIMERRESOL_TIMER1RESOL_000064_US 0x04
  925 +#define RF_TIMERRESOL_TIMER1RESOL_004100_US 0x08
  926 +#define RF_TIMERRESOL_TIMER1RESOL_262000_US 0x0C
  927 +
  928 +#define RF_TIMERRESOL_TIMER2RESOL_MASK 0xFC
  929 +#define RF_TIMERRESOL_TIMER2RESOL_OFF 0x00 // Default
  930 +#define RF_TIMERRESOL_TIMER2RESOL_000064_US 0x01
  931 +#define RF_TIMERRESOL_TIMER2RESOL_004100_US 0x02
  932 +#define RF_TIMERRESOL_TIMER2RESOL_262000_US 0x03
  933 +
  934 +/*!
  935 + * RegTimer1Coef
  936 + */
  937 +#define RF_TIMER1COEF_TIMER1COEFFICIENT 0xF5 // Default
  938 +
  939 +/*!
  940 + * RegTimer2Coef
  941 + */
  942 +#define RF_TIMER2COEF_TIMER2COEFFICIENT 0x20 // Default
  943 +
  944 +/*!
  945 + * RegImageCal
  946 + */
  947 +#define RF_IMAGECAL_AUTOIMAGECAL_MASK 0x7F
  948 +#define RF_IMAGECAL_AUTOIMAGECAL_ON 0x80
  949 +#define RF_IMAGECAL_AUTOIMAGECAL_OFF 0x00 // Default
  950 +
  951 +#define RF_IMAGECAL_IMAGECAL_MASK 0xBF
  952 +#define RF_IMAGECAL_IMAGECAL_START 0x40
  953 +
  954 +#define RF_IMAGECAL_IMAGECAL_RUNNING 0x20
  955 +#define RF_IMAGECAL_IMAGECAL_DONE 0x00 // Default
  956 +
  957 +#define RF_IMAGECAL_TEMPCHANGE_HIGHER 0x08
  958 +#define RF_IMAGECAL_TEMPCHANGE_LOWER 0x00
  959 +
  960 +#define RF_IMAGECAL_TEMPTHRESHOLD_MASK 0xF9
  961 +#define RF_IMAGECAL_TEMPTHRESHOLD_05 0x00
  962 +#define RF_IMAGECAL_TEMPTHRESHOLD_10 0x02 // Default
  963 +#define RF_IMAGECAL_TEMPTHRESHOLD_15 0x04
  964 +#define RF_IMAGECAL_TEMPTHRESHOLD_20 0x06
  965 +
  966 +#define RF_IMAGECAL_TEMPMONITOR_MASK 0xFE
  967 +#define RF_IMAGECAL_TEMPMONITOR_ON 0x00 // Default
  968 +#define RF_IMAGECAL_TEMPMONITOR_OFF 0x01
  969 +
  970 +/*!
  971 + * RegTemp (Read Only)
  972 + */
  973 +
  974 +/*!
  975 + * RegLowBat
  976 + */
  977 +#define RF_LOWBAT_MASK 0xF7
  978 +#define RF_LOWBAT_ON 0x08
  979 +#define RF_LOWBAT_OFF 0x00 // Default
  980 +
  981 +#define RF_LOWBAT_TRIM_MASK 0xF8
  982 +#define RF_LOWBAT_TRIM_1695 0x00
  983 +#define RF_LOWBAT_TRIM_1764 0x01
  984 +#define RF_LOWBAT_TRIM_1835 0x02 // Default
  985 +#define RF_LOWBAT_TRIM_1905 0x03
  986 +#define RF_LOWBAT_TRIM_1976 0x04
  987 +#define RF_LOWBAT_TRIM_2045 0x05
  988 +#define RF_LOWBAT_TRIM_2116 0x06
  989 +#define RF_LOWBAT_TRIM_2185 0x07
  990 +
  991 +/*!
  992 + * RegIrqFlags1
  993 + */
  994 +#define RF_IRQFLAGS1_MODEREADY 0x80
  995 +
  996 +#define RF_IRQFLAGS1_RXREADY 0x40
  997 +
  998 +#define RF_IRQFLAGS1_TXREADY 0x20
  999 +
  1000 +#define RF_IRQFLAGS1_PLLLOCK 0x10
  1001 +
  1002 +#define RF_IRQFLAGS1_RSSI 0x08
  1003 +
  1004 +#define RF_IRQFLAGS1_TIMEOUT 0x04
  1005 +
  1006 +#define RF_IRQFLAGS1_PREAMBLEDETECT 0x02
  1007 +
  1008 +#define RF_IRQFLAGS1_SYNCADDRESSMATCH 0x01
  1009 +
  1010 +/*!
  1011 + * RegIrqFlags2
  1012 + */
  1013 +#define RF_IRQFLAGS2_FIFOFULL 0x80
  1014 +
  1015 +#define RF_IRQFLAGS2_FIFOEMPTY 0x40
  1016 +
  1017 +#define RF_IRQFLAGS2_FIFOLEVEL 0x20
  1018 +
  1019 +#define RF_IRQFLAGS2_FIFOOVERRUN 0x10
  1020 +
  1021 +#define RF_IRQFLAGS2_PACKETSENT 0x08
  1022 +
  1023 +#define RF_IRQFLAGS2_PAYLOADREADY 0x04
  1024 +
  1025 +#define RF_IRQFLAGS2_CRCOK 0x02
  1026 +
  1027 +#define RF_IRQFLAGS2_LOWBAT 0x01
  1028 +
  1029 +/*!
  1030 + * RegDioMapping1
  1031 + */
  1032 +#define RF_DIOMAPPING1_DIO0_MASK 0x3F
  1033 +#define RF_DIOMAPPING1_DIO0_00 0x00 // Default
  1034 +#define RF_DIOMAPPING1_DIO0_01 0x40
  1035 +#define RF_DIOMAPPING1_DIO0_10 0x80
  1036 +#define RF_DIOMAPPING1_DIO0_11 0xC0
  1037 +
  1038 +#define RF_DIOMAPPING1_DIO1_MASK 0xCF
  1039 +#define RF_DIOMAPPING1_DIO1_00 0x00 // Default
  1040 +#define RF_DIOMAPPING1_DIO1_01 0x10
  1041 +#define RF_DIOMAPPING1_DIO1_10 0x20
  1042 +#define RF_DIOMAPPING1_DIO1_11 0x30
  1043 +
  1044 +#define RF_DIOMAPPING1_DIO2_MASK 0xF3
  1045 +#define RF_DIOMAPPING1_DIO2_00 0x00 // Default
  1046 +#define RF_DIOMAPPING1_DIO2_01 0x04
  1047 +#define RF_DIOMAPPING1_DIO2_10 0x08
  1048 +#define RF_DIOMAPPING1_DIO2_11 0x0C
  1049 +
  1050 +#define RF_DIOMAPPING1_DIO3_MASK 0xFC
  1051 +#define RF_DIOMAPPING1_DIO3_00 0x00 // Default
  1052 +#define RF_DIOMAPPING1_DIO3_01 0x01
  1053 +#define RF_DIOMAPPING1_DIO3_10 0x02
  1054 +#define RF_DIOMAPPING1_DIO3_11 0x03
  1055 +
  1056 +/*!
  1057 + * RegDioMapping2
  1058 + */
  1059 +#define RF_DIOMAPPING2_DIO4_MASK 0x3F
  1060 +#define RF_DIOMAPPING2_DIO4_00 0x00 // Default
  1061 +#define RF_DIOMAPPING2_DIO4_01 0x40
  1062 +#define RF_DIOMAPPING2_DIO4_10 0x80
  1063 +#define RF_DIOMAPPING2_DIO4_11 0xC0
  1064 +
  1065 +#define RF_DIOMAPPING2_DIO5_MASK 0xCF
  1066 +#define RF_DIOMAPPING2_DIO5_00 0x00 // Default
  1067 +#define RF_DIOMAPPING2_DIO5_01 0x10
  1068 +#define RF_DIOMAPPING2_DIO5_10 0x20
  1069 +#define RF_DIOMAPPING2_DIO5_11 0x30
  1070 +
  1071 +#define RF_DIOMAPPING2_MAP_MASK 0xFE
  1072 +#define RF_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01
  1073 +#define RF_DIOMAPPING2_MAP_RSSI 0x00 // Default
  1074 +
  1075 +/*!
  1076 + * RegVersion (Read Only)
  1077 + */
  1078 +
  1079 +/*!
  1080 + * RegPllHop
  1081 + */
  1082 +#define RF_PLLHOP_FASTHOP_MASK 0x7F
  1083 +#define RF_PLLHOP_FASTHOP_ON 0x80
  1084 +#define RF_PLLHOP_FASTHOP_OFF 0x00 // Default
  1085 +
  1086 +/*!
  1087 + * RegTcxo
  1088 + */
  1089 +#define RF_TCXO_TCXOINPUT_MASK 0xEF
  1090 +#define RF_TCXO_TCXOINPUT_ON 0x10
  1091 +#define RF_TCXO_TCXOINPUT_OFF 0x00 // Default
  1092 +
  1093 +/*!
  1094 + * RegPaDac
  1095 + */
  1096 +#define RF_PADAC_20DBM_MASK 0xF8
  1097 +#define RF_PADAC_20DBM_ON 0x07
  1098 +#define RF_PADAC_20DBM_OFF 0x04 // Default
  1099 +
  1100 +/*!
  1101 + * RegFormerTemp
  1102 + */
  1103 +
  1104 +/*!
  1105 + * RegBitrateFrac
  1106 + */
  1107 +#define RF_BITRATEFRAC_MASK 0xF0
  1108 +
  1109 +/*!
  1110 + * RegAgcRef
  1111 + */
  1112 +
  1113 +/*!
  1114 + * RegAgcThresh1
  1115 + */
  1116 +
  1117 +/*!
  1118 + * RegAgcThresh2
  1119 + */
  1120 +
  1121 +/*!
  1122 + * RegAgcThresh3
  1123 + */
  1124 +
  1125 +/*!
  1126 + * RegPll
  1127 + */
  1128 +#define RF_PLL_BANDWIDTH_MASK 0x3F
  1129 +#define RF_PLL_BANDWIDTH_75 0x00
  1130 +#define RF_PLL_BANDWIDTH_150 0x40
  1131 +#define RF_PLL_BANDWIDTH_225 0x80
  1132 +#define RF_PLL_BANDWIDTH_300 0xC0 // Default
  1133 +
  1134 +#endif // __SX1276_REGS_FSK_H__
... ...
emetteur/SX1276Lib/registers/sx1276Regs-LoRa.h 0 → 100644
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... ... @@ -0,0 +1,565 @@
  1 +/*
  2 + / _____) _ | |
  3 +( (____ _____ ____ _| |_ _____ ____| |__
  4 + \____ \| ___ | (_ _) ___ |/ ___) _ \
  5 + _____) ) ____| | | || |_| ____( (___| | | |
  6 +(______/|_____)_|_|_| \__)_____)\____)_| |_|
  7 + (C) 2014 Semtech
  8 +
  9 +Description: SX1276 LoRa modem registers and bits definitions
  10 +
  11 +License: Revised BSD License, see LICENSE.TXT file include in the project
  12 +
  13 +Maintainer: Miguel Luis and Gregory Cristian
  14 +*/
  15 +#ifndef __SX1276_REGS_LORA_H__
  16 +#define __SX1276_REGS_LORA_H__
  17 +
  18 +/*!
  19 + * ============================================================================
  20 + * SX1276 Internal registers Address
  21 + * ============================================================================
  22 + */
  23 +#define REG_LR_FIFO 0x00
  24 +// Common settings
  25 +#define REG_LR_OPMODE 0x01
  26 +#define REG_LR_FRFMSB 0x06
  27 +#define REG_LR_FRFMID 0x07
  28 +#define REG_LR_FRFLSB 0x08
  29 +// Tx settings
  30 +#define REG_LR_PACONFIG 0x09
  31 +#define REG_LR_PARAMP 0x0A
  32 +#define REG_LR_OCP 0x0B
  33 +// Rx settings
  34 +#define REG_LR_LNA 0x0C
  35 +// LoRa registers
  36 +#define REG_LR_FIFOADDRPTR 0x0D
  37 +#define REG_LR_FIFOTXBASEADDR 0x0E
  38 +#define REG_LR_FIFORXBASEADDR 0x0F
  39 +#define REG_LR_FIFORXCURRENTADDR 0x10
  40 +#define REG_LR_IRQFLAGSMASK 0x11
  41 +#define REG_LR_IRQFLAGS 0x12
  42 +#define REG_LR_RXNBBYTES 0x13
  43 +#define REG_LR_RXHEADERCNTVALUEMSB 0x14
  44 +#define REG_LR_RXHEADERCNTVALUELSB 0x15
  45 +#define REG_LR_RXPACKETCNTVALUEMSB 0x16
  46 +#define REG_LR_RXPACKETCNTVALUELSB 0x17
  47 +#define REG_LR_MODEMSTAT 0x18
  48 +#define REG_LR_PKTSNRVALUE 0x19
  49 +#define REG_LR_PKTRSSIVALUE 0x1A
  50 +#define REG_LR_RSSIVALUE 0x1B
  51 +#define REG_LR_HOPCHANNEL 0x1C
  52 +#define REG_LR_MODEMCONFIG1 0x1D
  53 +#define REG_LR_MODEMCONFIG2 0x1E
  54 +#define REG_LR_SYMBTIMEOUTLSB 0x1F
  55 +#define REG_LR_PREAMBLEMSB 0x20
  56 +#define REG_LR_PREAMBLELSB 0x21
  57 +#define REG_LR_PAYLOADLENGTH 0x22
  58 +#define REG_LR_PAYLOADMAXLENGTH 0x23
  59 +#define REG_LR_HOPPERIOD 0x24
  60 +#define REG_LR_FIFORXBYTEADDR 0x25
  61 +#define REG_LR_MODEMCONFIG3 0x26
  62 +#define REG_LR_FEIMSB 0x28
  63 +#define REG_LR_FEIMID 0x29
  64 +#define REG_LR_FEILSB 0x2A
  65 +#define REG_LR_RSSIWIDEBAND 0x2C
  66 +#define REG_LR_TEST2F 0x2F
  67 +#define REG_LR_TEST30 0x30
  68 +#define REG_LR_DETECTOPTIMIZE 0x31
  69 +#define REG_LR_INVERTIQ 0x33
  70 +#define REG_LR_TEST36 0x36
  71 +#define REG_LR_DETECTIONTHRESHOLD 0x37
  72 +#define REG_LR_SYNCWORD 0x39
  73 +#define REG_LR_TEST3A 0x3A
  74 +#define REG_LR_INVERTIQ2 0x3B
  75 +
  76 +// end of documented register in datasheet
  77 +// I/O settings
  78 +#define REG_LR_DIOMAPPING1 0x40
  79 +#define REG_LR_DIOMAPPING2 0x41
  80 +// Version
  81 +#define REG_LR_VERSION 0x42
  82 +// Additional settings
  83 +#define REG_LR_PLLHOP 0x44
  84 +#define REG_LR_TCXO 0x4B
  85 +#define REG_LR_PADAC 0x4D
  86 +#define REG_LR_FORMERTEMP 0x5B
  87 +#define REG_LR_BITRATEFRAC 0x5D
  88 +#define REG_LR_AGCREF 0x61
  89 +#define REG_LR_AGCTHRESH1 0x62
  90 +#define REG_LR_AGCTHRESH2 0x63
  91 +#define REG_LR_AGCTHRESH3 0x64
  92 +#define REG_LR_PLL 0x70
  93 +
  94 +/*!
  95 + * ============================================================================
  96 + * SX1276 LoRa bits control definition
  97 + * ============================================================================
  98 + */
  99 +
  100 +/*!
  101 + * RegFifo
  102 + */
  103 +
  104 +/*!
  105 + * RegOpMode
  106 + */
  107 +#define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F
  108 +#define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default
  109 +#define RFLR_OPMODE_LONGRANGEMODE_ON 0x80
  110 +
  111 +#define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF
  112 +#define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40
  113 +#define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default
  114 +
  115 +#define RFLR_OPMODE_FREQMODE_ACCESS_MASK 0xF7
  116 +#define RFLR_OPMODE_FREQMODE_ACCESS_LF 0x08 // Default
  117 +#define RFLR_OPMODE_FREQMODE_ACCESS_HF 0x00
  118 +
  119 +#define RFLR_OPMODE_MASK 0xF8
  120 +#define RFLR_OPMODE_SLEEP 0x00
  121 +#define RFLR_OPMODE_STANDBY 0x01 // Default
  122 +#define RFLR_OPMODE_SYNTHESIZER_TX 0x02
  123 +#define RFLR_OPMODE_TRANSMITTER 0x03
  124 +#define RFLR_OPMODE_SYNTHESIZER_RX 0x04
  125 +#define RFLR_OPMODE_RECEIVER 0x05
  126 +// LoRa specific modes
  127 +#define RFLR_OPMODE_RECEIVER_SINGLE 0x06
  128 +#define RFLR_OPMODE_CAD 0x07
  129 +
  130 +/*!
  131 + * RegFrf (MHz)
  132 + */
  133 +#define RFLR_FRFMSB_434_MHZ 0x6C // Default
  134 +#define RFLR_FRFMID_434_MHZ 0x80 // Default
  135 +#define RFLR_FRFLSB_434_MHZ 0x00 // Default
  136 +
  137 +/*!
  138 + * RegPaConfig
  139 + */
  140 +#define RFLR_PACONFIG_PASELECT_MASK 0x7F
  141 +#define RFLR_PACONFIG_PASELECT_PABOOST 0x80
  142 +#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default
  143 +
  144 +#define RFLR_PACONFIG_MAX_POWER_MASK 0x8F
  145 +
  146 +#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0
  147 +
  148 +/*!
  149 + * RegPaRamp
  150 + */
  151 +#define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF
  152 +#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10
  153 +#define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default
  154 +
  155 +#define RFLR_PARAMP_MASK 0xF0
  156 +#define RFLR_PARAMP_3400_US 0x00
  157 +#define RFLR_PARAMP_2000_US 0x01
  158 +#define RFLR_PARAMP_1000_US 0x02
  159 +#define RFLR_PARAMP_0500_US 0x03
  160 +#define RFLR_PARAMP_0250_US 0x04
  161 +#define RFLR_PARAMP_0125_US 0x05
  162 +#define RFLR_PARAMP_0100_US 0x06
  163 +#define RFLR_PARAMP_0062_US 0x07
  164 +#define RFLR_PARAMP_0050_US 0x08
  165 +#define RFLR_PARAMP_0040_US 0x09 // Default
  166 +#define RFLR_PARAMP_0031_US 0x0A
  167 +#define RFLR_PARAMP_0025_US 0x0B
  168 +#define RFLR_PARAMP_0020_US 0x0C
  169 +#define RFLR_PARAMP_0015_US 0x0D
  170 +#define RFLR_PARAMP_0012_US 0x0E
  171 +#define RFLR_PARAMP_0010_US 0x0F
  172 +
  173 +/*!
  174 + * RegOcp
  175 + */
  176 +#define RFLR_OCP_MASK 0xDF
  177 +#define RFLR_OCP_ON 0x20 // Default
  178 +#define RFLR_OCP_OFF 0x00
  179 +
  180 +#define RFLR_OCP_TRIM_MASK 0xE0
  181 +#define RFLR_OCP_TRIM_045_MA 0x00
  182 +#define RFLR_OCP_TRIM_050_MA 0x01
  183 +#define RFLR_OCP_TRIM_055_MA 0x02
  184 +#define RFLR_OCP_TRIM_060_MA 0x03
  185 +#define RFLR_OCP_TRIM_065_MA 0x04
  186 +#define RFLR_OCP_TRIM_070_MA 0x05
  187 +#define RFLR_OCP_TRIM_075_MA 0x06
  188 +#define RFLR_OCP_TRIM_080_MA 0x07
  189 +#define RFLR_OCP_TRIM_085_MA 0x08
  190 +#define RFLR_OCP_TRIM_090_MA 0x09
  191 +#define RFLR_OCP_TRIM_095_MA 0x0A
  192 +#define RFLR_OCP_TRIM_100_MA 0x0B // Default
  193 +#define RFLR_OCP_TRIM_105_MA 0x0C
  194 +#define RFLR_OCP_TRIM_110_MA 0x0D
  195 +#define RFLR_OCP_TRIM_115_MA 0x0E
  196 +#define RFLR_OCP_TRIM_120_MA 0x0F
  197 +#define RFLR_OCP_TRIM_130_MA 0x10
  198 +#define RFLR_OCP_TRIM_140_MA 0x11
  199 +#define RFLR_OCP_TRIM_150_MA 0x12
  200 +#define RFLR_OCP_TRIM_160_MA 0x13
  201 +#define RFLR_OCP_TRIM_170_MA 0x14
  202 +#define RFLR_OCP_TRIM_180_MA 0x15
  203 +#define RFLR_OCP_TRIM_190_MA 0x16
  204 +#define RFLR_OCP_TRIM_200_MA 0x17
  205 +#define RFLR_OCP_TRIM_210_MA 0x18
  206 +#define RFLR_OCP_TRIM_220_MA 0x19
  207 +#define RFLR_OCP_TRIM_230_MA 0x1A
  208 +#define RFLR_OCP_TRIM_240_MA 0x1B
  209 +
  210 +/*!
  211 + * RegLna
  212 + */
  213 +#define RFLR_LNA_GAIN_MASK 0x1F
  214 +#define RFLR_LNA_GAIN_G1 0x20 // Default
  215 +#define RFLR_LNA_GAIN_G2 0x40
  216 +#define RFLR_LNA_GAIN_G3 0x60
  217 +#define RFLR_LNA_GAIN_G4 0x80
  218 +#define RFLR_LNA_GAIN_G5 0xA0
  219 +#define RFLR_LNA_GAIN_G6 0xC0
  220 +
  221 +#define RFLR_LNA_BOOST_LF_MASK 0xE7
  222 +#define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default
  223 +
  224 +#define RFLR_LNA_BOOST_HF_MASK 0xFC
  225 +#define RFLR_LNA_BOOST_HF_OFF 0x00 // Default
  226 +#define RFLR_LNA_BOOST_HF_ON 0x03
  227 +
  228 +/*!
  229 + * RegFifoAddrPtr
  230 + */
  231 +#define RFLR_FIFOADDRPTR 0x00 // Default
  232 +
  233 +/*!
  234 + * RegFifoTxBaseAddr
  235 + */
  236 +#define RFLR_FIFOTXBASEADDR 0x80 // Default
  237 +
  238 +/*!
  239 + * RegFifoTxBaseAddr
  240 + */
  241 +#define RFLR_FIFORXBASEADDR 0x00 // Default
  242 +
  243 +/*!
  244 + * RegFifoRxCurrentAddr (Read Only)
  245 + */
  246 +
  247 +/*!
  248 + * RegIrqFlagsMask
  249 + */
  250 +#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80
  251 +#define RFLR_IRQFLAGS_RXDONE_MASK 0x40
  252 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20
  253 +#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10
  254 +#define RFLR_IRQFLAGS_TXDONE_MASK 0x08
  255 +#define RFLR_IRQFLAGS_CADDONE_MASK 0x04
  256 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02
  257 +#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01
  258 +
  259 +/*!
  260 + * RegIrqFlags
  261 + */
  262 +#define RFLR_IRQFLAGS_RXTIMEOUT 0x80
  263 +#define RFLR_IRQFLAGS_RXDONE 0x40
  264 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20
  265 +#define RFLR_IRQFLAGS_VALIDHEADER 0x10
  266 +#define RFLR_IRQFLAGS_TXDONE 0x08
  267 +#define RFLR_IRQFLAGS_CADDONE 0x04
  268 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02
  269 +#define RFLR_IRQFLAGS_CADDETECTED 0x01
  270 +
  271 +/*!
  272 + * RegFifoRxNbBytes (Read Only)
  273 + */
  274 +
  275 +/*!
  276 + * RegRxHeaderCntValueMsb (Read Only)
  277 + */
  278 +
  279 +/*!
  280 + * RegRxHeaderCntValueLsb (Read Only)
  281 + */
  282 +
  283 +/*!
  284 + * RegRxPacketCntValueMsb (Read Only)
  285 + */
  286 +
  287 +/*!
  288 + * RegRxPacketCntValueLsb (Read Only)
  289 + */
  290 +
  291 +/*!
  292 + * RegModemStat (Read Only)
  293 + */
  294 +#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F
  295 +#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0
  296 +
  297 +/*!
  298 + * RegPktSnrValue (Read Only)
  299 + */
  300 +
  301 +/*!
  302 + * RegPktRssiValue (Read Only)
  303 + */
  304 +
  305 +/*!
  306 + * RegRssiValue (Read Only)
  307 + */
  308 +
  309 +/*!
  310 + * RegHopChannel (Read Only)
  311 + */
  312 +#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F
  313 +#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80
  314 +#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default
  315 +
  316 +#define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK 0xBF
  317 +#define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON 0x40
  318 +#define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF 0x00 // Default
  319 +
  320 +#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F
  321 +
  322 +/*!
  323 + * RegModemConfig1
  324 + */
  325 +#define RFLR_MODEMCONFIG1_BW_MASK 0x0F
  326 +#define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00
  327 +#define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10
  328 +#define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20
  329 +#define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30
  330 +#define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40
  331 +#define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50
  332 +#define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60
  333 +#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default
  334 +#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80
  335 +#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90
  336 +
  337 +#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1
  338 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02
  339 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default
  340 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06
  341 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08
  342 +
  343 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE
  344 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x01
  345 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default
  346 +
  347 +/*!
  348 + * RegModemConfig2
  349 + */
  350 +#define RFLR_MODEMCONFIG2_SF_MASK 0x0F
  351 +#define RFLR_MODEMCONFIG2_SF_6 0x60
  352 +#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default
  353 +#define RFLR_MODEMCONFIG2_SF_8 0x80
  354 +#define RFLR_MODEMCONFIG2_SF_9 0x90
  355 +#define RFLR_MODEMCONFIG2_SF_10 0xA0
  356 +#define RFLR_MODEMCONFIG2_SF_11 0xB0
  357 +#define RFLR_MODEMCONFIG2_SF_12 0xC0
  358 +
  359 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7
  360 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08
  361 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00
  362 +
  363 +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB
  364 +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04
  365 +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default
  366 +
  367 +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC
  368 +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default
  369 +
  370 +/*!
  371 + * RegSymbTimeoutLsb
  372 + */
  373 +#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default
  374 +
  375 +/*!
  376 + * RegPreambleLengthMsb
  377 + */
  378 +#define RFLR_PREAMBLELENGTHMSB 0x00 // Default
  379 +
  380 +/*!
  381 + * RegPreambleLengthLsb
  382 + */
  383 +#define RFLR_PREAMBLELENGTHLSB 0x08 // Default
  384 +
  385 +/*!
  386 + * RegPayloadLength
  387 + */
  388 +#define RFLR_PAYLOADLENGTH 0x0E // Default
  389 +
  390 +/*!
  391 + * RegPayloadMaxLength
  392 + */
  393 +#define RFLR_PAYLOADMAXLENGTH 0xFF // Default
  394 +
  395 +/*!
  396 + * RegHopPeriod
  397 + */
  398 +#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default
  399 +
  400 +/*!
  401 + * RegFifoRxByteAddr (Read Only)
  402 + */
  403 +
  404 +/*!
  405 + * RegModemConfig3
  406 + */
  407 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7
  408 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08
  409 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default
  410 +
  411 +#define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB
  412 +#define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default
  413 +#define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00
  414 +
  415 +/*!
  416 + * RegFeiMsb (Read Only)
  417 + */
  418 +
  419 +/*!
  420 + * RegFeiMid (Read Only)
  421 + */
  422 +
  423 +/*!
  424 + * RegFeiLsb (Read Only)
  425 + */
  426 +
  427 +/*!
  428 + * RegRssiWideband (Read Only)
  429 + */
  430 +
  431 +/*!
  432 + * RegDetectOptimize
  433 + */
  434 +#define RFLR_DETECTIONOPTIMIZE_MASK 0xF8
  435 +#define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 0x03 // Default
  436 +#define RFLR_DETECTIONOPTIMIZE_SF6 0x05
  437 +
  438 +/*!
  439 + * RegInvertIQ
  440 + */
  441 +#define RFLR_INVERTIQ_RX_MASK 0xBF
  442 +#define RFLR_INVERTIQ_RX_OFF 0x00
  443 +#define RFLR_INVERTIQ_RX_ON 0x40
  444 +#define RFLR_INVERTIQ_TX_MASK 0xFE
  445 +#define RFLR_INVERTIQ_TX_OFF 0x01
  446 +#define RFLR_INVERTIQ_TX_ON 0x00
  447 +
  448 +/*!
  449 + * RegDetectionThreshold
  450 + */
  451 +#define RFLR_DETECTIONTHRESH_SF7_TO_SF12 0x0A // Default
  452 +#define RFLR_DETECTIONTHRESH_SF6 0x0C
  453 +
  454 +/*!
  455 + * RegInvertIQ2
  456 + */
  457 +#define RFLR_INVERTIQ2_ON 0x19
  458 +#define RFLR_INVERTIQ2_OFF 0x1D
  459 +
  460 +/*!
  461 + * RegDioMapping1
  462 + */
  463 +#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F
  464 +#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default
  465 +#define RFLR_DIOMAPPING1_DIO0_01 0x40
  466 +#define RFLR_DIOMAPPING1_DIO0_10 0x80
  467 +#define RFLR_DIOMAPPING1_DIO0_11 0xC0
  468 +
  469 +#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF
  470 +#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default
  471 +#define RFLR_DIOMAPPING1_DIO1_01 0x10
  472 +#define RFLR_DIOMAPPING1_DIO1_10 0x20
  473 +#define RFLR_DIOMAPPING1_DIO1_11 0x30
  474 +
  475 +#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3
  476 +#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default
  477 +#define RFLR_DIOMAPPING1_DIO2_01 0x04
  478 +#define RFLR_DIOMAPPING1_DIO2_10 0x08
  479 +#define RFLR_DIOMAPPING1_DIO2_11 0x0C
  480 +
  481 +#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC
  482 +#define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default
  483 +#define RFLR_DIOMAPPING1_DIO3_01 0x01
  484 +#define RFLR_DIOMAPPING1_DIO3_10 0x02
  485 +#define RFLR_DIOMAPPING1_DIO3_11 0x03
  486 +
  487 +/*!
  488 + * RegDioMapping2
  489 + */
  490 +#define RFLR_DIOMAPPING2_DIO4_MASK 0x3F
  491 +#define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default
  492 +#define RFLR_DIOMAPPING2_DIO4_01 0x40
  493 +#define RFLR_DIOMAPPING2_DIO4_10 0x80
  494 +#define RFLR_DIOMAPPING2_DIO4_11 0xC0
  495 +
  496 +#define RFLR_DIOMAPPING2_DIO5_MASK 0xCF
  497 +#define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default
  498 +#define RFLR_DIOMAPPING2_DIO5_01 0x10
  499 +#define RFLR_DIOMAPPING2_DIO5_10 0x20
  500 +#define RFLR_DIOMAPPING2_DIO5_11 0x30
  501 +
  502 +#define RFLR_DIOMAPPING2_MAP_MASK 0xFE
  503 +#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01
  504 +#define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default
  505 +
  506 +/*!
  507 + * RegVersion (Read Only)
  508 + */
  509 +
  510 +/*!
  511 + * RegPllHop
  512 + */
  513 +#define RFLR_PLLHOP_FASTHOP_MASK 0x7F
  514 +#define RFLR_PLLHOP_FASTHOP_ON 0x80
  515 +#define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default
  516 +
  517 +/*!
  518 + * RegTcxo
  519 + */
  520 +#define RFLR_TCXO_TCXOINPUT_MASK 0xEF
  521 +#define RFLR_TCXO_TCXOINPUT_ON 0x10
  522 +#define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default
  523 +
  524 +/*!
  525 + * RegPaDac
  526 + */
  527 +#define RFLR_PADAC_20DBM_MASK 0xF8
  528 +#define RFLR_PADAC_20DBM_ON 0x07
  529 +#define RFLR_PADAC_20DBM_OFF 0x04 // Default
  530 +
  531 +/*!
  532 + * RegFormerTemp
  533 + */
  534 +
  535 +/*!
  536 + * RegBitrateFrac
  537 + */
  538 +#define RF_BITRATEFRAC_MASK 0xF0
  539 +
  540 +/*!
  541 + * RegAgcRef
  542 + */
  543 +
  544 +/*!
  545 + * RegAgcThresh1
  546 + */
  547 +
  548 +/*!
  549 + * RegAgcThresh2
  550 + */
  551 +
  552 +/*!
  553 + * RegAgcThresh3
  554 + */
  555 +
  556 +/*!
  557 + * RegPll
  558 + */
  559 +#define RF_PLL_BANDWIDTH_MASK 0x3F
  560 +#define RF_PLL_BANDWIDTH_75 0x00
  561 +#define RF_PLL_BANDWIDTH_150 0x40
  562 +#define RF_PLL_BANDWIDTH_225 0x80
  563 +#define RF_PLL_BANDWIDTH_300 0xC0 // Default
  564 +
  565 +#endif // __SX1276_REGS_LORA_H__
... ...
emetteur/SX1276Lib/sx1276/sx1276-hal.cpp 0 → 100644
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... ... @@ -0,0 +1,349 @@
  1 +/*
  2 + / _____) _ | |
  3 +( (____ _____ ____ _| |_ _____ ____| |__
  4 + \____ \| ___ | (_ _) ___ |/ ___) _ \
  5 + _____) ) ____| | | || |_| ____( (___| | | |
  6 +(______/|_____)_|_|_| \__)_____)\____)_| |_|
  7 + (C) 2014 Semtech
  8 +
  9 +Description: -
  10 +
  11 +License: Revised BSD License, see LICENSE.TXT file include in the project
  12 +
  13 +Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
  14 +*/
  15 +#include "sx1276-hal.h"
  16 +
  17 +const RadioRegisters_t SX1276MB1xAS::RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE;
  18 +
  19 +SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events,
  20 + PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
  21 + PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
  22 + PinName antSwitch )
  23 + : SX1276( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 ),
  24 + AntSwitch( antSwitch ),
  25 + #if( defined ( TARGET_NUCLEO_L152RE ) )
  26 + Fake( D8 )
  27 + #else
  28 + Fake( A3 )
  29 + #endif
  30 +{
  31 + this->RadioEvents = events;
  32 +
  33 + Reset( );
  34 +
  35 + RxChainCalibration( );
  36 +
  37 + IoInit( );
  38 +
  39 + SetOpMode( RF_OPMODE_SLEEP );
  40 +
  41 + IoIrqInit( dioIrq );
  42 +
  43 + RadioRegistersInit( );
  44 +
  45 + SetModem( MODEM_FSK );
  46 +
  47 + this->settings.State = RF_IDLE ;
  48 +}
  49 +
  50 +SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events )
  51 + #if defined ( TARGET_NUCLEO_L152RE )
  52 + : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3
  53 + AntSwitch( A4 ),
  54 + Fake( D8 )
  55 + #elif defined( TARGET_LPC11U6X )
  56 + : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
  57 + AntSwitch( P0_23 ),
  58 + Fake( A3 )
  59 + #else
  60 + : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
  61 + AntSwitch( A4 ),
  62 + Fake( A3 )
  63 + #endif
  64 +{
  65 + this->RadioEvents = events;
  66 +
  67 + Reset( );
  68 +
  69 + boardConnected = UNKNOWN;
  70 +
  71 + DetectBoardType( );
  72 +
  73 + RxChainCalibration( );
  74 +
  75 + IoInit( );
  76 +
  77 + SetOpMode( RF_OPMODE_SLEEP );
  78 + IoIrqInit( dioIrq );
  79 +
  80 + RadioRegistersInit( );
  81 +
  82 + SetModem( MODEM_FSK );
  83 +
  84 + this->settings.State = RF_IDLE ;
  85 +}
  86 +
  87 +//-------------------------------------------------------------------------
  88 +// Board relative functions
  89 +//-------------------------------------------------------------------------
  90 +uint8_t SX1276MB1xAS::DetectBoardType( void )
  91 +{
  92 + if( boardConnected == UNKNOWN )
  93 + {
  94 + this->AntSwitch.input( );
  95 + wait_ms( 1 );
  96 + if( this->AntSwitch == 1 )
  97 + {
  98 + boardConnected = SX1276MB1LAS;
  99 + }
  100 + else
  101 + {
  102 + boardConnected = SX1276MB1MAS;
  103 + }
  104 + this->AntSwitch.output( );
  105 + wait_ms( 1 );
  106 + }
  107 + return ( boardConnected );
  108 +}
  109 +
  110 +void SX1276MB1xAS::IoInit( void )
  111 +{
  112 + AntSwInit( );
  113 + SpiInit( );
  114 +}
  115 +
  116 +void SX1276MB1xAS::RadioRegistersInit( )
  117 +{
  118 + uint8_t i = 0;
  119 + for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
  120 + {
  121 + SetModem( RadioRegsInit[i].Modem );
  122 + Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
  123 + }
  124 +}
  125 +
  126 +void SX1276MB1xAS::SpiInit( void )
  127 +{
  128 + nss = 1;
  129 + spi.format( 8,0 );
  130 + uint32_t frequencyToSet = 8000000;
  131 + #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) )
  132 + spi.frequency( frequencyToSet );
  133 + #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
  134 + spi.frequency( frequencyToSet * 2 );
  135 + #else
  136 + #warning "Check the board's SPI frequency"
  137 + #endif
  138 + wait(0.1);
  139 +}
  140 +
  141 +void SX1276MB1xAS::IoIrqInit( DioIrqHandler *irqHandlers )
  142 +{
  143 +#if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) )
  144 + dio0.mode( PullDown );
  145 + dio1.mode( PullDown );
  146 + dio2.mode( PullDown );
  147 + dio3.mode( PullDown );
  148 + dio4.mode( PullDown );
  149 +#endif
  150 + dio0.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[0] ) ) );
  151 + dio1.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[1] ) ) );
  152 + dio2.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[2] ) ) );
  153 + dio3.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[3] ) ) );
  154 + dio4.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[4] ) ) );
  155 +}
  156 +
  157 +void SX1276MB1xAS::IoDeInit( void )
  158 +{
  159 + //nothing
  160 +}
  161 +
  162 +void SX1276MB1xAS::SetRfTxPower( int8_t power )
  163 +{
  164 + uint8_t paConfig = 0;
  165 + uint8_t paDac = 0;
  166 +
  167 + paConfig = Read( REG_PACONFIG );
  168 + paDac = Read( REG_PADAC );
  169 +
  170 + paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
  171 + paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
  172 +
  173 + if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
  174 + {
  175 + if( power > 17 )
  176 + {
  177 + paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
  178 + }
  179 + else
  180 + {
  181 + paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
  182 + }
  183 + if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
  184 + {
  185 + if( power < 5 )
  186 + {
  187 + power = 5;
  188 + }
  189 + if( power > 20 )
  190 + {
  191 + power = 20;
  192 + }
  193 + paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
  194 + }
  195 + else
  196 + {
  197 + if( power < 2 )
  198 + {
  199 + power = 2;
  200 + }
  201 + if( power > 17 )
  202 + {
  203 + power = 17;
  204 + }
  205 + paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
  206 + }
  207 + }
  208 + else
  209 + {
  210 + if( power < -1 )
  211 + {
  212 + power = -1;
  213 + }
  214 + if( power > 14 )
  215 + {
  216 + power = 14;
  217 + }
  218 + paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
  219 + }
  220 + Write( REG_PACONFIG, paConfig );
  221 + Write( REG_PADAC, paDac );
  222 +}
  223 +
  224 +uint8_t SX1276MB1xAS::GetPaSelect( uint32_t channel )
  225 +{
  226 + if( channel > RF_MID_BAND_THRESH )
  227 + {
  228 + if( boardConnected == SX1276MB1LAS )
  229 + {
  230 + return RF_PACONFIG_PASELECT_PABOOST;
  231 + }
  232 + else
  233 + {
  234 + return RF_PACONFIG_PASELECT_RFO;
  235 + }
  236 + }
  237 + else
  238 + {
  239 + return RF_PACONFIG_PASELECT_RFO;
  240 + }
  241 +}
  242 +
  243 +void SX1276MB1xAS::SetAntSwLowPower( bool status )
  244 +{
  245 + if( isRadioActive != status )
  246 + {
  247 + isRadioActive = status;
  248 +
  249 + if( status == false )
  250 + {
  251 + AntSwInit( );
  252 + }
  253 + else
  254 + {
  255 + AntSwDeInit( );
  256 + }
  257 + }
  258 +}
  259 +
  260 +void SX1276MB1xAS::AntSwInit( void )
  261 +{
  262 + this->AntSwitch = 0;
  263 +}
  264 +
  265 +void SX1276MB1xAS::AntSwDeInit( void )
  266 +{
  267 + this->AntSwitch = 0;
  268 +}
  269 +
  270 +void SX1276MB1xAS::SetAntSw( uint8_t opMode )
  271 +{
  272 + switch( opMode )
  273 + {
  274 + case RFLR_OPMODE_TRANSMITTER:
  275 + this->AntSwitch = 1;
  276 + break;
  277 + case RFLR_OPMODE_RECEIVER:
  278 + case RFLR_OPMODE_RECEIVER_SINGLE:
  279 + case RFLR_OPMODE_CAD:
  280 + this->AntSwitch = 0;
  281 + break;
  282 + default:
  283 + this->AntSwitch = 0;
  284 + break;
  285 + }
  286 +}
  287 +
  288 +bool SX1276MB1xAS::CheckRfFrequency( uint32_t frequency )
  289 +{
  290 + // Implement check. Currently all frequencies are supported
  291 + return true;
  292 +}
  293 +
  294 +void SX1276MB1xAS::Reset( void )
  295 +{
  296 + reset.output( );
  297 + reset = 0;
  298 + wait_ms( 1 );
  299 + reset.input( );
  300 + wait_ms( 6 );
  301 +}
  302 +
  303 +void SX1276MB1xAS::Write( uint8_t addr, uint8_t data )
  304 +{
  305 + Write( addr, &data, 1 );
  306 +}
  307 +
  308 +uint8_t SX1276MB1xAS::Read( uint8_t addr )
  309 +{
  310 + uint8_t data;
  311 + Read( addr, &data, 1 );
  312 + return data;
  313 +}
  314 +
  315 +void SX1276MB1xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
  316 +{
  317 + uint8_t i;
  318 +
  319 + nss = 0;
  320 + spi.write( addr | 0x80 );
  321 + for( i = 0; i < size; i++ )
  322 + {
  323 + spi.write( buffer[i] );
  324 + }
  325 + nss = 1;
  326 +}
  327 +
  328 +void SX1276MB1xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
  329 +{
  330 + uint8_t i;
  331 +
  332 + nss = 0;
  333 + spi.write( addr & 0x7F );
  334 + for( i = 0; i < size; i++ )
  335 + {
  336 + buffer[i] = spi.write( 0 );
  337 + }
  338 + nss = 1;
  339 +}
  340 +
  341 +void SX1276MB1xAS::WriteFifo( uint8_t *buffer, uint8_t size )
  342 +{
  343 + Write( 0, buffer, size );
  344 +}
  345 +
  346 +void SX1276MB1xAS::ReadFifo( uint8_t *buffer, uint8_t size )
  347 +{
  348 + Read( 0, buffer, size );
  349 +}
... ...
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  1 +/*
  2 + / _____) _ | |
  3 +( (____ _____ ____ _| |_ _____ ____| |__
  4 + \____ \| ___ | (_ _) ___ |/ ___) _ \
  5 + _____) ) ____| | | || |_| ____( (___| | | |
  6 +(______/|_____)_|_|_| \__)_____)\____)_| |_|
  7 + (C) 2014 Semtech
  8 +
  9 +Description: -
  10 +
  11 +License: Revised BSD License, see LICENSE.TXT file include in the project
  12 +
  13 +Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
  14 +*/
  15 +#ifndef __SX1276_HAL_H__
  16 +#define __SX1276_HAL_H__
  17 +#include "sx1276.h"
  18 +
  19 +/*!
  20 + * @brief Radio hardware registers initialization definition
  21 + *
  22 + * @remark Can be automatically generated by the SX1276 GUI (not yet implemented)
  23 + */
  24 +#define RADIO_INIT_REGISTERS_VALUE \
  25 +{ \
  26 + { MODEM_FSK , REG_LNA , 0x23 },\
  27 + { MODEM_FSK , REG_RXCONFIG , 0x1E },\
  28 + { MODEM_FSK , REG_RSSICONFIG , 0xD2 },\
  29 + { MODEM_FSK , REG_AFCFEI , 0x01 },\
  30 + { MODEM_FSK , REG_PREAMBLEDETECT , 0xAA },\
  31 + { MODEM_FSK , REG_OSC , 0x07 },\
  32 + { MODEM_FSK , REG_SYNCCONFIG , 0x12 },\
  33 + { MODEM_FSK , REG_SYNCVALUE1 , 0xC1 },\
  34 + { MODEM_FSK , REG_SYNCVALUE2 , 0x94 },\
  35 + { MODEM_FSK , REG_SYNCVALUE3 , 0xC1 },\
  36 + { MODEM_FSK , REG_PACKETCONFIG1 , 0xD8 },\
  37 + { MODEM_FSK , REG_FIFOTHRESH , 0x8F },\
  38 + { MODEM_FSK , REG_IMAGECAL , 0x02 },\
  39 + { MODEM_FSK , REG_DIOMAPPING1 , 0x00 },\
  40 + { MODEM_FSK , REG_DIOMAPPING2 , 0x30 },\
  41 + { MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },\
  42 +} \
  43 +
  44 +/*!
  45 + * Actual implementation of a SX1276 radio, includes some modifications to make it compatible with the MB1 LAS board
  46 + */
  47 +class SX1276MB1xAS : public SX1276
  48 +{
  49 +protected:
  50 + /*!
  51 + * Antenna switch GPIO pins objects
  52 + */
  53 + DigitalInOut AntSwitch;
  54 + DigitalIn Fake;
  55 +
  56 +private:
  57 + static const RadioRegisters_t RadioRegsInit[];
  58 +
  59 +public:
  60 + SX1276MB1xAS( RadioEvents_t *events,
  61 + PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
  62 + PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
  63 + PinName antSwitch );
  64 +
  65 + SX1276MB1xAS( RadioEvents_t *events );
  66 +
  67 + virtual ~SX1276MB1xAS( ) { };
  68 +
  69 +protected:
  70 + /*!
  71 + * @brief Initializes the radio I/Os pins interface
  72 + */
  73 + virtual void IoInit( void );
  74 +
  75 + /*!
  76 + * @brief Initializes the radio registers
  77 + */
  78 + virtual void RadioRegistersInit( );
  79 +
  80 + /*!
  81 + * @brief Initializes the radio SPI
  82 + */
  83 + virtual void SpiInit( void );
  84 +
  85 + /*!
  86 + * @brief Initializes DIO IRQ handlers
  87 + *
  88 + * @param [IN] irqHandlers Array containing the IRQ callback functions
  89 + */
  90 + virtual void IoIrqInit( DioIrqHandler *irqHandlers );
  91 +
  92 + /*!
  93 + * @brief De-initializes the radio I/Os pins interface.
  94 + *
  95 + * \remark Useful when going in MCU lowpower modes
  96 + */
  97 + virtual void IoDeInit( void );
  98 +
  99 + /*!
  100 + * \brief Sets the radio output power.
  101 + *
  102 + * @param [IN] power Sets the RF output power
  103 + */
  104 + virtual void SetRfTxPower( int8_t power );
  105 +
  106 + /*!
  107 + * @brief Gets the board PA selection configuration
  108 + *
  109 + * @param [IN] channel Channel frequency in Hz
  110 + * @retval PaSelect RegPaConfig PaSelect value
  111 + */
  112 + virtual uint8_t GetPaSelect( uint32_t channel );
  113 +
  114 + /*!
  115 + * @brief Set the RF Switch I/Os pins in Low Power mode
  116 + *
  117 + * @param [IN] status enable or disable
  118 + */
  119 + virtual void SetAntSwLowPower( bool status );
  120 +
  121 + /*!
  122 + * @brief Initializes the RF Switch I/Os pins interface
  123 + */
  124 + virtual void AntSwInit( void );
  125 +
  126 + /*!
  127 + * @brief De-initializes the RF Switch I/Os pins interface
  128 + *
  129 + * @remark Needed to decrease the power consumption in MCU lowpower modes
  130 + */
  131 + virtual void AntSwDeInit( void );
  132 +
  133 + /*!
  134 + * @brief Controls the antena switch if necessary.
  135 + *
  136 + * @remark see errata note
  137 + *
  138 + * @param [IN] opMode Current radio operating mode
  139 + */
  140 + virtual void SetAntSw( uint8_t opMode );
  141 +
  142 +public:
  143 + /*!
  144 + * @brief Detect the board connected by reading the value of the antenna switch pin
  145 + */
  146 + virtual uint8_t DetectBoardType( void );
  147 +
  148 + /*!
  149 + * @brief Checks if the given RF frequency is supported by the hardware
  150 + *
  151 + * @param [IN] frequency RF frequency to be checked
  152 + * @retval isSupported [true: supported, false: unsupported]
  153 + */
  154 + virtual bool CheckRfFrequency( uint32_t frequency );
  155 +
  156 + /*!
  157 + * @brief Writes the radio register at the specified address
  158 + *
  159 + * @param [IN]: addr Register address
  160 + * @param [IN]: data New register value
  161 + */
  162 + virtual void Write ( uint8_t addr, uint8_t data ) ;
  163 +
  164 + /*!
  165 + * @brief Reads the radio register at the specified address
  166 + *
  167 + * @param [IN]: addr Register address
  168 + * @retval data Register value
  169 + */
  170 + virtual uint8_t Read ( uint8_t addr ) ;
  171 +
  172 + /*!
  173 + * @brief Writes multiple radio registers starting at address
  174 + *
  175 + * @param [IN] addr First Radio register address
  176 + * @param [IN] buffer Buffer containing the new register's values
  177 + * @param [IN] size Number of registers to be written
  178 + */
  179 + virtual void Write( uint8_t addr, uint8_t *buffer, uint8_t size ) ;
  180 +
  181 + /*!
  182 + * @brief Reads multiple radio registers starting at address
  183 + *
  184 + * @param [IN] addr First Radio register address
  185 + * @param [OUT] buffer Buffer where to copy the registers data
  186 + * @param [IN] size Number of registers to be read
  187 + */
  188 + virtual void Read ( uint8_t addr, uint8_t *buffer, uint8_t size ) ;
  189 +
  190 + /*!
  191 + * @brief Writes the buffer contents to the SX1276 FIFO
  192 + *
  193 + * @param [IN] buffer Buffer containing data to be put on the FIFO.
  194 + * @param [IN] size Number of bytes to be written to the FIFO
  195 + */
  196 + virtual void WriteFifo( uint8_t *buffer, uint8_t size ) ;
  197 +
  198 + /*!
  199 + * @brief Reads the contents of the SX1276 FIFO
  200 + *
  201 + * @param [OUT] buffer Buffer where to copy the FIFO read data.
  202 + * @param [IN] size Number of bytes to be read from the FIFO
  203 + */
  204 + virtual void ReadFifo( uint8_t *buffer, uint8_t size ) ;
  205 +
  206 + /*!
  207 + * @brief Reset the SX1276
  208 + */
  209 + virtual void Reset( void );
  210 +};
  211 +
  212 +#endif // __SX1276_HAL_H__
... ...
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  1 +/*
  2 + / _____) _ | |
  3 +( (____ _____ ____ _| |_ _____ ____| |__
  4 + \____ \| ___ | (_ _) ___ |/ ___) _ \
  5 + _____) ) ____| | | || |_| ____( (___| | | |
  6 +(______/|_____)_|_|_| \__)_____)\____)_| |_|
  7 + (C) 2014 Semtech
  8 +
  9 +Description: Actual implementation of a SX1276 radio, inherits Radio
  10 +
  11 +License: Revised BSD License, see LICENSE.TXT file include in the project
  12 +
  13 +Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
  14 +*/
  15 +#include "sx1276.h"
  16 +
  17 +const FskBandwidth_t SX1276::FskBandwidths[] =
  18 +{
  19 + { 2600 , 0x17 },
  20 + { 3100 , 0x0F },
  21 + { 3900 , 0x07 },
  22 + { 5200 , 0x16 },
  23 + { 6300 , 0x0E },
  24 + { 7800 , 0x06 },
  25 + { 10400 , 0x15 },
  26 + { 12500 , 0x0D },
  27 + { 15600 , 0x05 },
  28 + { 20800 , 0x14 },
  29 + { 25000 , 0x0C },
  30 + { 31300 , 0x04 },
  31 + { 41700 , 0x13 },
  32 + { 50000 , 0x0B },
  33 + { 62500 , 0x03 },
  34 + { 83333 , 0x12 },
  35 + { 100000, 0x0A },
  36 + { 125000, 0x02 },
  37 + { 166700, 0x11 },
  38 + { 200000, 0x09 },
  39 + { 250000, 0x01 },
  40 + { 300000, 0x00 }, // Invalid Bandwidth
  41 +};
  42 +
  43 +
  44 +SX1276::SX1276( RadioEvents_t *events,
  45 + PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
  46 + PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
  47 + : Radio( events ),
  48 + spi( mosi, miso, sclk ),
  49 + nss( nss ),
  50 + reset( reset ),
  51 + dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
  52 + isRadioActive( false )
  53 +{
  54 + wait_ms( 10 );
  55 + this->rxtxBuffer = new uint8_t[RX_BUFFER_SIZE];
  56 +
  57 + this->RadioEvents = events;
  58 +
  59 + this->dioIrq = new DioIrqHandler[6];
  60 +
  61 + this->dioIrq[0] = &SX1276::OnDio0Irq;
  62 + this->dioIrq[1] = &SX1276::OnDio1Irq;
  63 + this->dioIrq[2] = &SX1276::OnDio2Irq;
  64 + this->dioIrq[3] = &SX1276::OnDio3Irq;
  65 + this->dioIrq[4] = &SX1276::OnDio4Irq;
  66 + this->dioIrq[5] = NULL;
  67 +
  68 + this->settings.State = RF_IDLE;
  69 +}
  70 +
  71 +SX1276::~SX1276( )
  72 +{
  73 + delete this->rxtxBuffer;
  74 + delete this->dioIrq;
  75 +}
  76 +
  77 +void SX1276::Init( RadioEvents_t *events )
  78 +{
  79 + this->RadioEvents = events;
  80 +}
  81 +
  82 +RadioState SX1276::GetStatus( void )
  83 +{
  84 + return this->settings.State;
  85 +}
  86 +
  87 +void SX1276::SetChannel( uint32_t freq )
  88 +{
  89 + this->settings.Channel = freq;
  90 + freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
  91 + Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
  92 + Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
  93 + Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
  94 +}
  95 +
  96 +bool SX1276::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
  97 +{
  98 + int16_t rssi = 0;
  99 +
  100 + SetModem( modem );
  101 +
  102 + SetChannel( freq );
  103 +
  104 + SetOpMode( RF_OPMODE_RECEIVER );
  105 +
  106 + wait_ms( 1 );
  107 +
  108 + rssi = GetRssi( modem );
  109 +
  110 + Sleep( );
  111 +
  112 + if( rssi > rssiThresh )
  113 + {
  114 + return false;
  115 + }
  116 + return true;
  117 +}
  118 +
  119 +uint32_t SX1276::Random( void )
  120 +{
  121 + uint8_t i;
  122 + uint32_t rnd = 0;
  123 +
  124 + /*
  125 + * Radio setup for random number generation
  126 + */
  127 + // Set LoRa modem ON
  128 + SetModem( MODEM_LORA );
  129 +
  130 + // Disable LoRa modem interrupts
  131 + Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
  132 + RFLR_IRQFLAGS_RXDONE |
  133 + RFLR_IRQFLAGS_PAYLOADCRCERROR |
  134 + RFLR_IRQFLAGS_VALIDHEADER |
  135 + RFLR_IRQFLAGS_TXDONE |
  136 + RFLR_IRQFLAGS_CADDONE |
  137 + RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
  138 + RFLR_IRQFLAGS_CADDETECTED );
  139 +
  140 + // Set radio in continuous reception
  141 + SetOpMode( RF_OPMODE_RECEIVER );
  142 +
  143 + for( i = 0; i < 32; i++ )
  144 + {
  145 + wait_ms( 1 );
  146 + // Unfiltered RSSI value reading. Only takes the LSB value
  147 + rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
  148 + }
  149 +
  150 + Sleep( );
  151 +
  152 + return rnd;
  153 +}
  154 +
  155 +/*!
  156 + * Performs the Rx chain calibration for LF and HF bands
  157 + * \remark Must be called just after the reset so all registers are at their
  158 + * default values
  159 + */
  160 +void SX1276::RxChainCalibration( void )
  161 +{
  162 + uint8_t regPaConfigInitVal;
  163 + uint32_t initialFreq;
  164 +
  165 + // Save context
  166 + regPaConfigInitVal = this->Read( REG_PACONFIG );
  167 + initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
  168 + ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
  169 + ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
  170 +
  171 + // Cut the PA just in case, RFO output, power = -1 dBm
  172 + this->Write( REG_PACONFIG, 0x00 );
  173 +
  174 + // Launch Rx chain calibration for LF band
  175 + Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
  176 + while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
  177 + {
  178 + }
  179 +
  180 + // Sets a Frequency in HF band
  181 + SetChannel( 868000000 );
  182 +
  183 + // Launch Rx chain calibration for HF band
  184 + Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
  185 + while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
  186 + {
  187 + }
  188 +
  189 + // Restore context
  190 + this->Write( REG_PACONFIG, regPaConfigInitVal );
  191 + SetChannel( initialFreq );
  192 +}
  193 +
  194 +/*!
  195 + * Returns the known FSK bandwidth registers value
  196 + *
  197 + * \param [IN] bandwidth Bandwidth value in Hz
  198 + * \retval regValue Bandwidth register value.
  199 + */
  200 +uint8_t SX1276::GetFskBandwidthRegValue( uint32_t bandwidth )
  201 +{
  202 + uint8_t i;
  203 +
  204 + for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
  205 + {
  206 + if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
  207 + {
  208 + return FskBandwidths[i].RegValue;
  209 + }
  210 + }
  211 + // ERROR: Value not found
  212 + while( 1 );
  213 +}
  214 +
  215 +void SX1276::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
  216 + uint32_t datarate, uint8_t coderate,
  217 + uint32_t bandwidthAfc, uint16_t preambleLen,
  218 + uint16_t symbTimeout, bool fixLen,
  219 + uint8_t payloadLen,
  220 + bool crcOn, bool freqHopOn, uint8_t hopPeriod,
  221 + bool iqInverted, bool rxContinuous )
  222 +{
  223 + SetModem( modem );
  224 +
  225 + switch( modem )
  226 + {
  227 + case MODEM_FSK:
  228 + {
  229 + this->settings.Fsk.Bandwidth = bandwidth;
  230 + this->settings.Fsk.Datarate = datarate;
  231 + this->settings.Fsk.BandwidthAfc = bandwidthAfc;
  232 + this->settings.Fsk.FixLen = fixLen;
  233 + this->settings.Fsk.PayloadLen = payloadLen;
  234 + this->settings.Fsk.CrcOn = crcOn;
  235 + this->settings.Fsk.IqInverted = iqInverted;
  236 + this->settings.Fsk.RxContinuous = rxContinuous;
  237 + this->settings.Fsk.PreambleLen = preambleLen;
  238 + this->settings.Fsk.RxSingleTimeout = symbTimeout * ( ( 1.0 / ( double )datarate ) * 8.0 ) * 1e3;
  239 +
  240 + datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
  241 + Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
  242 + Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
  243 +
  244 + Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
  245 + Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
  246 +
  247 + Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
  248 + Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
  249 +
  250 + if( fixLen == 1 )
  251 + {
  252 + Write( REG_PAYLOADLENGTH, payloadLen );
  253 + }
  254 + else
  255 + {
  256 + Write( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum
  257 + }
  258 +
  259 + Write( REG_PACKETCONFIG1,
  260 + ( Read( REG_PACKETCONFIG1 ) &
  261 + RF_PACKETCONFIG1_CRC_MASK &
  262 + RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
  263 + ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
  264 + ( crcOn << 4 ) );
  265 + Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
  266 + }
  267 + break;
  268 + case MODEM_LORA:
  269 + {
  270 + if( bandwidth > 2 )
  271 + {
  272 + // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
  273 + while( 1 );
  274 + }
  275 + bandwidth += 7;
  276 + this->settings.LoRa.Bandwidth = bandwidth;
  277 + this->settings.LoRa.Datarate = datarate;
  278 + this->settings.LoRa.Coderate = coderate;
  279 + this->settings.LoRa.PreambleLen = preambleLen;
  280 + this->settings.LoRa.FixLen = fixLen;
  281 + this->settings.LoRa.PayloadLen = payloadLen;
  282 + this->settings.LoRa.CrcOn = crcOn;
  283 + this->settings.LoRa.FreqHopOn = freqHopOn;
  284 + this->settings.LoRa.HopPeriod = hopPeriod;
  285 + this->settings.LoRa.IqInverted = iqInverted;
  286 + this->settings.LoRa.RxContinuous = rxContinuous;
  287 +
  288 + if( datarate > 12 )
  289 + {
  290 + datarate = 12;
  291 + }
  292 + else if( datarate < 6 )
  293 + {
  294 + datarate = 6;
  295 + }
  296 +
  297 + if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
  298 + ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
  299 + {
  300 + this->settings.LoRa.LowDatarateOptimize = 0x01;
  301 + }
  302 + else
  303 + {
  304 + this->settings.LoRa.LowDatarateOptimize = 0x00;
  305 + }
  306 +
  307 + Write( REG_LR_MODEMCONFIG1,
  308 + ( Read( REG_LR_MODEMCONFIG1 ) &
  309 + RFLR_MODEMCONFIG1_BW_MASK &
  310 + RFLR_MODEMCONFIG1_CODINGRATE_MASK &
  311 + RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
  312 + ( bandwidth << 4 ) | ( coderate << 1 ) |
  313 + fixLen );
  314 +
  315 + Write( REG_LR_MODEMCONFIG2,
  316 + ( Read( REG_LR_MODEMCONFIG2 ) &
  317 + RFLR_MODEMCONFIG2_SF_MASK &
  318 + RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
  319 + RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
  320 + ( datarate << 4 ) | ( crcOn << 2 ) |
  321 + ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
  322 +
  323 + Write( REG_LR_MODEMCONFIG3,
  324 + ( Read( REG_LR_MODEMCONFIG3 ) &
  325 + RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
  326 + ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
  327 +
  328 + Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
  329 +
  330 + Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
  331 + Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
  332 +
  333 + if( fixLen == 1 )
  334 + {
  335 + Write( REG_LR_PAYLOADLENGTH, payloadLen );
  336 + }
  337 +
  338 + if( this->settings.LoRa.FreqHopOn == true )
  339 + {
  340 + Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
  341 + Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
  342 + }
  343 +
  344 + if( ( bandwidth == 9 ) && ( this->settings.Channel > RF_MID_BAND_THRESH ) )
  345 + {
  346 + // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
  347 + Write( REG_LR_TEST36, 0x02 );
  348 + Write( REG_LR_TEST3A, 0x64 );
  349 + }
  350 + else if( bandwidth == 9 )
  351 + {
  352 + // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
  353 + Write( REG_LR_TEST36, 0x02 );
  354 + Write( REG_LR_TEST3A, 0x7F );
  355 + }
  356 + else
  357 + {
  358 + // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
  359 + Write( REG_LR_TEST36, 0x03 );
  360 + }
  361 +
  362 + if( datarate == 6 )
  363 + {
  364 + Write( REG_LR_DETECTOPTIMIZE,
  365 + ( Read( REG_LR_DETECTOPTIMIZE ) &
  366 + RFLR_DETECTIONOPTIMIZE_MASK ) |
  367 + RFLR_DETECTIONOPTIMIZE_SF6 );
  368 + Write( REG_LR_DETECTIONTHRESHOLD,
  369 + RFLR_DETECTIONTHRESH_SF6 );
  370 + }
  371 + else
  372 + {
  373 + Write( REG_LR_DETECTOPTIMIZE,
  374 + ( Read( REG_LR_DETECTOPTIMIZE ) &
  375 + RFLR_DETECTIONOPTIMIZE_MASK ) |
  376 + RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
  377 + Write( REG_LR_DETECTIONTHRESHOLD,
  378 + RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
  379 + }
  380 + }
  381 + break;
  382 + }
  383 +}
  384 +
  385 +void SX1276::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
  386 + uint32_t bandwidth, uint32_t datarate,
  387 + uint8_t coderate, uint16_t preambleLen,
  388 + bool fixLen, bool crcOn, bool freqHopOn,
  389 + uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
  390 +{
  391 + SetModem( modem );
  392 +
  393 + SetRfTxPower( power );
  394 +
  395 + switch( modem )
  396 + {
  397 + case MODEM_FSK:
  398 + {
  399 + this->settings.Fsk.Power = power;
  400 + this->settings.Fsk.Fdev = fdev;
  401 + this->settings.Fsk.Bandwidth = bandwidth;
  402 + this->settings.Fsk.Datarate = datarate;
  403 + this->settings.Fsk.PreambleLen = preambleLen;
  404 + this->settings.Fsk.FixLen = fixLen;
  405 + this->settings.Fsk.CrcOn = crcOn;
  406 + this->settings.Fsk.IqInverted = iqInverted;
  407 + this->settings.Fsk.TxTimeout = timeout;
  408 +
  409 + fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
  410 + Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
  411 + Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
  412 +
  413 + datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
  414 + Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
  415 + Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
  416 +
  417 + Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
  418 + Write( REG_PREAMBLELSB, preambleLen & 0xFF );
  419 +
  420 + Write( REG_PACKETCONFIG1,
  421 + ( Read( REG_PACKETCONFIG1 ) &
  422 + RF_PACKETCONFIG1_CRC_MASK &
  423 + RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
  424 + ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
  425 + ( crcOn << 4 ) );
  426 + Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
  427 + }
  428 + break;
  429 + case MODEM_LORA:
  430 + {
  431 + this->settings.LoRa.Power = power;
  432 + if( bandwidth > 2 )
  433 + {
  434 + // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
  435 + while( 1 );
  436 + }
  437 + bandwidth += 7;
  438 + this->settings.LoRa.Bandwidth = bandwidth;
  439 + this->settings.LoRa.Datarate = datarate;
  440 + this->settings.LoRa.Coderate = coderate;
  441 + this->settings.LoRa.PreambleLen = preambleLen;
  442 + this->settings.LoRa.FixLen = fixLen;
  443 + this->settings.LoRa.FreqHopOn = freqHopOn;
  444 + this->settings.LoRa.HopPeriod = hopPeriod;
  445 + this->settings.LoRa.CrcOn = crcOn;
  446 + this->settings.LoRa.IqInverted = iqInverted;
  447 + this->settings.LoRa.TxTimeout = timeout;
  448 +
  449 + if( datarate > 12 )
  450 + {
  451 + datarate = 12;
  452 + }
  453 + else if( datarate < 6 )
  454 + {
  455 + datarate = 6;
  456 + }
  457 + if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
  458 + ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
  459 + {
  460 + this->settings.LoRa.LowDatarateOptimize = 0x01;
  461 + }
  462 + else
  463 + {
  464 + this->settings.LoRa.LowDatarateOptimize = 0x00;
  465 + }
  466 +
  467 + if( this->settings.LoRa.FreqHopOn == true )
  468 + {
  469 + Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
  470 + Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
  471 + }
  472 +
  473 + Write( REG_LR_MODEMCONFIG1,
  474 + ( Read( REG_LR_MODEMCONFIG1 ) &
  475 + RFLR_MODEMCONFIG1_BW_MASK &
  476 + RFLR_MODEMCONFIG1_CODINGRATE_MASK &
  477 + RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
  478 + ( bandwidth << 4 ) | ( coderate << 1 ) |
  479 + fixLen );
  480 +
  481 + Write( REG_LR_MODEMCONFIG2,
  482 + ( Read( REG_LR_MODEMCONFIG2 ) &
  483 + RFLR_MODEMCONFIG2_SF_MASK &
  484 + RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
  485 + ( datarate << 4 ) | ( crcOn << 2 ) );
  486 +
  487 + Write( REG_LR_MODEMCONFIG3,
  488 + ( Read( REG_LR_MODEMCONFIG3 ) &
  489 + RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
  490 + ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
  491 +
  492 + Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
  493 + Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
  494 +
  495 + if( datarate == 6 )
  496 + {
  497 + Write( REG_LR_DETECTOPTIMIZE,
  498 + ( Read( REG_LR_DETECTOPTIMIZE ) &
  499 + RFLR_DETECTIONOPTIMIZE_MASK ) |
  500 + RFLR_DETECTIONOPTIMIZE_SF6 );
  501 + Write( REG_LR_DETECTIONTHRESHOLD,
  502 + RFLR_DETECTIONTHRESH_SF6 );
  503 + }
  504 + else
  505 + {
  506 + Write( REG_LR_DETECTOPTIMIZE,
  507 + ( Read( REG_LR_DETECTOPTIMIZE ) &
  508 + RFLR_DETECTIONOPTIMIZE_MASK ) |
  509 + RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
  510 + Write( REG_LR_DETECTIONTHRESHOLD,
  511 + RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
  512 + }
  513 + }
  514 + break;
  515 + }
  516 +}
  517 +
  518 +uint32_t SX1276::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
  519 +{
  520 + uint32_t airTime = 0;
  521 +
  522 + switch( modem )
  523 + {
  524 + case MODEM_FSK:
  525 + {
  526 + airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
  527 + ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
  528 + ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
  529 + ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
  530 + pktLen +
  531 + ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
  532 + this->settings.Fsk.Datarate ) * 1e3 );
  533 + }
  534 + break;
  535 + case MODEM_LORA:
  536 + {
  537 + double bw = 0.0;
  538 + // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
  539 + switch( this->settings.LoRa.Bandwidth )
  540 + {
  541 + //case 0: // 7.8 kHz
  542 + // bw = 78e2;
  543 + // break;
  544 + //case 1: // 10.4 kHz
  545 + // bw = 104e2;
  546 + // break;
  547 + //case 2: // 15.6 kHz
  548 + // bw = 156e2;
  549 + // break;
  550 + //case 3: // 20.8 kHz
  551 + // bw = 208e2;
  552 + // break;
  553 + //case 4: // 31.2 kHz
  554 + // bw = 312e2;
  555 + // break;
  556 + //case 5: // 41.4 kHz
  557 + // bw = 414e2;
  558 + // break;
  559 + //case 6: // 62.5 kHz
  560 + // bw = 625e2;
  561 + // break;
  562 + case 7: // 125 kHz
  563 + bw = 125e3;
  564 + break;
  565 + case 8: // 250 kHz
  566 + bw = 250e3;
  567 + break;
  568 + case 9: // 500 kHz
  569 + bw = 500e3;
  570 + break;
  571 + }
  572 +
  573 + // Symbol rate : time for one symbol (secs)
  574 + double rs = bw / ( 1 << this->settings.LoRa.Datarate );
  575 + double ts = 1 / rs;
  576 + // time of preamble
  577 + double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
  578 + // Symbol length of payload and time
  579 + double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
  580 + 28 + 16 * this->settings.LoRa.CrcOn -
  581 + ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
  582 + ( double )( 4 * ( this->settings.LoRa.Datarate -
  583 + ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) ) *
  584 + ( this->settings.LoRa.Coderate + 4 );
  585 + double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
  586 + double tPayload = nPayload * ts;
  587 + // Time on air
  588 + double tOnAir = tPreamble + tPayload;
  589 + // return ms secs
  590 + airTime = floor( tOnAir * 1e3 + 0.999 );
  591 + }
  592 + break;
  593 + }
  594 + return airTime;
  595 +}
  596 +
  597 +void SX1276::Send( uint8_t *buffer, uint8_t size )
  598 +{
  599 + uint32_t txTimeout = 0;
  600 +
  601 + switch( this->settings.Modem )
  602 + {
  603 + case MODEM_FSK:
  604 + {
  605 + this->settings.FskPacketHandler.NbBytes = 0;
  606 + this->settings.FskPacketHandler.Size = size;
  607 +
  608 + if( this->settings.Fsk.FixLen == false )
  609 + {
  610 + WriteFifo( ( uint8_t* )&size, 1 );
  611 + }
  612 + else
  613 + {
  614 + Write( REG_PAYLOADLENGTH, size );
  615 + }
  616 +
  617 + if( ( size > 0 ) && ( size <= 64 ) )
  618 + {
  619 + this->settings.FskPacketHandler.ChunkSize = size;
  620 + }
  621 + else
  622 + {
  623 + memcpy( rxtxBuffer, buffer, size );
  624 + this->settings.FskPacketHandler.ChunkSize = 32;
  625 + }
  626 +
  627 + // Write payload buffer
  628 + WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
  629 + this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
  630 + txTimeout = this->settings.Fsk.TxTimeout;
  631 + }
  632 + break;
  633 + case MODEM_LORA:
  634 + {
  635 + if( this->settings.LoRa.IqInverted == true )
  636 + {
  637 + Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
  638 + Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
  639 + }
  640 + else
  641 + {
  642 + Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
  643 + Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
  644 + }
  645 +
  646 + this->settings.LoRaPacketHandler.Size = size;
  647 +
  648 + // Initializes the payload size
  649 + Write( REG_LR_PAYLOADLENGTH, size );
  650 +
  651 + // Full buffer used for Tx
  652 + Write( REG_LR_FIFOTXBASEADDR, 0 );
  653 + Write( REG_LR_FIFOADDRPTR, 0 );
  654 +
  655 + // FIFO operations can not take place in Sleep mode
  656 + if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
  657 + {
  658 + Standby( );
  659 + wait_ms( 1 );
  660 + }
  661 + // Write payload buffer
  662 + WriteFifo( buffer, size );
  663 + txTimeout = this->settings.LoRa.TxTimeout;
  664 + }
  665 + break;
  666 + }
  667 +
  668 + Tx( txTimeout );
  669 +}
  670 +
  671 +void SX1276::Sleep( void )
  672 +{
  673 + txTimeoutTimer.detach( );
  674 + rxTimeoutTimer.detach( );
  675 +
  676 + SetOpMode( RF_OPMODE_SLEEP );
  677 + this->settings.State = RF_IDLE;
  678 +}
  679 +
  680 +void SX1276::Standby( void )
  681 +{
  682 + txTimeoutTimer.detach( );
  683 + rxTimeoutTimer.detach( );
  684 +
  685 + SetOpMode( RF_OPMODE_STANDBY );
  686 + this->settings.State = RF_IDLE;
  687 +}
  688 +
  689 +void SX1276::Rx( uint32_t timeout )
  690 +{
  691 + bool rxContinuous = false;
  692 +
  693 + switch( this->settings.Modem )
  694 + {
  695 + case MODEM_FSK:
  696 + {
  697 + rxContinuous = this->settings.Fsk.RxContinuous;
  698 +
  699 + // DIO0=PayloadReady
  700 + // DIO1=FifoLevel
  701 + // DIO2=SyncAddr
  702 + // DIO3=FifoEmpty
  703 + // DIO4=Preamble
  704 + // DIO5=ModeReady
  705 + Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
  706 + RF_DIOMAPPING1_DIO1_MASK &
  707 + RF_DIOMAPPING1_DIO2_MASK ) |
  708 + RF_DIOMAPPING1_DIO0_00 |
  709 + RF_DIOMAPPING1_DIO1_00 |
  710 + RF_DIOMAPPING1_DIO2_11 );
  711 +
  712 + Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
  713 + RF_DIOMAPPING2_MAP_MASK ) |
  714 + RF_DIOMAPPING2_DIO4_11 |
  715 + RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
  716 +
  717 + this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
  718 +
  719 + Write( REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT );
  720 +
  721 + this->settings.FskPacketHandler.PreambleDetected = false;
  722 + this->settings.FskPacketHandler.SyncWordDetected = false;
  723 + this->settings.FskPacketHandler.NbBytes = 0;
  724 + this->settings.FskPacketHandler.Size = 0;
  725 + }
  726 + break;
  727 + case MODEM_LORA:
  728 + {
  729 + if( this->settings.LoRa.IqInverted == true )
  730 + {
  731 + Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
  732 + Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
  733 + }
  734 + else
  735 + {
  736 + Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
  737 + Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
  738 + }
  739 +
  740 + // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal
  741 + if( this->settings.LoRa.Bandwidth < 9 )
  742 + {
  743 + Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) & 0x7F );
  744 + Write( REG_LR_TEST30, 0x00 );
  745 + switch( this->settings.LoRa.Bandwidth )
  746 + {
  747 + case 0: // 7.8 kHz
  748 + Write( REG_LR_TEST2F, 0x48 );
  749 + SetChannel(this->settings.Channel + 7.81e3 );
  750 + break;
  751 + case 1: // 10.4 kHz
  752 + Write( REG_LR_TEST2F, 0x44 );
  753 + SetChannel(this->settings.Channel + 10.42e3 );
  754 + break;
  755 + case 2: // 15.6 kHz
  756 + Write( REG_LR_TEST2F, 0x44 );
  757 + SetChannel(this->settings.Channel + 15.62e3 );
  758 + break;
  759 + case 3: // 20.8 kHz
  760 + Write( REG_LR_TEST2F, 0x44 );
  761 + SetChannel(this->settings.Channel + 20.83e3 );
  762 + break;
  763 + case 4: // 31.2 kHz
  764 + Write( REG_LR_TEST2F, 0x44 );
  765 + SetChannel(this->settings.Channel + 31.25e3 );
  766 + break;
  767 + case 5: // 41.4 kHz
  768 + Write( REG_LR_TEST2F, 0x44 );
  769 + SetChannel(this->settings.Channel + 41.67e3 );
  770 + break;
  771 + case 6: // 62.5 kHz
  772 + Write( REG_LR_TEST2F, 0x40 );
  773 + break;
  774 + case 7: // 125 kHz
  775 + Write( REG_LR_TEST2F, 0x40 );
  776 + break;
  777 + case 8: // 250 kHz
  778 + Write( REG_LR_TEST2F, 0x40 );
  779 + break;
  780 + }
  781 + }
  782 + else
  783 + {
  784 + Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) | 0x80 );
  785 + }
  786 +
  787 + rxContinuous = this->settings.LoRa.RxContinuous;
  788 +
  789 + if( this->settings.LoRa.FreqHopOn == true )
  790 + {
  791 + Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
  792 + //RFLR_IRQFLAGS_RXDONE |
  793 + //RFLR_IRQFLAGS_PAYLOADCRCERROR |
  794 + RFLR_IRQFLAGS_VALIDHEADER |
  795 + RFLR_IRQFLAGS_TXDONE |
  796 + RFLR_IRQFLAGS_CADDONE |
  797 + //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
  798 + RFLR_IRQFLAGS_CADDETECTED );
  799 +
  800 + // DIO0=RxDone, DIO2=FhssChangeChannel
  801 + Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
  802 + }
  803 + else
  804 + {
  805 + Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
  806 + //RFLR_IRQFLAGS_RXDONE |
  807 + //RFLR_IRQFLAGS_PAYLOADCRCERROR |
  808 + RFLR_IRQFLAGS_VALIDHEADER |
  809 + RFLR_IRQFLAGS_TXDONE |
  810 + RFLR_IRQFLAGS_CADDONE |
  811 + RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
  812 + RFLR_IRQFLAGS_CADDETECTED );
  813 +
  814 + // DIO0=RxDone
  815 + Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
  816 + }
  817 + Write( REG_LR_FIFORXBASEADDR, 0 );
  818 + Write( REG_LR_FIFOADDRPTR, 0 );
  819 + }
  820 + break;
  821 + }
  822 +
  823 + memset( rxtxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
  824 +
  825 + this->settings.State = RF_RX_RUNNING;
  826 + if( timeout != 0 )
  827 + {
  828 + rxTimeoutTimer.attach_us( mbed::callback( this, &SX1276::OnTimeoutIrq ), timeout * 1e3 );
  829 + }
  830 +
  831 + if( this->settings.Modem == MODEM_FSK )
  832 + {
  833 + SetOpMode( RF_OPMODE_RECEIVER );
  834 +
  835 + if( rxContinuous == false )
  836 + {
  837 + rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1276::OnTimeoutIrq ),
  838 + this->settings.Fsk.RxSingleTimeout * 1e3 );
  839 + }
  840 + }
  841 + else
  842 + {
  843 + if( rxContinuous == true )
  844 + {
  845 + SetOpMode( RFLR_OPMODE_RECEIVER );
  846 + }
  847 + else
  848 + {
  849 + SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
  850 + }
  851 + }
  852 +}
  853 +
  854 +void SX1276::Tx( uint32_t timeout )
  855 +{
  856 +
  857 + switch( this->settings.Modem )
  858 + {
  859 + case MODEM_FSK:
  860 + {
  861 + // DIO0=PacketSent
  862 + // DIO1=FifoEmpty
  863 + // DIO2=FifoFull
  864 + // DIO3=FifoEmpty
  865 + // DIO4=LowBat
  866 + // DIO5=ModeReady
  867 + Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
  868 + RF_DIOMAPPING1_DIO1_MASK &
  869 + RF_DIOMAPPING1_DIO2_MASK ) |
  870 + RF_DIOMAPPING1_DIO1_01 );
  871 +
  872 + Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
  873 + RF_DIOMAPPING2_MAP_MASK ) );
  874 + this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
  875 + }
  876 + break;
  877 + case MODEM_LORA:
  878 + {
  879 + if( this->settings.LoRa.FreqHopOn == true )
  880 + {
  881 + Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
  882 + RFLR_IRQFLAGS_RXDONE |
  883 + RFLR_IRQFLAGS_PAYLOADCRCERROR |
  884 + RFLR_IRQFLAGS_VALIDHEADER |
  885 + //RFLR_IRQFLAGS_TXDONE |
  886 + RFLR_IRQFLAGS_CADDONE |
  887 + //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
  888 + RFLR_IRQFLAGS_CADDETECTED );
  889 +
  890 + // DIO0=TxDone, DIO2=FhssChangeChannel
  891 + Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
  892 + }
  893 + else
  894 + {
  895 + Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
  896 + RFLR_IRQFLAGS_RXDONE |
  897 + RFLR_IRQFLAGS_PAYLOADCRCERROR |
  898 + RFLR_IRQFLAGS_VALIDHEADER |
  899 + //RFLR_IRQFLAGS_TXDONE |
  900 + RFLR_IRQFLAGS_CADDONE |
  901 + RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
  902 + RFLR_IRQFLAGS_CADDETECTED );
  903 +
  904 + // DIO0=TxDone
  905 + Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
  906 + }
  907 + }
  908 + break;
  909 + }
  910 +
  911 + this->settings.State = RF_TX_RUNNING;
  912 + txTimeoutTimer.attach_us( mbed::callback( this, &SX1276::OnTimeoutIrq ), timeout * 1e3 );
  913 + SetOpMode( RF_OPMODE_TRANSMITTER );
  914 +}
  915 +
  916 +void SX1276::StartCad( void )
  917 +{
  918 + switch( this->settings.Modem )
  919 + {
  920 + case MODEM_FSK:
  921 + {
  922 +
  923 + }
  924 + break;
  925 + case MODEM_LORA:
  926 + {
  927 + Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
  928 + RFLR_IRQFLAGS_RXDONE |
  929 + RFLR_IRQFLAGS_PAYLOADCRCERROR |
  930 + RFLR_IRQFLAGS_VALIDHEADER |
  931 + RFLR_IRQFLAGS_TXDONE |
  932 + //RFLR_IRQFLAGS_CADDONE |
  933 + RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
  934 + //RFLR_IRQFLAGS_CADDETECTED
  935 + );
  936 +
  937 + // DIO3=CADDone
  938 + Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO3_MASK ) | RFLR_DIOMAPPING1_DIO3_00 );
  939 +
  940 + this->settings.State = RF_CAD;
  941 + SetOpMode( RFLR_OPMODE_CAD );
  942 + }
  943 + break;
  944 + default:
  945 + break;
  946 + }
  947 +}
  948 +
  949 +void SX1276::SetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time )
  950 +{
  951 + uint32_t timeout = ( uint32_t )( time * 1e6 );
  952 +
  953 + SetChannel( freq );
  954 +
  955 + SetTxConfig( MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, timeout );
  956 +
  957 + Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) & RF_PACKETCONFIG2_DATAMODE_MASK ) );
  958 + // Disable radio interrupts
  959 + Write( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 );
  960 + Write( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 );
  961 +
  962 + this->settings.State = RF_TX_RUNNING;
  963 + txTimeoutTimer.attach_us( mbed::callback( this, &SX1276::OnTimeoutIrq ), timeout );
  964 + SetOpMode( RF_OPMODE_TRANSMITTER );
  965 +}
  966 +
  967 +int16_t SX1276::GetRssi( RadioModems_t modem )
  968 +{
  969 + int16_t rssi = 0;
  970 +
  971 + switch( modem )
  972 + {
  973 + case MODEM_FSK:
  974 + rssi = -( Read( REG_RSSIVALUE ) >> 1 );
  975 + break;
  976 + case MODEM_LORA:
  977 + if( this->settings.Channel > RF_MID_BAND_THRESH )
  978 + {
  979 + rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
  980 + }
  981 + else
  982 + {
  983 + rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
  984 + }
  985 + break;
  986 + default:
  987 + rssi = -1;
  988 + break;
  989 + }
  990 + return rssi;
  991 +}
  992 +
  993 +void SX1276::SetOpMode( uint8_t opMode )
  994 +{
  995 + if( opMode == RF_OPMODE_SLEEP )
  996 + {
  997 + SetAntSwLowPower( true );
  998 + }
  999 + else
  1000 + {
  1001 + SetAntSwLowPower( false );
  1002 + SetAntSw( opMode );
  1003 + }
  1004 + Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
  1005 +}
  1006 +
  1007 +void SX1276::SetModem( RadioModems_t modem )
  1008 +{
  1009 + if( ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_ON ) != 0 )
  1010 + {
  1011 + this->settings.Modem = MODEM_LORA;
  1012 + }
  1013 + else
  1014 + {
  1015 + this->settings.Modem = MODEM_FSK;
  1016 + }
  1017 +
  1018 + if( this->settings.Modem == modem )
  1019 + {
  1020 + return;
  1021 + }
  1022 +
  1023 + this->settings.Modem = modem;
  1024 + switch( this->settings.Modem )
  1025 + {
  1026 + default:
  1027 + case MODEM_FSK:
  1028 + Sleep( );
  1029 + Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
  1030 +
  1031 + Write( REG_DIOMAPPING1, 0x00 );
  1032 + Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
  1033 + break;
  1034 + case MODEM_LORA:
  1035 + Sleep( );
  1036 + Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
  1037 +
  1038 + Write( REG_DIOMAPPING1, 0x00 );
  1039 + Write( REG_DIOMAPPING2, 0x00 );
  1040 + break;
  1041 + }
  1042 +}
  1043 +
  1044 +void SX1276::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
  1045 +{
  1046 + this->SetModem( modem );
  1047 +
  1048 + switch( modem )
  1049 + {
  1050 + case MODEM_FSK:
  1051 + if( this->settings.Fsk.FixLen == false )
  1052 + {
  1053 + this->Write( REG_PAYLOADLENGTH, max );
  1054 + }
  1055 + break;
  1056 + case MODEM_LORA:
  1057 + this->Write( REG_LR_PAYLOADMAXLENGTH, max );
  1058 + break;
  1059 + }
  1060 +}
  1061 +
  1062 +void SX1276::SetPublicNetwork( bool enable )
  1063 +{
  1064 + SetModem( MODEM_LORA );
  1065 + this->settings.LoRa.PublicNetwork = enable;
  1066 + if( enable == true )
  1067 + {
  1068 + // Change LoRa modem SyncWord
  1069 + Write( REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD );
  1070 + }
  1071 + else
  1072 + {
  1073 + // Change LoRa modem SyncWord
  1074 + Write( REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD );
  1075 + }
  1076 +}
  1077 +
  1078 +void SX1276::OnTimeoutIrq( void )
  1079 +{
  1080 + switch( this->settings.State )
  1081 + {
  1082 + case RF_RX_RUNNING:
  1083 + if( this->settings.Modem == MODEM_FSK )
  1084 + {
  1085 + this->settings.FskPacketHandler.PreambleDetected = false;
  1086 + this->settings.FskPacketHandler.SyncWordDetected = false;
  1087 + this->settings.FskPacketHandler.NbBytes = 0;
  1088 + this->settings.FskPacketHandler.Size = 0;
  1089 +
  1090 + // Clear Irqs
  1091 + Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
  1092 + RF_IRQFLAGS1_PREAMBLEDETECT |
  1093 + RF_IRQFLAGS1_SYNCADDRESSMATCH );
  1094 + Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
  1095 +
  1096 + if( this->settings.Fsk.RxContinuous == true )
  1097 + {
  1098 + // Continuous mode restart Rx chain
  1099 + Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
  1100 + rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1276::OnTimeoutIrq ),
  1101 + this->settings.Fsk.RxSingleTimeout * 1e3 );
  1102 + }
  1103 + else
  1104 + {
  1105 + this->settings.State = RF_IDLE;
  1106 + rxTimeoutSyncWord.detach( );
  1107 + }
  1108 + }
  1109 + if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
  1110 + {
  1111 + this->RadioEvents->RxTimeout( );
  1112 + }
  1113 + break;
  1114 + case RF_TX_RUNNING:
  1115 + // Tx timeout shouldn't happen.
  1116 + // But it has been observed that when it happens it is a result of a corrupted SPI transfer
  1117 + // it depends on the platform design.
  1118 + //
  1119 + // The workaround is to put the radio in a known state. Thus, we re-initialize it.
  1120 +
  1121 + // BEGIN WORKAROUND
  1122 +
  1123 + // Reset the radio
  1124 + Reset( );
  1125 +
  1126 + // Calibrate Rx chain
  1127 + RxChainCalibration( );
  1128 +
  1129 + // Initialize radio default values
  1130 + SetOpMode( RF_OPMODE_SLEEP );
  1131 +
  1132 + RadioRegistersInit( );
  1133 +
  1134 + SetModem( MODEM_FSK );
  1135 +
  1136 + // Restore previous network type setting.
  1137 + SetPublicNetwork( this->settings.LoRa.PublicNetwork );
  1138 + // END WORKAROUND
  1139 +
  1140 + this->settings.State = RF_IDLE;
  1141 + if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
  1142 + {
  1143 + this->RadioEvents->TxTimeout( );
  1144 + }
  1145 + break;
  1146 + default:
  1147 + break;
  1148 + }
  1149 +}
  1150 +
  1151 +void SX1276::OnDio0Irq( void )
  1152 +{
  1153 + volatile uint8_t irqFlags = 0;
  1154 +
  1155 + switch( this->settings.State )
  1156 + {
  1157 + case RF_RX_RUNNING:
  1158 + //TimerStop( &RxTimeoutTimer );
  1159 + // RxDone interrupt
  1160 + switch( this->settings.Modem )
  1161 + {
  1162 + case MODEM_FSK:
  1163 + if( this->settings.Fsk.CrcOn == true )
  1164 + {
  1165 + irqFlags = Read( REG_IRQFLAGS2 );
  1166 + if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
  1167 + {
  1168 + // Clear Irqs
  1169 + Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
  1170 + RF_IRQFLAGS1_PREAMBLEDETECT |
  1171 + RF_IRQFLAGS1_SYNCADDRESSMATCH );
  1172 + Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
  1173 +
  1174 + rxTimeoutTimer.detach( );
  1175 +
  1176 + if( this->settings.Fsk.RxContinuous == false )
  1177 + {
  1178 + rxTimeoutSyncWord.detach( );
  1179 + this->settings.State = RF_IDLE;
  1180 + }
  1181 + else
  1182 + {
  1183 + // Continuous mode restart Rx chain
  1184 + Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
  1185 + rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1276::OnTimeoutIrq ),
  1186 + this->settings.Fsk.RxSingleTimeout * 1e3 );
  1187 + }
  1188 +
  1189 + if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
  1190 + {
  1191 + this->RadioEvents->RxError( );
  1192 + }
  1193 + this->settings.FskPacketHandler.PreambleDetected = false;
  1194 + this->settings.FskPacketHandler.SyncWordDetected = false;
  1195 + this->settings.FskPacketHandler.NbBytes = 0;
  1196 + this->settings.FskPacketHandler.Size = 0;
  1197 + break;
  1198 + }
  1199 + }
  1200 +
  1201 + // Read received packet size
  1202 + if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
  1203 + {
  1204 + if( this->settings.Fsk.FixLen == false )
  1205 + {
  1206 + ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
  1207 + }
  1208 + else
  1209 + {
  1210 + this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
  1211 + }
  1212 + ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
  1213 + this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
  1214 + }
  1215 + else
  1216 + {
  1217 + ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
  1218 + this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
  1219 + }
  1220 +
  1221 + rxTimeoutTimer.detach( );
  1222 +
  1223 + if( this->settings.Fsk.RxContinuous == false )
  1224 + {
  1225 + this->settings.State = RF_IDLE;
  1226 + rxTimeoutSyncWord.detach( );
  1227 + }
  1228 + else
  1229 + {
  1230 + // Continuous mode restart Rx chain
  1231 + Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
  1232 + rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1276::OnTimeoutIrq ),
  1233 + this->settings.Fsk.RxSingleTimeout * 1e3 );
  1234 + }
  1235 +
  1236 + if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
  1237 + {
  1238 + this->RadioEvents->RxDone( rxtxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
  1239 + }
  1240 + this->settings.FskPacketHandler.PreambleDetected = false;
  1241 + this->settings.FskPacketHandler.SyncWordDetected = false;
  1242 + this->settings.FskPacketHandler.NbBytes = 0;
  1243 + this->settings.FskPacketHandler.Size = 0;
  1244 + break;
  1245 + case MODEM_LORA:
  1246 + {
  1247 + int8_t snr = 0;
  1248 +
  1249 + // Clear Irq
  1250 + Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
  1251 +
  1252 + irqFlags = Read( REG_LR_IRQFLAGS );
  1253 + if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
  1254 + {
  1255 + // Clear Irq
  1256 + Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
  1257 +
  1258 + if( this->settings.LoRa.RxContinuous == false )
  1259 + {
  1260 + this->settings.State = RF_IDLE;
  1261 + }
  1262 + rxTimeoutTimer.detach( );
  1263 +
  1264 + if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
  1265 + {
  1266 + this->RadioEvents->RxError( );
  1267 + }
  1268 + break;
  1269 + }
  1270 +
  1271 + this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
  1272 + if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
  1273 + {
  1274 + // Invert and divide by 4
  1275 + snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
  1276 + snr = -snr;
  1277 + }
  1278 + else
  1279 + {
  1280 + // Divide by 4
  1281 + snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
  1282 + }
  1283 +
  1284 + int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
  1285 + if( snr < 0 )
  1286 + {
  1287 + if( this->settings.Channel > RF_MID_BAND_THRESH )
  1288 + {
  1289 + this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
  1290 + snr;
  1291 + }
  1292 + else
  1293 + {
  1294 + this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
  1295 + snr;
  1296 + }
  1297 + }
  1298 + else
  1299 + {
  1300 + if( this->settings.Channel > RF_MID_BAND_THRESH )
  1301 + {
  1302 + this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
  1303 + }
  1304 + else
  1305 + {
  1306 + this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
  1307 + }
  1308 + }
  1309 +
  1310 + this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
  1311 + ReadFifo( rxtxBuffer, this->settings.LoRaPacketHandler.Size );
  1312 +
  1313 + if( this->settings.LoRa.RxContinuous == false )
  1314 + {
  1315 + this->settings.State = RF_IDLE;
  1316 + }
  1317 + rxTimeoutTimer.detach( );
  1318 +
  1319 + if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
  1320 + {
  1321 + this->RadioEvents->RxDone( rxtxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
  1322 + }
  1323 + }
  1324 + break;
  1325 + default:
  1326 + break;
  1327 + }
  1328 + break;
  1329 + case RF_TX_RUNNING:
  1330 + txTimeoutTimer.detach( );
  1331 + // TxDone interrupt
  1332 + switch( this->settings.Modem )
  1333 + {
  1334 + case MODEM_LORA:
  1335 + // Clear Irq
  1336 + Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
  1337 + // Intentional fall through
  1338 + case MODEM_FSK:
  1339 + default:
  1340 + this->settings.State = RF_IDLE;
  1341 + if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
  1342 + {
  1343 + this->RadioEvents->TxDone( );
  1344 + }
  1345 + break;
  1346 + }
  1347 + break;
  1348 + default:
  1349 + break;
  1350 + }
  1351 +}
  1352 +
  1353 +void SX1276::OnDio1Irq( void )
  1354 +{
  1355 + switch( this->settings.State )
  1356 + {
  1357 + case RF_RX_RUNNING:
  1358 + switch( this->settings.Modem )
  1359 + {
  1360 + case MODEM_FSK:
  1361 + // FifoLevel interrupt
  1362 + // Read received packet size
  1363 + if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
  1364 + {
  1365 + if( this->settings.Fsk.FixLen == false )
  1366 + {
  1367 + ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
  1368 + }
  1369 + else
  1370 + {
  1371 + this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
  1372 + }
  1373 + }
  1374 +
  1375 + if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
  1376 + {
  1377 + ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
  1378 + this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
  1379 + }
  1380 + else
  1381 + {
  1382 + ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
  1383 + this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
  1384 + }
  1385 + break;
  1386 + case MODEM_LORA:
  1387 + // Sync time out
  1388 + rxTimeoutTimer.detach( );
  1389 + // Clear Irq
  1390 + Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT );
  1391 +
  1392 + this->settings.State = RF_IDLE;
  1393 + if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
  1394 + {
  1395 + this->RadioEvents->RxTimeout( );
  1396 + }
  1397 + break;
  1398 + default:
  1399 + break;
  1400 + }
  1401 + break;
  1402 + case RF_TX_RUNNING:
  1403 + switch( this->settings.Modem )
  1404 + {
  1405 + case MODEM_FSK:
  1406 + // FifoEmpty interrupt
  1407 + if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
  1408 + {
  1409 + WriteFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
  1410 + this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
  1411 + }
  1412 + else
  1413 + {
  1414 + // Write the last chunk of data
  1415 + WriteFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
  1416 + this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
  1417 + }
  1418 + break;
  1419 + case MODEM_LORA:
  1420 + break;
  1421 + default:
  1422 + break;
  1423 + }
  1424 + break;
  1425 + default:
  1426 + break;
  1427 + }
  1428 +}
  1429 +
  1430 +void SX1276::OnDio2Irq( void )
  1431 +{
  1432 + switch( this->settings.State )
  1433 + {
  1434 + case RF_RX_RUNNING:
  1435 + switch( this->settings.Modem )
  1436 + {
  1437 + case MODEM_FSK:
  1438 + // Checks if DIO4 is connected. If it is not PreambleDtected is set to true.
  1439 + if( this->dioIrq[4] == NULL )
  1440 + {
  1441 + this->settings.FskPacketHandler.PreambleDetected = true;
  1442 + }
  1443 +
  1444 + if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
  1445 + {
  1446 + rxTimeoutSyncWord.detach( );
  1447 +
  1448 + this->settings.FskPacketHandler.SyncWordDetected = true;
  1449 +
  1450 + this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
  1451 +
  1452 + this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
  1453 + ( uint16_t )Read( REG_AFCLSB ) ) *
  1454 + ( double )FREQ_STEP;
  1455 + this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
  1456 + }
  1457 + break;
  1458 + case MODEM_LORA:
  1459 + if( this->settings.LoRa.FreqHopOn == true )
  1460 + {
  1461 + // Clear Irq
  1462 + Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
  1463 +
  1464 + if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
  1465 + {
  1466 + this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
  1467 + }
  1468 + }
  1469 + break;
  1470 + default:
  1471 + break;
  1472 + }
  1473 + break;
  1474 + case RF_TX_RUNNING:
  1475 + switch( this->settings.Modem )
  1476 + {
  1477 + case MODEM_FSK:
  1478 + break;
  1479 + case MODEM_LORA:
  1480 + if( this->settings.LoRa.FreqHopOn == true )
  1481 + {
  1482 + // Clear Irq
  1483 + Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
  1484 +
  1485 + if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
  1486 + {
  1487 + this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
  1488 + }
  1489 + }
  1490 + break;
  1491 + default:
  1492 + break;
  1493 + }
  1494 + break;
  1495 + default:
  1496 + break;
  1497 + }
  1498 +}
  1499 +
  1500 +void SX1276::OnDio3Irq( void )
  1501 +{
  1502 + switch( this->settings.Modem )
  1503 + {
  1504 + case MODEM_FSK:
  1505 + break;
  1506 + case MODEM_LORA:
  1507 + if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
  1508 + {
  1509 + // Clear Irq
  1510 + Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
  1511 + if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
  1512 + {
  1513 + this->RadioEvents->CadDone( true );
  1514 + }
  1515 + }
  1516 + else
  1517 + {
  1518 + // Clear Irq
  1519 + Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
  1520 + if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
  1521 + {
  1522 + this->RadioEvents->CadDone( false );
  1523 + }
  1524 + }
  1525 + break;
  1526 + default:
  1527 + break;
  1528 + }
  1529 +}
  1530 +
  1531 +void SX1276::OnDio4Irq( void )
  1532 +{
  1533 + switch( this->settings.Modem )
  1534 + {
  1535 + case MODEM_FSK:
  1536 + {
  1537 + if( this->settings.FskPacketHandler.PreambleDetected == false )
  1538 + {
  1539 + this->settings.FskPacketHandler.PreambleDetected = true;
  1540 + }
  1541 + }
  1542 + break;
  1543 + case MODEM_LORA:
  1544 + break;
  1545 + default:
  1546 + break;
  1547 + }
  1548 +}
  1549 +
  1550 +void SX1276::OnDio5Irq( void )
  1551 +{
  1552 + switch( this->settings.Modem )
  1553 + {
  1554 + case MODEM_FSK:
  1555 + break;
  1556 + case MODEM_LORA:
  1557 + break;
  1558 + default:
  1559 + break;
  1560 + }
  1561 +}
... ...
emetteur/SX1276Lib/sx1276/sx1276.h 0 → 100644
  Show/Hide comments   View file @64abd45
... ... @@ -0,0 +1,506 @@
  1 +/*
  2 + / _____) _ | |
  3 +( (____ _____ ____ _| |_ _____ ____| |__
  4 + \____ \| ___ | (_ _) ___ |/ ___) _ \
  5 + _____) ) ____| | | || |_| ____( (___| | | |
  6 +(______/|_____)_|_|_| \__)_____)\____)_| |_|
  7 + (C) 2014 Semtech
  8 +
  9 +Description: Actual implementation of a SX1276 radio, inherits Radio
  10 +
  11 +License: Revised BSD License, see LICENSE.TXT file include in the project
  12 +
  13 +Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
  14 +*/
  15 +#ifndef __SX1276_H__
  16 +#define __SX1276_H__
  17 +
  18 +#include "radio.h"
  19 +#include "./registers/sx1276Regs-Fsk.h"
  20 +#include "./registers/sx1276Regs-LoRa.h"
  21 +#include "./typedefs/typedefs.h"
  22 +
  23 +/*!
  24 + * Radio wake-up time from sleep
  25 + */
  26 +#define RADIO_WAKEUP_TIME 1 // [ms]
  27 +
  28 +/*!
  29 + * Sync word for Private LoRa networks
  30 + */
  31 +#define LORA_MAC_PRIVATE_SYNCWORD 0x12
  32 +
  33 +/*!
  34 + * Sync word for Public LoRa networks
  35 + */
  36 +#define LORA_MAC_PUBLIC_SYNCWORD 0x34
  37 +
  38 +
  39 +/*!
  40 + * SX1276 definitions
  41 + */
  42 +#define XTAL_FREQ 32000000
  43 +#define FREQ_STEP 61.03515625
  44 +
  45 +#define RX_BUFFER_SIZE 256
  46 +
  47 +/*!
  48 + * Constant values need to compute the RSSI value
  49 + */
  50 +#define RSSI_OFFSET_LF -164.0
  51 +#define RSSI_OFFSET_HF -157.0
  52 +
  53 +#define RF_MID_BAND_THRESH 525000000
  54 +
  55 +/*!
  56 + * Actual implementation of a SX1276 radio, inherits Radio
  57 + */
  58 +class SX1276 : public Radio
  59 +{
  60 +protected:
  61 + /*!
  62 + * SPI Interface
  63 + */
  64 + SPI spi; // mosi, miso, sclk
  65 + DigitalOut nss;
  66 +
  67 + /*!
  68 + * SX1276 Reset pin
  69 + */
  70 + DigitalInOut reset;
  71 +
  72 + /*!
  73 + * SX1276 DIO pins
  74 + */
  75 + InterruptIn dio0;
  76 + InterruptIn dio1;
  77 + InterruptIn dio2;
  78 + InterruptIn dio3;
  79 + InterruptIn dio4;
  80 + DigitalIn dio5;
  81 +
  82 + bool isRadioActive;
  83 +
  84 + uint8_t boardConnected; //1 = SX1276MB1LAS; 0 = SX1276MB1MAS
  85 +
  86 + uint8_t *rxtxBuffer;
  87 +
  88 + /*!
  89 + * Hardware DIO IRQ functions
  90 + */
  91 + DioIrqHandler *dioIrq;
  92 +
  93 + /*!
  94 + * Tx and Rx timers
  95 + */
  96 + Timeout txTimeoutTimer;
  97 + Timeout rxTimeoutTimer;
  98 + Timeout rxTimeoutSyncWord;
  99 +
  100 + RadioSettings_t settings;
  101 +
  102 + static const FskBandwidth_t FskBandwidths[];
  103 +protected:
  104 +
  105 + /*!
  106 + * Performs the Rx chain calibration for LF and HF bands
  107 + * \remark Must be called just after the reset so all registers are at their
  108 + * default values
  109 + */
  110 + void RxChainCalibration( void );
  111 +
  112 +public:
  113 + SX1276( RadioEvents_t *events,
  114 + PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
  115 + PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 );
  116 + SX1276( RadioEvents_t *events );
  117 + virtual ~SX1276( );
  118 +
  119 + //-------------------------------------------------------------------------
  120 + // Redefined Radio functions
  121 + //-------------------------------------------------------------------------
  122 + /*!
  123 + * @brief Initializes the radio
  124 + *
  125 + * @param [IN] events Structure containing the driver callback functions
  126 + */
  127 + virtual void Init( RadioEvents_t *events );
  128 + /*!
  129 + * Return current radio status
  130 + *
  131 + * @param status Radio status. [RF_IDLE, RX_RUNNING, TX_RUNNING]
  132 + */
  133 + virtual RadioState GetStatus( void );
  134 + /*!
  135 + * @brief Configures the SX1276 with the given modem
  136 + *
  137 + * @param [IN] modem Modem to be used [0: FSK, 1: LoRa]
  138 + */
  139 + virtual void SetModem( RadioModems_t modem );
  140 + /*!
  141 + * @brief Sets the channel frequency
  142 + *
  143 + * @param [IN] freq Channel RF frequency
  144 + */
  145 + virtual void SetChannel( uint32_t freq );
  146 + /*!
  147 + * @brief Sets the channels configuration
  148 + *
  149 + * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
  150 + * @param [IN] freq Channel RF frequency
  151 + * @param [IN] rssiThresh RSSI threshold
  152 + *
  153 + * @retval isFree [true: Channel is free, false: Channel is not free]
  154 + */
  155 + virtual bool IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh );
  156 + /*!
  157 + * @brief Generates a 32 bits random value based on the RSSI readings
  158 + *
  159 + * \remark This function sets the radio in LoRa modem mode and disables
  160 + * all interrupts.
  161 + * After calling this function either Radio.SetRxConfig or
  162 + * Radio.SetTxConfig functions must be called.
  163 + *
  164 + * @retval randomValue 32 bits random value
  165 + */
  166 + virtual uint32_t Random( void );
  167 + /*!
  168 + * @brief Sets the reception parameters
  169 + *
  170 + * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
  171 + * @param [IN] bandwidth Sets the bandwidth
  172 + * FSK : >= 2600 and <= 250000 Hz
  173 + * LoRa: [0: 125 kHz, 1: 250 kHz,
  174 + * 2: 500 kHz, 3: Reserved]
  175 + * @param [IN] datarate Sets the Datarate
  176 + * FSK : 600..300000 bits/s
  177 + * LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
  178 + * 10: 1024, 11: 2048, 12: 4096 chips]
  179 + * @param [IN] coderate Sets the coding rate ( LoRa only )
  180 + * FSK : N/A ( set to 0 )
  181 + * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
  182 + * @param [IN] bandwidthAfc Sets the AFC Bandwidth ( FSK only )
  183 + * FSK : >= 2600 and <= 250000 Hz
  184 + * LoRa: N/A ( set to 0 )
  185 + * @param [IN] preambleLen Sets the Preamble length ( LoRa only )
  186 + * FSK : N/A ( set to 0 )
  187 + * LoRa: Length in symbols ( the hardware adds 4 more symbols )
  188 + * @param [IN] symbTimeout Sets the RxSingle timeout value
  189 + * FSK : timeout number of bytes
  190 + * LoRa: timeout in symbols
  191 + * @param [IN] fixLen Fixed length packets [0: variable, 1: fixed]
  192 + * @param [IN] payloadLen Sets payload length when fixed lenght is used
  193 + * @param [IN] crcOn Enables/Disables the CRC [0: OFF, 1: ON]
  194 + * @param [IN] freqHopOn Enables disables the intra-packet frequency hopping [0: OFF, 1: ON] (LoRa only)
  195 + * @param [IN] hopPeriod Number of symbols bewteen each hop (LoRa only)
  196 + * @param [IN] iqInverted Inverts IQ signals ( LoRa only )
  197 + * FSK : N/A ( set to 0 )
  198 + * LoRa: [0: not inverted, 1: inverted]
  199 + * @param [IN] rxContinuous Sets the reception in continuous mode
  200 + * [false: single mode, true: continuous mode]
  201 + */
  202 + virtual void SetRxConfig ( RadioModems_t modem, uint32_t bandwidth,
  203 + uint32_t datarate, uint8_t coderate,
  204 + uint32_t bandwidthAfc, uint16_t preambleLen,
  205 + uint16_t symbTimeout, bool fixLen,
  206 + uint8_t payloadLen,
  207 + bool crcOn, bool freqHopOn, uint8_t hopPeriod,
  208 + bool iqInverted, bool rxContinuous );
  209 + /*!
  210 + * @brief Sets the transmission parameters
  211 + *
  212 + * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
  213 + * @param [IN] power Sets the output power [dBm]
  214 + * @param [IN] fdev Sets the frequency deviation ( FSK only )
  215 + * FSK : [Hz]
  216 + * LoRa: 0
  217 + * @param [IN] bandwidth Sets the bandwidth ( LoRa only )
  218 + * FSK : 0
  219 + * LoRa: [0: 125 kHz, 1: 250 kHz,
  220 + * 2: 500 kHz, 3: Reserved]
  221 + * @param [IN] datarate Sets the Datarate
  222 + * FSK : 600..300000 bits/s
  223 + * LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
  224 + * 10: 1024, 11: 2048, 12: 4096 chips]
  225 + * @param [IN] coderate Sets the coding rate ( LoRa only )
  226 + * FSK : N/A ( set to 0 )
  227 + * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
  228 + * @param [IN] preambleLen Sets the preamble length
  229 + * @param [IN] fixLen Fixed length packets [0: variable, 1: fixed]
  230 + * @param [IN] crcOn Enables disables the CRC [0: OFF, 1: ON]
  231 + * @param [IN] freqHopOn Enables disables the intra-packet frequency hopping [0: OFF, 1: ON] (LoRa only)
  232 + * @param [IN] hopPeriod Number of symbols bewteen each hop (LoRa only)
  233 + * @param [IN] iqInverted Inverts IQ signals ( LoRa only )
  234 + * FSK : N/A ( set to 0 )
  235 + * LoRa: [0: not inverted, 1: inverted]
  236 + * @param [IN] timeout Transmission timeout [ms]
  237 + */
  238 + virtual void SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
  239 + uint32_t bandwidth, uint32_t datarate,
  240 + uint8_t coderate, uint16_t preambleLen,
  241 + bool fixLen, bool crcOn, bool freqHopOn,
  242 + uint8_t hopPeriod, bool iqInverted, uint32_t timeout );
  243 + /*!
  244 + * @brief Checks if the given RF frequency is supported by the hardware
  245 + *
  246 + * @param [IN] frequency RF frequency to be checked
  247 + * @retval isSupported [true: supported, false: unsupported]
  248 + */
  249 + virtual bool CheckRfFrequency( uint32_t frequency ) = 0;
  250 + /*!
  251 + * @brief Computes the packet time on air for the given payload
  252 + *
  253 + * \Remark Can only be called once SetRxConfig or SetTxConfig have been called
  254 + *
  255 + * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
  256 + * @param [IN] pktLen Packet payload length
  257 + *
  258 + * @retval airTime Computed airTime for the given packet payload length
  259 + */
  260 + virtual uint32_t TimeOnAir ( RadioModems_t modem, uint8_t pktLen );
  261 + /*!
  262 + * @brief Sends the buffer of size. Prepares the packet to be sent and sets
  263 + * the radio in transmission
  264 + *
  265 + * @param [IN]: buffer Buffer pointer
  266 + * @param [IN]: size Buffer size
  267 + */
  268 + virtual void Send( uint8_t *buffer, uint8_t size );
  269 + /*!
  270 + * @brief Sets the radio in sleep mode
  271 + */
  272 + virtual void Sleep( void );
  273 + /*!
  274 + * @brief Sets the radio in standby mode
  275 + */
  276 + virtual void Standby( void );
  277 + /*!
  278 + * @brief Sets the radio in CAD mode
  279 + */
  280 + virtual void StartCad( void );
  281 + /*!
  282 + * @brief Sets the radio in reception mode for the given time
  283 + * @param [IN] timeout Reception timeout [ms]
  284 + * [0: continuous, others timeout]
  285 + */
  286 + virtual void Rx( uint32_t timeout );
  287 + /*!
  288 + * @brief Sets the radio in transmission mode for the given time
  289 + * @param [IN] timeout Transmission timeout [ms]
  290 + * [0: continuous, others timeout]
  291 + */
  292 + virtual void Tx( uint32_t timeout );
  293 + /*!
  294 + * @brief Sets the radio in continuous wave transmission mode
  295 + *
  296 + * @param [IN]: freq Channel RF frequency
  297 + * @param [IN]: power Sets the output power [dBm]
  298 + * @param [IN]: time Transmission mode timeout [s]
  299 + */
  300 + virtual void SetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time );
  301 + /*!
  302 + * @brief Reads the current RSSI value
  303 + *
  304 + * @retval rssiValue Current RSSI value in [dBm]
  305 + */
  306 + virtual int16_t GetRssi ( RadioModems_t modem );
  307 + /*!
  308 + * @brief Writes the radio register at the specified address
  309 + *
  310 + * @param [IN]: addr Register address
  311 + * @param [IN]: data New register value
  312 + */
  313 + virtual void Write ( uint8_t addr, uint8_t data ) = 0;
  314 + /*!
  315 + * @brief Reads the radio register at the specified address
  316 + *
  317 + * @param [IN]: addr Register address
  318 + * @retval data Register value
  319 + */
  320 + virtual uint8_t Read ( uint8_t addr ) = 0;
  321 + /*!
  322 + * @brief Writes multiple radio registers starting at address
  323 + *
  324 + * @param [IN] addr First Radio register address
  325 + * @param [IN] buffer Buffer containing the new register's values
  326 + * @param [IN] size Number of registers to be written
  327 + */
  328 + virtual void Write( uint8_t addr, uint8_t *buffer, uint8_t size ) = 0;
  329 + /*!
  330 + * @brief Reads multiple radio registers starting at address
  331 + *
  332 + * @param [IN] addr First Radio register address
  333 + * @param [OUT] buffer Buffer where to copy the registers data
  334 + * @param [IN] size Number of registers to be read
  335 + */
  336 + virtual void Read ( uint8_t addr, uint8_t *buffer, uint8_t size ) = 0;
  337 + /*!
  338 + * @brief Writes the buffer contents to the SX1276 FIFO
  339 + *
  340 + * @param [IN] buffer Buffer containing data to be put on the FIFO.
  341 + * @param [IN] size Number of bytes to be written to the FIFO
  342 + */
  343 + virtual void WriteFifo( uint8_t *buffer, uint8_t size ) = 0;
  344 + /*!
  345 + * @brief Reads the contents of the SX1276 FIFO
  346 + *
  347 + * @param [OUT] buffer Buffer where to copy the FIFO read data.
  348 + * @param [IN] size Number of bytes to be read from the FIFO
  349 + */
  350 + virtual void ReadFifo( uint8_t *buffer, uint8_t size ) = 0;
  351 + /*!
  352 + * @brief Resets the SX1276
  353 + */
  354 + virtual void Reset( void ) = 0;
  355 +
  356 + /*!
  357 + * @brief Sets the maximum payload length.
  358 + *
  359 + * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
  360 + * @param [IN] max Maximum payload length in bytes
  361 + */
  362 + virtual void SetMaxPayloadLength( RadioModems_t modem, uint8_t max );
  363 +
  364 + /*!
  365 + * \brief Sets the network to public or private. Updates the sync byte.
  366 + *
  367 + * \remark Applies to LoRa modem only
  368 + *
  369 + * \param [IN] enable if true, it enables a public network
  370 + */
  371 + virtual void SetPublicNetwork( bool enable );
  372 +
  373 + //-------------------------------------------------------------------------
  374 + // Board relative functions
  375 + //-------------------------------------------------------------------------
  376 +
  377 +protected:
  378 + /*!
  379 + * @brief Initializes the radio I/Os pins interface
  380 + */
  381 + virtual void IoInit( void ) = 0;
  382 +
  383 + /*!
  384 + * @brief Initializes the radio registers
  385 + */
  386 + virtual void RadioRegistersInit( ) = 0;
  387 +
  388 + /*!
  389 + * @brief Initializes the radio SPI
  390 + */
  391 + virtual void SpiInit( void ) = 0;
  392 +
  393 + /*!
  394 + * @brief Initializes DIO IRQ handlers
  395 + *
  396 + * @param [IN] irqHandlers Array containing the IRQ callback functions
  397 + */
  398 + virtual void IoIrqInit( DioIrqHandler *irqHandlers ) = 0;
  399 +
  400 + /*!
  401 + * @brief De-initializes the radio I/Os pins interface.
  402 + *
  403 + * \remark Useful when going in MCU lowpower modes
  404 + */
  405 + virtual void IoDeInit( void ) = 0;
  406 +
  407 + /*!
  408 + * @brief Sets the radio output power.
  409 + *
  410 + * @param [IN] power Sets the RF output power
  411 + */
  412 + virtual void SetRfTxPower( int8_t power ) = 0;
  413 +
  414 + /*!
  415 + * @brief Gets the board PA selection configuration
  416 + *
  417 + * @param [IN] channel Channel frequency in Hz
  418 + * @retval PaSelect RegPaConfig PaSelect value
  419 + */
  420 + virtual uint8_t GetPaSelect( uint32_t channel ) = 0;
  421 +
  422 + /*!
  423 + * @brief Set the RF Switch I/Os pins in Low Power mode
  424 + *
  425 + * @param [IN] status enable or disable
  426 + */
  427 + virtual void SetAntSwLowPower( bool status ) = 0;
  428 +
  429 + /*!
  430 + * @brief Initializes the RF Switch I/Os pins interface
  431 + */
  432 + virtual void AntSwInit( void ) = 0;
  433 +
  434 + /*!
  435 + * @brief De-initializes the RF Switch I/Os pins interface
  436 + *
  437 + * \remark Needed to decrease the power consumption in MCU lowpower modes
  438 + */
  439 + virtual void AntSwDeInit( void ) = 0;
  440 +
  441 + /*!
  442 + * @brief Controls the antenna switch if necessary.
  443 + *
  444 + * \remark see errata note
  445 + *
  446 + * @param [IN] opMode Current radio operating mode
  447 + */
  448 + virtual void SetAntSw( uint8_t opMode ) = 0;
  449 +protected:
  450 +
  451 + /*!
  452 + * @brief Sets the SX1276 operating mode
  453 + *
  454 + * @param [IN] opMode New operating mode
  455 + */
  456 + virtual void SetOpMode( uint8_t opMode );
  457 +
  458 + /*
  459 + * SX1276 DIO IRQ callback functions prototype
  460 + */
  461 +
  462 + /*!
  463 + * @brief DIO 0 IRQ callback
  464 + */
  465 + virtual void OnDio0Irq( void );
  466 +
  467 + /*!
  468 + * @brief DIO 1 IRQ callback
  469 + */
  470 + virtual void OnDio1Irq( void );
  471 +
  472 + /*!
  473 + * @brief DIO 2 IRQ callback
  474 + */
  475 + virtual void OnDio2Irq( void );
  476 +
  477 + /*!
  478 + * @brief DIO 3 IRQ callback
  479 + */
  480 + virtual void OnDio3Irq( void );
  481 +
  482 + /*!
  483 + * @brief DIO 4 IRQ callback
  484 + */
  485 + virtual void OnDio4Irq( void );
  486 +
  487 + /*!
  488 + * @brief DIO 5 IRQ callback
  489 + */
  490 + virtual void OnDio5Irq( void );
  491 +
  492 + /*!
  493 + * @brief Tx & Rx timeout timer callback
  494 + */
  495 + virtual void OnTimeoutIrq( void );
  496 +
  497 + /*!
  498 + * Returns the known FSK bandwidth registers value
  499 + *
  500 + * \param [IN] bandwidth Bandwidth value in Hz
  501 + * \retval regValue Bandwidth register value.
  502 + */
  503 + static uint8_t GetFskBandwidthRegValue( uint32_t bandwidth );
  504 +};
  505 +
  506 +#endif // __SX1276_H__
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  1 +/*
  2 + / _____) _ | |
  3 +( (____ _____ ____ _| |_ _____ ____| |__
  4 + \____ \| ___ | (_ _) ___ |/ ___) _ \
  5 + _____) ) ____| | | || |_| ____( (___| | | |
  6 +(______/|_____)_|_|_| \__)_____)\____)_| |_|
  7 + (C) 2014 Semtech
  8 +
  9 +Description: -
  10 +
  11 +License: Revised BSD License, see LICENSE.TXT file include in the project
  12 +
  13 +Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
  14 +*/
  15 +#ifndef __TYPEDEFS_H__
  16 +#define __TYPEDEFS_H__
  17 +
  18 +#include "mbed.h"
  19 +#include "./enums/enums.h"
  20 +
  21 +class SX1276;
  22 +class SX1276MB1xAS;
  23 +/*!
  24 + * Hardware IO IRQ callback function definition
  25 + */
  26 +typedef void ( SX1276::*DioIrqHandler )( void );
  27 +
  28 +/*!
  29 + * triggers definition
  30 + */
  31 +typedef void ( SX1276::*Trigger )( void );
  32 +typedef void ( SX1276MB1xAS::*TriggerMB1xAS )( void );
  33 +
  34 +/*!
  35 + * FSK bandwidth definition
  36 + */
  37 +typedef struct
  38 +{
  39 + uint32_t bandwidth;
  40 + uint8_t RegValue;
  41 +}FskBandwidth_t;
  42 +
  43 +/*!
  44 + * Radio registers definition
  45 + */
  46 +typedef struct
  47 +{
  48 + ModemType Modem;
  49 + uint8_t Addr;
  50 + uint8_t Value;
  51 +}RadioRegisters_t;
  52 +
  53 +#endif //__TYPEDEFS_H__
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  1 +/*
  2 + / _____) _ | |
  3 +( (____ _____ ____ _| |_ _____ ____| |__
  4 + \____ \| ___ | (_ _) ___ |/ ___) _ \
  5 + _____) ) ____| | | || |_| ____( (___| | | |
  6 +(______/|_____)_|_|_| \__)_____)\____)_| |_|
  7 + ( C )2014 Semtech
  8 +
  9 +Description: Contains the callbacks for the IRQs and any application related details
  10 +
  11 +License: Revised BSD License, see LICENSE.TXT file include in the project
  12 +
  13 +Maintainer: Miguel Luis and Gregory Cristian
  14 +*/
  15 +#ifndef __MAIN_H__
  16 +#define __MAIN_H__
  17 +
  18 +
  19 +/*!
  20 + * Frequency hopping frequencies table
  21 + */
  22 +const uint32_t HoppingFrequencies[] =
  23 +{
  24 + 916500000,
  25 + 923500000,
  26 + 906500000,
  27 + 917500000,
  28 + 917500000,
  29 + 909000000,
  30 + 903000000,
  31 + 916000000,
  32 + 912500000,
  33 + 926000000,
  34 + 925000000,
  35 + 909500000,
  36 + 913000000,
  37 + 918500000,
  38 + 918500000,
  39 + 902500000,
  40 + 911500000,
  41 + 926500000,
  42 + 902500000,
  43 + 922000000,
  44 + 924000000,
  45 + 903500000,
  46 + 913000000,
  47 + 922000000,
  48 + 926000000,
  49 + 910000000,
  50 + 920000000,
  51 + 922500000,
  52 + 911000000,
  53 + 922000000,
  54 + 909500000,
  55 + 926000000,
  56 + 922000000,
  57 + 918000000,
  58 + 925500000,
  59 + 908000000,
  60 + 917500000,
  61 + 926500000,
  62 + 908500000,
  63 + 916000000,
  64 + 905500000,
  65 + 916000000,
  66 + 903000000,
  67 + 905000000,
  68 + 915000000,
  69 + 913000000,
  70 + 907000000,
  71 + 910000000,
  72 + 926500000,
  73 + 925500000,
  74 + 911000000
  75 +};
  76 +
  77 +/*
  78 + * Callback functions prototypes
  79 + */
  80 +/*!
  81 + * @brief Function to be executed on Radio Tx Done event
  82 + */
  83 +void OnTxDone( void );
  84 +
  85 +/*!
  86 + * @brief Function to be executed on Radio Rx Done event
  87 + */
  88 +void OnRxDone( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr );
  89 +
  90 +/*!
  91 + * @brief Function executed on Radio Tx Timeout event
  92 + */
  93 +void OnTxTimeout( void );
  94 +
  95 +/*!
  96 + * @brief Function executed on Radio Rx Timeout event
  97 + */
  98 +void OnRxTimeout( void );
  99 +
  100 +/*!
  101 + * @brief Function executed on Radio Rx Error event
  102 + */
  103 +void OnRxError( void );
  104 +
  105 +/*!
  106 + * @brief Function executed on Radio Fhss Change Channel event
  107 + */
  108 +void OnFhssChangeChannel( uint8_t channelIndex );
  109 +
  110 +/*!
  111 + * @brief Function executed on CAD Done event
  112 + */
  113 +void OnCadDone( void );
  114 +
  115 +#endif // __MAIN_H__
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