gpio.c
3.02 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
/*
* Copyright (C) 2015 Jan Wagner <mail@jwagner.eu>
* 2015-2016 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_nrf5x_common
* @{
*
* @file
* @brief Low-level GPIO driver implementation
*
* @note This GPIO driver implementation supports only one pin to be
* defined as external interrupt.
*
* @author Christian Kühling <kuehling@zedat.fu-berlin.de>
* @author Timo Ziegler <timo.ziegler@fu-berlin.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Jan Wagner <mail@jwagner.eu>
*
* @}
*/
#include "cpu.h"
#include "periph/gpio.h"
#include "periph_cpu.h"
#include "periph_conf.h"
/**
* @brief Place to store the interrupt context
*/
static gpio_isr_ctx_t exti_chan;
int gpio_init(gpio_t pin, gpio_mode_t mode)
{
switch (mode) {
case GPIO_IN:
case GPIO_IN_PD:
case GPIO_IN_PU:
case GPIO_OUT:
/* configure pin direction, input buffer and pull resistor state */
GPIO_BASE->PIN_CNF[pin] = mode;
break;
default:
return -1;
}
return 0;
}
int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
gpio_cb_t cb, void *arg)
{
/* disable external interrupt in case one is active */
NRF_GPIOTE->INTENSET &= ~(GPIOTE_INTENSET_IN0_Msk);
/* save callback */
exti_chan.cb = cb;
exti_chan.arg = arg;
/* configure pin as input */
gpio_init(pin, mode);
/* set interrupt priority and enable global GPIOTE interrupt */
NVIC_EnableIRQ(GPIOTE_IRQn);
/* configure the GPIOTE channel: set even mode, pin and active flank */
NRF_GPIOTE->CONFIG[0] = (GPIOTE_CONFIG_MODE_Event |
(pin << GPIOTE_CONFIG_PSEL_Pos) |
(flank << GPIOTE_CONFIG_POLARITY_Pos));
/* enable external interrupt */
NRF_GPIOTE->INTENSET |= GPIOTE_INTENSET_IN0_Msk;
return 0;
}
void gpio_irq_enable(gpio_t pin)
{
(void) pin;
NRF_GPIOTE->INTENSET |= GPIOTE_INTENSET_IN0_Msk;
}
void gpio_irq_disable(gpio_t pin)
{
(void) pin;
NRF_GPIOTE->INTENCLR |= GPIOTE_INTENSET_IN0_Msk;
}
int gpio_read(gpio_t pin)
{
if (GPIO_BASE->DIR & (1 << pin)) {
return (GPIO_BASE->OUT & (1 << pin)) ? 1 : 0;
}
else {
return (GPIO_BASE->IN & (1 << pin)) ? 1 : 0;
}
}
void gpio_set(gpio_t pin)
{
GPIO_BASE->OUTSET = (1 << pin);
}
void gpio_clear(gpio_t pin)
{
GPIO_BASE->OUTCLR = (1 << pin);
}
void gpio_toggle(gpio_t pin)
{
GPIO_BASE->OUT ^= (1 << pin);
}
void gpio_write(gpio_t pin, int value)
{
if (value) {
GPIO_BASE->OUTSET = (1 << pin);
} else {
GPIO_BASE->OUTCLR = (1 << pin);
}
}
void isr_gpiote(void)
{
if (NRF_GPIOTE->EVENTS_IN[0] == 1) {
NRF_GPIOTE->EVENTS_IN[0] = 0;
exti_chan.cb(exti_chan.arg);
}
cortexm_isr_end();
}