x86_ports.h
6.05 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
/* Copyright (C) 2004, 2005, 2006 Board of Trustees, Leland Stanford
* Jr. University. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
// Copy of Pintos' threads/io.h, license header extracted from Pintos' LICENSE file.
#ifndef CPU__X86__PORTS_H__
#define CPU__X86__PORTS_H__
#include <stdlib.h>
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Reads and returns a byte from PORT.
* @param[in] port Port to read from.
* @returns Read value.
*/
static inline uint8_t __attribute__((always_inline)) inb(uint16_t port)
{
/* See [IA32-v2a] "IN". */
uint8_t data;
__asm__ volatile("inb %w1, %b0" : "=a"(data) : "Nd"(port));
return data;
}
/**
* @brief Reads multiple bytes from a port.
* @param[in] port Port to read from.
* @param[out] addr Buffer to write the read values into.
* @param[in] cnt Number of bytes to read.
*/
static inline void __attribute__((always_inline)) insb(uint16_t port, void *addr, size_t cnt)
{
/* See [IA32-v2a] "INS". */
__asm__ volatile("rep insb" : "+D"(addr), "+c"(cnt) : "d"(port) : "memory");
}
/**
* @brief Reads and returns a word from PORT.
* @param[in] port Port to read from.
* @returns Read value.
*/
static inline uint16_t __attribute__((always_inline)) inw(uint16_t port)
{
uint16_t data;
/* See [IA32-v2a] "IN". */
__asm__ volatile("inw %w1, %w0" : "=a"(data) : "Nd"(port));
return data;
}
/**
* @brief Reads multiple words from a port.
* @param[in] port Port to read from.
* @param[out] addr Buffer to write the read values into.
* @param[in] cnt Number of words to read.
*/
static inline void __attribute__((always_inline)) insw(uint16_t port, void *addr, size_t cnt)
{
/* See [IA32-v2a] "INS". */
__asm__ volatile("rep insw" : "+D"(addr), "+c"(cnt) : "d"(port) : "memory");
}
/**
* @brief Reads and returns a long from PORT.
* @param[in] port Port to read from.
* @returns Read value.
*/
static inline uint32_t __attribute__((always_inline)) inl(uint16_t port)
{
/* See [IA32-v2a] "IN". */
uint32_t data;
__asm__ volatile("inl %w1, %0" : "=a"(data) : "Nd"(port));
return data;
}
/**
* @brief Reads multiple longs from a port.
* @param[in] port Port to read from.
* @param[out] addr Buffer to write the read values into.
* @param[in] cnt Number of words to read.
*/
static inline void __attribute__((always_inline)) insl(uint16_t port, void *addr, size_t cnt)
{
/* See [IA32-v2a] "INS". */
__asm__ volatile("rep insl" : "+D"(addr), "+c"(cnt) : "d"(port) : "memory");
}
/**
* @brief Writes a byte into a port.
* @param[in] port Port to write into.
* @param[in] data Byte to write.
*/
static inline void __attribute__((always_inline)) outb(uint16_t port, uint8_t data)
{
/* See [IA32-v2b] "OUT". */
__asm__ volatile("outb %b0, %w1" : : "a"(data), "Nd"(port));
}
/**
* @brief Writes multiple bytes into a port.
* @param[in] port Port to write into.
* @param[in] addr Buffer to read from.
* @param[in] cnt Number of bytes to write.
*/
static inline void __attribute__((always_inline)) outsb(uint16_t port, const void *addr, size_t cnt)
{
/* See [IA32-v2b] "OUTS". */
__asm__ volatile("rep outsb" : "+S"(addr), "+c"(cnt) : "d"(port));
}
/**
* @brief Writes a word into a port.
* @param[in] port Port to write into.
* @param[in] data Word to write.
*/
static inline void __attribute__((always_inline)) outw(uint16_t port, uint16_t data)
{
/* See [IA32-v2b] "OUT". */
__asm__ volatile("outw %w0, %w1" : : "a"(data), "Nd"(port));
}
/**
* @brief Writes multiple words into a port.
* @param[in] port Port to write into.
* @param[in] addr Buffer to read from.
* @param[in] cnt Number of words to write.
*/
static inline void __attribute__((always_inline)) outsw(uint16_t port, const void *addr, size_t cnt)
{
/* See [IA32-v2b] "OUTS". */
__asm__ volatile("rep outsw" : "+S"(addr), "+c"(cnt) : "d"(port));
}
/**
* @brief Writes a long into a port.
* @param[in] port Port to write into.
* @param[in] data Long to write.
*/
static inline void __attribute__((always_inline)) outl(uint16_t port, uint32_t data)
{
/* See [IA32-v2b] "OUT". */
__asm__ volatile("outl %0, %w1" : : "a"(data), "Nd"(port));
}
/**
* @brief Writes multiple longs into a port.
* @param[in] port Port to write into.
* @param[in] addr Buffer to read from.
* @param[in] cnt Number of longs to write.
*/
static inline void __attribute__((always_inline)) outsl(uint16_t port, const void *addr, size_t cnt)
{
/* See [IA32-v2b] "OUTS". */
__asm__ volatile("rep outsl" : "+S"(addr), "+c"(cnt) : "d"(port));
}
/**
* @brief Make sure a write to a port was already acknowledged.
*/
static inline void __attribute__((always_inline)) io_wait(void)
{
__asm__ volatile(" jmp 1f\n"
"1: jmp 2f\n"
"2:");
}
#ifdef __cplusplus
}
#endif
#endif