fb11e647
 vrobic
reseau statique a...
|
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
|
/*
* Copyright (C) 2015 Daniel Krebs
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_samd21
* @{
* @file
* @brief Low-level RTT driver implementation
* @author Daniel Krebs <github@daniel-krebs.net>
* @}
*/
#include <time.h>
#include "cpu.h"
#include "periph/rtt.h"
#include "periph_conf.h"
/* guard file in case no RTT device was specified */
#if RTT_NUMOF
typedef struct {
rtt_cb_t overflow_cb; /**< called from RTT interrupt on overflow */
void* overflow_arg; /**< argument passed to overflow callback */
rtt_cb_t alarm_cb; /**< called from RTT interrupt on alarm */
void* alarm_arg; /**< argument passen to alarm callback */
} rtt_state_t;
static rtt_state_t rtt_callback;
/**
* @brief Initialize RTT module
*
* The RTT is running at 32768 Hz by default, i.e. @ XOSC32K frequency without
* divider. There are 2 cascaded dividers in the clock path:
*
* - GCLK_GENDIV_DIV(n): between 1 and 31
* - RTC_MODE0_CTRL_PRESCALER_DIVn: between 1 and 1024, see defines in `component_rtc.h`
*
* However the division scheme of GCLK_GENDIV_DIV can be changed by setting
* GCLK_GENCTRL_DIVSEL:
*
* - GCLK_GENCTRL_DIVSEL = 0: Clock divided by GENDIV.DIV (default)
* - GCLK_GENCTRL_DIVSEL = 1: Clock divided by 2^( GENDIV.DIV + 1 )
*/
void rtt_init(void)
{
RtcMode0 *rtcMode0 = &(RTT_DEV);
/* Turn on power manager for RTC */
PM->APBAMASK.reg |= PM_APBAMASK_RTC;
/* RTC uses External 32,768KHz Oscillator because OSC32K isn't accurate
* enough (p1075/1138). Also keep running in standby. */
SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_ONDEMAND |
SYSCTRL_XOSC32K_EN32K |
SYSCTRL_XOSC32K_XTALEN |
SYSCTRL_XOSC32K_STARTUP(6) |
#if RTT_RUNSTDBY
SYSCTRL_XOSC32K_RUNSTDBY |
#endif
SYSCTRL_XOSC32K_ENABLE;
/* Setup clock GCLK2 with divider 1 */
GCLK->GENDIV.reg = GCLK_GENDIV_ID(2) | GCLK_GENDIV_DIV(1);
while (GCLK->STATUS.bit.SYNCBUSY) {}
/* Enable GCLK2 with XOSC32K as source. Use divider without modification
* and keep running in standby. */
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(2) |
GCLK_GENCTRL_GENEN |
#if RTT_RUNSTDBY
GCLK_GENCTRL_RUNSTDBY |
#endif
GCLK_GENCTRL_SRC_XOSC32K;
while (GCLK->STATUS.bit.SYNCBUSY) {}
/* Connect GCLK2 to RTC */
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_GEN_GCLK2 |
GCLK_CLKCTRL_CLKEN |
GCLK_CLKCTRL_ID(RTC_GCLK_ID);
while (GCLK->STATUS.bit.SYNCBUSY) {}
/* Disable RTC */
rtt_poweroff();
/* Reset RTC */
rtcMode0->CTRL.bit.SWRST = 1;
while (rtcMode0->STATUS.bit.SYNCBUSY || rtcMode0->CTRL.bit.SWRST) {}
/* Configure as 32bit counter with no prescaler and no clear on match compare */
rtcMode0->CTRL.reg = RTC_MODE0_CTRL_MODE_COUNT32 | RTC_MODE0_CTRL_PRESCALER_DIV1;
while (rtcMode0->STATUS.bit.SYNCBUSY) {}
/* Setup interrupt */
NVIC_EnableIRQ(RTT_IRQ);
/* Enable RTC */
rtt_poweron();
}
void rtt_set_overflow_cb(rtt_cb_t cb, void *arg)
{
rtt_callback.overflow_cb = cb;
rtt_callback.overflow_arg = arg;
/* Enable Overflow Interrupt and clear flag */
RtcMode0 *rtcMode0 = &(RTT_DEV);
rtcMode0->INTFLAG.bit.OVF = 1;
rtcMode0->INTENSET.bit.OVF = 1;
}
void rtt_clear_overflow_cb(void)
{
/* Disable Overflow Interrupt */
RtcMode0 *rtcMode0 = &(RTT_DEV);
rtcMode0->INTENCLR.bit.OVF = 1;
rtt_callback.overflow_cb = NULL;
rtt_callback.overflow_arg = NULL;
}
uint32_t rtt_get_counter(void)
{
RtcMode0 *rtcMode0 = &(RTT_DEV);
while (rtcMode0->STATUS.bit.SYNCBUSY) {}
return rtcMode0->COUNT.reg;
}
void rtt_set_counter(uint32_t counter)
{
RtcMode0 *rtcMode0 = &(RTT_DEV);
rtcMode0->COUNT.reg = counter;
while (rtcMode0->STATUS.bit.SYNCBUSY) {}
}
void rtt_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)
{
rtt_callback.alarm_cb = cb;
rtt_callback.alarm_arg = arg;
RtcMode0 *rtcMode0 = &(RTT_DEV);
rtcMode0->COMP[0].reg = alarm;
while (rtcMode0->STATUS.bit.SYNCBUSY) {}
/* Enable Compare Interrupt and clear flag */
rtcMode0->INTFLAG.bit.CMP0 = 1;
rtcMode0->INTENSET.bit.CMP0 = 1;
}
void rtt_clear_alarm(void)
{
/* Disable Compare Interrupt */
RtcMode0 *rtcMode0 = &(RTT_DEV);
rtcMode0->INTENCLR.bit.CMP0 = 1;
rtt_callback.alarm_cb = NULL;
rtt_callback.alarm_arg = NULL;
}
uint32_t rtt_get_alarm(void)
{
RtcMode0 *rtcMode0 = &(RTT_DEV);
return rtcMode0->COMP[0].reg;
}
void rtt_poweron(void)
{
RtcMode0 *rtcMode0 = &(RTT_DEV);
rtcMode0->CTRL.bit.ENABLE = 1;
while (rtcMode0->STATUS.bit.SYNCBUSY) {}
}
void rtt_poweroff(void)
{
RtcMode0 *rtcMode0 = &(RTT_DEV);
rtcMode0->CTRL.bit.ENABLE = 0;
while (rtcMode0->STATUS.bit.SYNCBUSY) {}
}
void RTT_ISR(void)
{
RtcMode0 *rtcMode0 = &(RTT_DEV);
uint8_t status = rtcMode0->INTFLAG.reg;
if ( (status & RTC_MODE0_INTFLAG_CMP0) && (rtt_callback.alarm_cb != NULL) ) {
rtt_callback.alarm_cb(rtt_callback.alarm_arg);
rtcMode0->INTFLAG.bit.CMP0 = 1;
}
if ( (status & RTC_MODE0_INTFLAG_OVF) && (rtt_callback.overflow_cb != NULL) ) {
rtt_callback.overflow_cb(rtt_callback.overflow_arg);
rtcMode0->INTFLAG.bit.OVF = 1;
}
cortexm_isr_end();
}
#endif /* RTT_NUMOF */
|