Release 14.3 par P.40xd (nt64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

ALTIUM-03::  Tue Mar 28 09:08:59 2017

par -w -t 1 projet_sc_map.ncd projet_sc.ncd
"C:\Users\Altium-3\Desktop\blas_delaporte\ProjectOutputs\Default - All
Constraints\projet_sc_map.pcf" 


Constraints file: C:\Users\Altium-3\Desktop\blas_delaporte\ProjectOutputs\Default - All Constraints\projet_sc_map.pcf.
Loading device for application Rf_Device from file '3s1500.nph' in environment C:\Xilinx\14.3\ISE_DS\ISE\.
   "projet_sc" is an NCD, version 3.2, device xc3s1500, package fg676, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
   Note: For the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high".

Device speed data version:  "PRODUCTION 1.39 2012-10-12".


Device Utilization Summary:

   Number of External IOBs                  26 out of 487     5%
      Number of LOCed IOBs                  26 out of 26    100%



Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 1 secs 
Finished initial Timing Analysis.  REAL time: 1 secs 


Starting Placer
Total REAL time at the beginning of Placer: 1 secs 
Total CPU  time at the beginning of Placer: 1 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:5e663589) REAL time: 1 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:5e663589) REAL time: 1 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:5e663589) REAL time: 1 secs 

Phase 4.2  Initial Clock and IO Placement
Phase 4.2  Initial Clock and IO Placement (Checksum:5e663589) REAL time: 1 secs 

Phase 5.36  Local Placement Optimization
Phase 5.36  Local Placement Optimization (Checksum:5e663589) REAL time: 1 secs 

Phase 6.8  Global Placement
Phase 6.8  Global Placement (Checksum:5e663589) REAL time: 1 secs 

Phase 7.5  Local Placement Optimization
Phase 7.5  Local Placement Optimization (Checksum:5e663589) REAL time: 1 secs 

Phase 8.18  Placement Optimization
Phase 8.18  Placement Optimization (Checksum:5e663589) REAL time: 1 secs 

Phase 9.5  Local Placement Optimization
Phase 9.5  Local Placement Optimization (Checksum:5e663589) REAL time: 1 secs 

Total REAL time to Placer completion: 1 secs 
Total CPU  time to Placer completion: 1 secs 
Writing design to file projet_sc.ncd



Starting Router


Phase  1  : 44 unrouted;      REAL time: 2 secs 

Phase  2  : 44 unrouted;      REAL time: 2 secs 

Phase  3  : 0 unrouted;      REAL time: 2 secs 

Phase  4  : 0 unrouted; (Par is working to improve performance)     REAL time: 3 secs 

Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 3 secs 

Updating file: projet_sc.ncd with current fully routed design.

Phase  6  : 0 unrouted; (Par is working to improve performance)     REAL time: 3 secs 

Phase  7  : 0 unrouted; (Par is working to improve performance)     REAL time: 3 secs 

Phase  8  : 0 unrouted; (Par is working to improve performance)     REAL time: 3 secs 

Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 2 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

Timing Score: 0 (Setup: 0, Hold: 0)



Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  298 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file projet_sc.ncd



PAR done!