projet_sc.mof
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FamilyName=Spartan3
VendorName=Xilinx
SynthArchName=spartan3
LogFileName=C:\Users\Altium-3\Desktop\blas_delaporte\ProjectOutputs\Default - All Constraints\projet_sc.synthlog
OutputFileName=C:\Users\Altium-3\Desktop\blas_delaporte\ProjectOutputs\Default - All Constraints\projet_sc.edf
BFLFileName=C:\Users\Altium-3\Desktop\blas_delaporte\ProjectOutputs\Default - All Constraints\projet_sc.bfl
Entity=projet_sc
VerilogMode=1
VHDL87=0
InsertIOBuffers=True
SDB_MaxMultipliers=32
InferRam=Auto
RomStyle=Logic
SisOptimizationLevel=Medium
SDB_ActiveLowAsynPreset=False
SDB_ActiveLowAsynReset=False
SDB_ActiveLowTristate=False
SDB_AlteraAdder=False
SDB_AlteraLpmAddSub=False
SDB_AlteraLpmCompare=False
SDB_AlteraLpmMultiply=False
SDB_AlteraLVDS=False
SDB_EdifBitvecInHex=True
SDB_EnableAsynFlipFlop=True
SDB_EnableLatch=False
SDB_EnableSyncFlipFlop=True
SDB_LatticeCCU2=False
SDB_LatticeCCU2B=False
SDB_LatticeFADD2=False
SDB_LatticeFADD2B=False
SDB_LatticeFSUB2=False
SDB_LatticeFSUB2B=False
SDB_LatticeMult=False
SDB_LatticeMultB=False
SDB_TristateInternalToMux=False
SDB_TristatePushToTop=False
SDB_TristateToMux=False
SDB_XilinxMacroAdder=True
SDB_XilinxMacroMux=True
SDB_XilinxMult=True
SDB_XilinxMuxF56=True
SDB_XilinxMuxF78=False