essai1.VHD
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------------------------------------------------------------
-- VHDL essai1
-- 2017 5 17 18 18 52
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 16.0.9.368
------------------------------------------------------------
------------------------------------------------------------
-- VHDL essai1
------------------------------------------------------------
Library IEEE;
Use IEEE.std_logic_1164.all;
--synthesis translate_off
Library GENERIC_LIB;
Use GENERIC_LIB.all;
--synthesis translate_on
Entity essai1 Is
port
(
CLK_BRD : In STD_LOGIC; -- ObjectKind=Port|PrimaryId=CLK_BRD
HA2 : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=HA2
HA8 : Out STD_LOGIC -- ObjectKind=Port|PrimaryId=HA8
);
attribute MacroCell : boolean;
End essai1;
------------------------------------------------------------
------------------------------------------------------------
Architecture Structure Of essai1 Is
Component CD4CES -- ObjectKind=Part|PrimaryId=U7|SecondaryId=1
port
(
C : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U7-C
CE : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U7-CE
CEO : out STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U7-CEO
CLR : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U7-CLR
Q0 : out STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U7-Q0
Q1 : out STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U7-Q1
Q2 : out STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U7-Q2
Q3 : out STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U7-Q3
TC : out STD_LOGIC -- ObjectKind=Pin|PrimaryId=U7-TC
);
End Component;
Component CLKGEN -- ObjectKind=Part|PrimaryId=U3|SecondaryId=1
port
(
FREQ : out STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U3-FREQ
TIMEBASE : in STD_LOGIC -- ObjectKind=Pin|PrimaryId=U3-TIMEBASE
);
End Component;
Component Configurable_U1 -- ObjectKind=Part|PrimaryId=U1|SecondaryId=1
port
(
C : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U1-C
D : in STD_LOGIC_VECTOR(7 Downto 0); -- ObjectKind=Pin|PrimaryId=U1-D[7..0]
PWM : out STD_LOGIC -- ObjectKind=Pin|PrimaryId=U1-PWM
);
End Component;
Component Configurable_U2 -- ObjectKind=Part|PrimaryId=U2|SecondaryId=1
port
(
C : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U2-C
D_B : in STD_LOGIC_VECTOR(7 Downto 0); -- ObjectKind=Pin|PrimaryId=U2-D_B[7..0]
Q_B : out STD_LOGIC_VECTOR(7 Downto 0) -- ObjectKind=Pin|PrimaryId=U2-Q_B[7..0]
);
End Component;
Component Configurable_U4 -- ObjectKind=Part|PrimaryId=U4|SecondaryId=1
port
(
A : in STD_LOGIC_VECTOR(7 Downto 0); -- ObjectKind=Pin|PrimaryId=U4-A[7..0]
B : in STD_LOGIC_VECTOR(7 Downto 0); -- ObjectKind=Pin|PrimaryId=U4-B[7..0]
LT : out STD_LOGIC -- ObjectKind=Pin|PrimaryId=U4-LT
);
End Component;
Component Configurable_U5 -- ObjectKind=Part|PrimaryId=U5|SecondaryId=1
port
(
AOUT : out STD_LOGIC_VECTOR(7 Downto 0) -- ObjectKind=Pin|PrimaryId=U5-AOUT[7..0]
);
End Component;
Component Configurable_U6 -- ObjectKind=Part|PrimaryId=U6|SecondaryId=1
port
(
I0 : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U6-I0
I1 : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U6-I1
I2 : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U6-I2
I3 : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U6-I3
I4 : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U6-I4
I5 : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U6-I5
I6 : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U6-I6
I7 : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U6-I7
O : out STD_LOGIC_VECTOR(7 Downto 0) -- ObjectKind=Pin|PrimaryId=U6-O[7..0]
);
End Component;
Signal PinSignal_U1_PWM : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_PWM
Signal PinSignal_U2_Q_B : STD_LOGIC_VECTOR(7 Downto 0); -- ObjectKind=Net|PrimaryId=NetU2_Q_B[7..0]
Signal PinSignal_U3_FREQ : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU2_C
Signal PinSignal_U4_LT : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU4_LT
Signal PinSignal_U5_AOUT : STD_LOGIC_VECTOR(7 Downto 0); -- ObjectKind=Net|PrimaryId=NetU4_B[7..0]
Signal PinSignal_U6_O : STD_LOGIC_VECTOR(7 Downto 0); -- ObjectKind=Net|PrimaryId=NetU1_D[7..0]
Signal PinSignal_U7_Q0 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU6_I4
Signal PinSignal_U7_Q1 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU6_I5
Signal PinSignal_U7_Q2 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU6_I6
Signal PinSignal_U7_Q3 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU6_I7
Signal PinSignal_U8_CEO : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU7_CE
Signal PinSignal_U8_Q0 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU6_I0
Signal PinSignal_U8_Q1 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU6_I1
Signal PinSignal_U8_Q2 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU6_I2
Signal PinSignal_U8_Q3 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU6_I3
Signal PinSignal_U8_TC : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU7_C
Signal PowerSignal_GND : STD_LOGIC; -- ObjectKind=Net|PrimaryId=GND
Signal PowerSignal_VCC : STD_LOGIC; -- ObjectKind=Net|PrimaryId=VCC
Begin
U8 : CD4CES -- ObjectKind=Part|PrimaryId=U8|SecondaryId=1
Port Map
(
C => PinSignal_U3_FREQ, -- ObjectKind=Pin|PrimaryId=U8-C
CE => PowerSignal_VCC, -- ObjectKind=Pin|PrimaryId=U8-CE
CEO => PinSignal_U8_CEO, -- ObjectKind=Pin|PrimaryId=U8-CEO
CLR => PowerSignal_GND, -- ObjectKind=Pin|PrimaryId=U8-CLR
Q0 => PinSignal_U8_Q0, -- ObjectKind=Pin|PrimaryId=U8-Q0
Q1 => PinSignal_U8_Q1, -- ObjectKind=Pin|PrimaryId=U8-Q1
Q2 => PinSignal_U8_Q2, -- ObjectKind=Pin|PrimaryId=U8-Q2
Q3 => PinSignal_U8_Q3, -- ObjectKind=Pin|PrimaryId=U8-Q3
TC => PinSignal_U8_TC -- ObjectKind=Pin|PrimaryId=U8-TC
);
U7 : CD4CES -- ObjectKind=Part|PrimaryId=U7|SecondaryId=1
Port Map
(
C => PinSignal_U8_TC, -- ObjectKind=Pin|PrimaryId=U7-C
CE => PinSignal_U8_CEO, -- ObjectKind=Pin|PrimaryId=U7-CE
CLR => PowerSignal_GND, -- ObjectKind=Pin|PrimaryId=U7-CLR
Q0 => PinSignal_U7_Q0, -- ObjectKind=Pin|PrimaryId=U7-Q0
Q1 => PinSignal_U7_Q1, -- ObjectKind=Pin|PrimaryId=U7-Q1
Q2 => PinSignal_U7_Q2, -- ObjectKind=Pin|PrimaryId=U7-Q2
Q3 => PinSignal_U7_Q3 -- ObjectKind=Pin|PrimaryId=U7-Q3
);
U6 : Configurable_U6 -- ObjectKind=Part|PrimaryId=U6|SecondaryId=1
Port Map
(
I0 => PinSignal_U8_Q0, -- ObjectKind=Pin|PrimaryId=U6-I0
I1 => PinSignal_U8_Q1, -- ObjectKind=Pin|PrimaryId=U6-I1
I2 => PinSignal_U8_Q2, -- ObjectKind=Pin|PrimaryId=U6-I2
I3 => PinSignal_U8_Q3, -- ObjectKind=Pin|PrimaryId=U6-I3
I4 => PinSignal_U7_Q0, -- ObjectKind=Pin|PrimaryId=U6-I4
I5 => PinSignal_U7_Q1, -- ObjectKind=Pin|PrimaryId=U6-I5
I6 => PinSignal_U7_Q2, -- ObjectKind=Pin|PrimaryId=U6-I6
I7 => PinSignal_U7_Q3, -- ObjectKind=Pin|PrimaryId=U6-I7
O => PinSignal_U6_O -- ObjectKind=Pin|PrimaryId=U6-O[7..0]
);
U5 : Configurable_U5 -- ObjectKind=Part|PrimaryId=U5|SecondaryId=1
Port Map
(
AOUT => PinSignal_U5_AOUT -- ObjectKind=Pin|PrimaryId=U5-AOUT[7..0]
);
U4 : Configurable_U4 -- ObjectKind=Part|PrimaryId=U4|SecondaryId=1
Port Map
(
A => PinSignal_U2_Q_B, -- ObjectKind=Pin|PrimaryId=U4-A[7..0]
B => PinSignal_U5_AOUT, -- ObjectKind=Pin|PrimaryId=U4-B[7..0]
LT => PinSignal_U4_LT -- ObjectKind=Pin|PrimaryId=U4-LT
);
U3 : CLKGEN -- ObjectKind=Part|PrimaryId=U3|SecondaryId=1
Port Map
(
FREQ => PinSignal_U3_FREQ, -- ObjectKind=Pin|PrimaryId=U3-FREQ
TIMEBASE => CLK_BRD -- ObjectKind=Pin|PrimaryId=U3-TIMEBASE
);
U2 : Configurable_U2 -- ObjectKind=Part|PrimaryId=U2|SecondaryId=1
Port Map
(
C => PinSignal_U3_FREQ, -- ObjectKind=Pin|PrimaryId=U2-C
D_B => PinSignal_U6_O, -- ObjectKind=Pin|PrimaryId=U2-D_B[7..0]
Q_B => PinSignal_U2_Q_B -- ObjectKind=Pin|PrimaryId=U2-Q_B[7..0]
);
U1 : Configurable_U1 -- ObjectKind=Part|PrimaryId=U1|SecondaryId=1
Port Map
(
C => CLK_BRD, -- ObjectKind=Pin|PrimaryId=U1-C
D => PinSignal_U6_O, -- ObjectKind=Pin|PrimaryId=U1-D[7..0]
PWM => PinSignal_U1_PWM -- ObjectKind=Pin|PrimaryId=U1-PWM
);
-- Signal Assignments
---------------------
HA2 <= PinSignal_U1_PWM; -- ObjectKind=Net|PrimaryId=NetU1_PWM
HA8 <= PinSignal_U4_LT; -- ObjectKind=Net|PrimaryId=NetU4_LT
PowerSignal_GND <= '0'; -- ObjectKind=Net|PrimaryId=GND
PowerSignal_VCC <= '1'; -- ObjectKind=Net|PrimaryId=VCC
End Structure;
------------------------------------------------------------