fpga_projet_map.mrp
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Release 14.3 Map P.40xd (nt64)
Xilinx Mapping Report File for Design 'FPGA_projet'
Design Information
------------------
Command Line : map -p XC3S1500-FG676-4 -pr b -tx off -c 100 -t 1 -u
-ignore_keep_hierarchy -o fpga_projet_map.ncd fpga_projet.ngd
Target Device : xc3s1500
Target Package : fg676
Target Speed : -4
Mapper Version : spartan3 -- $Revision: 1.55 $
Mapped Date : Wed May 17 18:19:11 2017
Design Summary
--------------
Number of errors: 0
Number of warnings: 89
Logic Utilization:
Number of Slice Flip Flops: 463 out of 26,624 1%
Number of 4 input LUTs: 437 out of 26,624 1%
Logic Distribution:
Number of occupied Slices: 343 out of 13,312 2%
Number of Slices containing only related logic: 343 out of 343 100%
Number of Slices containing unrelated logic: 0 out of 343 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 449 out of 26,624 1%
Number used as logic: 437
Number used as a route-thru: 12
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 7 out of 487 1%
IOB Flip Flops: 2
Number of BUFGMUXs: 2 out of 8 25%
Average Fanout of Non-Clock Nets: 3.01
Peak Memory Usage: 281 MB
Total REAL time to MAP completion: 2 secs
Total CPU time to MAP completion: 2 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:Map:124 - The command line option -t can only be used when running in
timing mode (-timing option). The option will be ignored.
WARNING:Map:210 - The -tx switch is not supported for this architecture, and
will be ignored.
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol "physical_group_n2j/n2j" (output signal=n2j) has a mix of clock and
non-clock loads. The non-clock loads are:
Pin I0 of U3/U_FREQ/freq_sig_m2_am
Pin I0 of U3/U_FREQ/divisor_5_0_component_c0/clkd
Pin I0 of U3/U_FREQ/divisor_5_0_component_c0/clko
WARNING:Pack:266 - The function generator U5/TAP1/tapstate_r__not_0 failed to
merge with F5 multiplexer U5/TAP1/i223. Tried to combine two collections of
symbols from different positions within the same layer. The design will
exhibit suboptimal timing.
WARNING:Pack:266 - The function generator U5/TAP1/tapstate_r__not_0 failed to
merge with F5 multiplexer U5/TAP1/i224. Unable to resolve the conflicts
between two or more collections of symbols which have restrictive placement
or routing requirements. The original symbols are:
MUXF5 symbol "U5/TAP1/i224" (Output Signal = U5/TAP1/n237)
LUT symbol "U5/TAP1/tapstate_r__not_0" (Output Signal =
U5/TAP1/tapstate_r__not_0)
MUXF5 symbol "U5/TAP1/i222" (Output Signal = U5/TAP1/n235)
Failure 1: Unable to combine the following symbols into a single slice.
MUXF5 symbol "U5/TAP1/i224" (Output Signal = U5/TAP1/n237)
MUXF5 symbol "U5/TAP1/i222" (Output Signal = U5/TAP1/n235)
LUT symbol "U5/TAP1/tapstate_r__not_0" (Output Signal =
U5/TAP1/tapstate_r__not_0)
There is more than one F5MUX.
Failure 2: Unable to combine the following symbols into a single slice.
MUXF6 symbol "U5/TAP1/i227" (Output Signal = U5/TAP1/n240)
MUXF5 symbol "U5/TAP1/i225" (Output Signal = U5/TAP1/n238)
MUXF6 symbol "U5/TAP1/i226" (Output Signal = U5/TAP1/n239)
MUXF5 symbol "U5/TAP1/i223" (Output Signal = U5/TAP1/n236)
There is more than one MUXF6.
The design will exhibit suboptimal timing.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c9 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c10 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c1 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c4 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c5 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c3 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c7 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c8 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c6 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c0 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c2 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
U3/U_FREQ/divisor_9_0_component_c8/u1_s is sourced by a combinatorial pin.
This is not good design practice. Use the CE pin to control the loading of
data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
U3/U_FREQ/divisor_25_0_component_c9/u1_s is sourced by a combinatorial pin.
This is not good design practice. Use the CE pin to control the loading of
data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net PinSignal_U8_TC is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net PinSignal_U3_FREQ is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal <U3/TDO_ENABLE> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/TAP1/exit1dr> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_11> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_10> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_13> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_12> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_21> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_20> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_15> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_14> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_23> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_22> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_31> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_30> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_17> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_16> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_25> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_24> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_19> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_18> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_27> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_26> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_29> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_28> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_11> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_10> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_13> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_12> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_15> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_14> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/TAP1/reset> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_11> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_10> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_13> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_12> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_15> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_14> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U7/CEO> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_1> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_0> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_3> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_2> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_5> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_4> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_7> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_6> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_9> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_8> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Value/regout_0> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_1> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_0> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_3> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_2> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_5> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_4> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_7> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_6> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_9> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_8> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_1> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_0> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_3> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_2> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_5> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_4> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_7> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_6> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_9> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_8> is
incomplete. The signal does not drive any load pins in the design.
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network U7/CEO has no load.
INFO:LIT:395 - The above info message is repeated 68 more times for the
following (max. 5 shown):
U5/RegisterInput_Value/regout_0,
U5/RegisterConfiguration/regout_31,
U5/RegisterConfiguration/regout_30,
U5/RegisterConfiguration/regout_29,
U5/RegisterConfiguration/regout_28
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
Section 4 - Removed Logic Summary
---------------------------------
245 block(s) optimized away
157 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
The signal "U5/TRST_not" is sourceless and has been removed.
The signal "U5/RegisterInput_Value/n19" is sourceless and has been removed.
The signal "U5/RegisterInput_Value/n21" is sourceless and has been removed.
The signal "U5/control_register/n68" is sourceless and has been removed.
The signal "U5/control_register/n70" is sourceless and has been removed.
The signal "U5/control_register/n74" is sourceless and has been removed.
The signal "U5/control_register/n76" is sourceless and has been removed.
The signal "U5/control_register/n78" is sourceless and has been removed.
The signal "U5/control_register/n80" is sourceless and has been removed.
The signal "U5/control_register/n82" is sourceless and has been removed.
The signal "U5/control_register/n84" is sourceless and has been removed.
The signal "U5/control_register/n86" is sourceless and has been removed.
The signal "U5/control_register/n88" is sourceless and has been removed.
The signal "U5/control_register/n90" is sourceless and has been removed.
The signal "U5/control_register/n92" is sourceless and has been removed.
The signal "U5/control_register/n94" is sourceless and has been removed.
The signal "U5/control_register/n96" is sourceless and has been removed.
The signal "U5/control_register/n98" is sourceless and has been removed.
The signal "U5/control_register/n100" is sourceless and has been removed.
The signal "U5/RegisterOutput_Value/n70" is sourceless and has been removed.
The signal "U5/RegisterOutput_Value/n76" is sourceless and has been removed.
The signal "U5/RegisterOutput_Value/n78" is sourceless and has been removed.
The signal "U5/RegisterOutput_Value/n82" is sourceless and has been removed.
The signal "U5/RegisterOutput_Value/n88" is sourceless and has been removed.
The signal "U5/RegisterOutput_Value/n90" is sourceless and has been removed.
The signal "U5/RegisterOutput_Value/n94" is sourceless and has been removed.
The signal "U5/RegisterOutput_Value/n100" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n236" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n238" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n242" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n244" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n246" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n248" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n250" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n252" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n254" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n256" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n258" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n260" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n262" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n264" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n266" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n268" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n270" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n272" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n274" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n276" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n278" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n280" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n282" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n284" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n286" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n288" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n290" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n292" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n294" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n296" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n298" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n300" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n302" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n304" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n306" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n308" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n310" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n312" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n314" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n316" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n318" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n320" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n322" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n324" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n326" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n328" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n330" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n332" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n334" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n336" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n338" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n340" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n342" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n344" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n346" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n348" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n350" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n352" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n354" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n356" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n358" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n360" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n362" is sourceless and has been removed.
The signal "U5/RegisterConfiguration/n364" is sourceless and has been removed.
The signal "U5/TAP1/trst_not" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n124" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n126" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n130" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n132" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n134" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n136" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n138" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n140" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n142" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n144" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n146" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n148" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n150" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n152" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n154" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n156" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n158" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n160" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n162" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n164" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n166" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n168" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n170" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n172" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n174" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n176" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n178" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n180" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n182" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n184" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n186" is sourceless and has been removed.
The signal "U5/RegisterInput_Length/n188" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n124" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n126" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n130" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n132" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n134" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n136" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n138" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n140" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n142" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n144" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n146" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n148" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n150" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n152" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n154" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n156" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n158" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n160" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n162" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n164" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n166" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n168" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n170" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n172" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n174" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n176" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n178" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n180" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n182" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n184" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n186" is sourceless and has been removed.
The signal "U5/RegisterOutput_Length/n188" is sourceless and has been removed.
The signal "U3/U_FREQ/tap1/TRST_i" is sourceless and has been removed.
Optimized Block(s):
TYPE BLOCK
GND U1/n2r
VCC U3/U_FREQ/divisor_main_component_c10/VCC
INV U3/U_FREQ/tap1/TRST_i
AND2 U5/RegisterConfiguration/n236
AND2B1 U5/RegisterConfiguration/n238
AND2 U5/RegisterConfiguration/n242
AND2B1 U5/RegisterConfiguration/n244
AND2 U5/RegisterConfiguration/n246
AND2B1 U5/RegisterConfiguration/n248
AND2 U5/RegisterConfiguration/n250
AND2B1 U5/RegisterConfiguration/n252
AND2 U5/RegisterConfiguration/n254
AND2B1 U5/RegisterConfiguration/n256
AND2 U5/RegisterConfiguration/n258
AND2B1 U5/RegisterConfiguration/n260
AND2 U5/RegisterConfiguration/n262
AND2B1 U5/RegisterConfiguration/n264
AND2 U5/RegisterConfiguration/n266
AND2B1 U5/RegisterConfiguration/n268
AND2 U5/RegisterConfiguration/n270
AND2B1 U5/RegisterConfiguration/n272
AND2 U5/RegisterConfiguration/n274
AND2B1 U5/RegisterConfiguration/n276
AND2 U5/RegisterConfiguration/n278
AND2B1 U5/RegisterConfiguration/n280
AND2 U5/RegisterConfiguration/n282
AND2B1 U5/RegisterConfiguration/n284
AND2 U5/RegisterConfiguration/n286
AND2B1 U5/RegisterConfiguration/n288
AND2 U5/RegisterConfiguration/n290
AND2B1 U5/RegisterConfiguration/n292
AND2 U5/RegisterConfiguration/n294
AND2B1 U5/RegisterConfiguration/n296
AND2 U5/RegisterConfiguration/n298
AND2B1 U5/RegisterConfiguration/n300
AND2 U5/RegisterConfiguration/n302
AND2B1 U5/RegisterConfiguration/n304
AND2 U5/RegisterConfiguration/n306
AND2B1 U5/RegisterConfiguration/n308
AND2 U5/RegisterConfiguration/n310
AND2B1 U5/RegisterConfiguration/n312
AND2 U5/RegisterConfiguration/n314
AND2B1 U5/RegisterConfiguration/n316
AND2 U5/RegisterConfiguration/n318
AND2B1 U5/RegisterConfiguration/n320
AND2 U5/RegisterConfiguration/n322
AND2B1 U5/RegisterConfiguration/n324
AND2 U5/RegisterConfiguration/n326
AND2B1 U5/RegisterConfiguration/n328
AND2 U5/RegisterConfiguration/n330
AND2B1 U5/RegisterConfiguration/n332
AND2 U5/RegisterConfiguration/n334
AND2B1 U5/RegisterConfiguration/n336
AND2 U5/RegisterConfiguration/n338
AND2B1 U5/RegisterConfiguration/n340
AND2 U5/RegisterConfiguration/n342
AND2B1 U5/RegisterConfiguration/n344
AND2 U5/RegisterConfiguration/n346
AND2B1 U5/RegisterConfiguration/n348
AND2 U5/RegisterConfiguration/n350
AND2B1 U5/RegisterConfiguration/n352
AND2 U5/RegisterConfiguration/n354
AND2B1 U5/RegisterConfiguration/n356
AND2 U5/RegisterConfiguration/n358
AND2B1 U5/RegisterConfiguration/n360
AND2 U5/RegisterConfiguration/n362
AND2B1 U5/RegisterConfiguration/n364
AND2 U5/RegisterConfiguration/n6i
AND2 U5/RegisterConfiguration/n6n
AND2 U5/RegisterConfiguration/n6p
AND2 U5/RegisterConfiguration/n6r
AND2 U5/RegisterConfiguration/n6t
AND2 U5/RegisterConfiguration/n6v
AND2 U5/RegisterConfiguration/n6x
AND2 U5/RegisterConfiguration/n6z
AND2 U5/RegisterConfiguration/n7b
AND2 U5/RegisterConfiguration/n7d
AND2 U5/RegisterConfiguration/n7f
AND2 U5/RegisterConfiguration/n7h
AND2 U5/RegisterConfiguration/n7j
AND2 U5/RegisterConfiguration/n7l
AND2 U5/RegisterConfiguration/n7n
AND2 U5/RegisterConfiguration/n7p
AND2 U5/RegisterConfiguration/n7r
AND2 U5/RegisterConfiguration/n7v
AND2 U5/RegisterConfiguration/n7z
AND2 U5/RegisterConfiguration/n8b
AND2 U5/RegisterConfiguration/n8d
AND2 U5/RegisterConfiguration/n8f
AND2 U5/RegisterConfiguration/n8h
AND2 U5/RegisterConfiguration/n8j
AND2 U5/RegisterConfiguration/n8l
AND2 U5/RegisterConfiguration/n8n
AND2 U5/RegisterConfiguration/n8p
AND2 U5/RegisterConfiguration/n8r
AND2 U5/RegisterConfiguration/n8t
AND2 U5/RegisterInput_Length/n124
AND2B1 U5/RegisterInput_Length/n126
AND2 U5/RegisterInput_Length/n130
AND2B1 U5/RegisterInput_Length/n132
AND2 U5/RegisterInput_Length/n134
AND2B1 U5/RegisterInput_Length/n136
AND2 U5/RegisterInput_Length/n138
AND2B1 U5/RegisterInput_Length/n140
AND2 U5/RegisterInput_Length/n142
AND2B1 U5/RegisterInput_Length/n144
AND2 U5/RegisterInput_Length/n146
AND2B1 U5/RegisterInput_Length/n148
AND2 U5/RegisterInput_Length/n150
AND2B1 U5/RegisterInput_Length/n152
AND2 U5/RegisterInput_Length/n154
AND2B1 U5/RegisterInput_Length/n156
AND2 U5/RegisterInput_Length/n158
AND2B1 U5/RegisterInput_Length/n160
AND2 U5/RegisterInput_Length/n162
AND2B1 U5/RegisterInput_Length/n164
AND2 U5/RegisterInput_Length/n166
AND2B1 U5/RegisterInput_Length/n168
AND2 U5/RegisterInput_Length/n170
AND2B1 U5/RegisterInput_Length/n172
AND2 U5/RegisterInput_Length/n174
AND2B1 U5/RegisterInput_Length/n176
AND2 U5/RegisterInput_Length/n178
AND2B1 U5/RegisterInput_Length/n180
AND2 U5/RegisterInput_Length/n182
AND2B1 U5/RegisterInput_Length/n184
AND2 U5/RegisterInput_Length/n186
AND2B1 U5/RegisterInput_Length/n188
AND2 U5/RegisterInput_Length/n3g
AND2 U5/RegisterInput_Length/n3l
AND2 U5/RegisterInput_Length/n3n
AND2 U5/RegisterInput_Length/n3p
AND2 U5/RegisterInput_Length/n3r
AND2 U5/RegisterInput_Length/n3t
AND2 U5/RegisterInput_Length/n3v
AND2 U5/RegisterInput_Length/n3x
AND2 U5/RegisterInput_Length/n3z
AND2 U5/RegisterInput_Length/n4b
AND2 U5/RegisterInput_Length/n4d
AND2 U5/RegisterInput_Length/n4f
AND2 U5/RegisterInput_Length/n4h
AND2 U5/RegisterInput_Length/n4j
AND2 U5/RegisterInput_Length/n4l
AND2 U5/RegisterInput_Value/n0k
AND2 U5/RegisterInput_Value/n19
AND2B1 U5/RegisterInput_Value/n21
AND2 U5/RegisterOutput_Length/n124
AND2B1 U5/RegisterOutput_Length/n126
AND2 U5/RegisterOutput_Length/n130
AND2B1 U5/RegisterOutput_Length/n132
AND2 U5/RegisterOutput_Length/n134
AND2B1 U5/RegisterOutput_Length/n136
AND2 U5/RegisterOutput_Length/n138
AND2B1 U5/RegisterOutput_Length/n140
AND2 U5/RegisterOutput_Length/n142
AND2B1 U5/RegisterOutput_Length/n144
AND2 U5/RegisterOutput_Length/n146
AND2B1 U5/RegisterOutput_Length/n148
AND2 U5/RegisterOutput_Length/n150
AND2B1 U5/RegisterOutput_Length/n152
AND2 U5/RegisterOutput_Length/n154
AND2B1 U5/RegisterOutput_Length/n156
AND2 U5/RegisterOutput_Length/n158
AND2B1 U5/RegisterOutput_Length/n160
AND2 U5/RegisterOutput_Length/n162
AND2B1 U5/RegisterOutput_Length/n164
AND2 U5/RegisterOutput_Length/n166
AND2B1 U5/RegisterOutput_Length/n168
AND2 U5/RegisterOutput_Length/n170
AND2B1 U5/RegisterOutput_Length/n172
AND2 U5/RegisterOutput_Length/n174
AND2B1 U5/RegisterOutput_Length/n176
AND2 U5/RegisterOutput_Length/n178
AND2B1 U5/RegisterOutput_Length/n180
AND2 U5/RegisterOutput_Length/n182
AND2B1 U5/RegisterOutput_Length/n184
AND2 U5/RegisterOutput_Length/n186
AND2B1 U5/RegisterOutput_Length/n188
AND2 U5/RegisterOutput_Length/n3g
AND2 U5/RegisterOutput_Length/n3j
AND2 U5/RegisterOutput_Length/n3l
AND2 U5/RegisterOutput_Length/n3n
AND2 U5/RegisterOutput_Length/n3r
AND2 U5/RegisterOutput_Length/n3t
AND2 U5/RegisterOutput_Length/n3v
AND2 U5/RegisterOutput_Length/n3x
AND2 U5/RegisterOutput_Length/n3z
AND2 U5/RegisterOutput_Length/n4b
AND2 U5/RegisterOutput_Length/n4d
AND2 U5/RegisterOutput_Length/n4f
AND2 U5/RegisterOutput_Length/n4h
AND2 U5/RegisterOutput_Length/n4j
AND2 U5/RegisterOutput_Length/n4l
AND2B1 U5/RegisterOutput_Value/n100
AND2B1 U5/RegisterOutput_Value/n70
AND2B1 U5/RegisterOutput_Value/n76
AND2 U5/RegisterOutput_Value/n78
AND2 U5/RegisterOutput_Value/n82
AND2B1 U5/RegisterOutput_Value/n88
AND2 U5/RegisterOutput_Value/n90
AND2 U5/RegisterOutput_Value/n94
AND2 U5/TAP1/id_reg_unit/n1k
AND2 U5/TAP1/id_reg_unit/n1q
AND2 U5/TAP1/id_reg_unit/n1s
AND2 U5/TAP1/id_reg_unit/n2a
AND2 U5/TAP1/id_reg_unit/n2c
AND2 U5/TAP1/id_reg_unit/n2e
AND2 U5/TAP1/id_reg_unit/n2i
AND2 U5/TAP1/id_reg_unit/n2k
AND2 U5/TAP1/id_reg_unit/n2o
AND2 U5/TAP1/id_reg_unit/n2s
AND2 U5/TAP1/id_reg_unit/n2y
AND2 U5/TAP1/id_reg_unit/n3a
AND2 U5/TAP1/id_reg_unit/n3c
AND2 U5/TAP1/id_reg_unit/n3e
AND2 U5/TAP1/id_reg_unit/n3g
AND2 U5/TAP1/id_reg_unit/n3i
AND2 U5/TAP1/id_reg_unit/n3k
AND2 U5/TAP1/id_reg_unit/n3m
AND2 U5/TAP1/id_reg_unit/n3o
AND2 U5/TAP1/id_reg_unit/n3s
AND2 U5/TAP1/id_reg_unit/n3u
VCC U5/TAP1/n4a
INV U5/TAP1/trst_not
INV U5/TRST_not
AND2B1 U5/control_register/n100
AND2 U5/control_register/n68
AND2B1 U5/control_register/n70
AND2 U5/control_register/n74
AND2B1 U5/control_register/n76
AND2 U5/control_register/n78
AND2B1 U5/control_register/n80
AND2 U5/control_register/n82
AND2B1 U5/control_register/n84
AND2 U5/control_register/n86
AND2B1 U5/control_register/n88
AND2 U5/control_register/n90
AND2B1 U5/control_register/n92
AND2 U5/control_register/n94
AND2B1 U5/control_register/n96
AND2 U5/control_register/n98
GND U5/n13i
VCC U5/n13j
GND n2h
VCC n2i
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| CLK_BRD | IOB | INPUT | LVCMOS25 | | | | | | |
| HA2 | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF1 | | |
| HA8 | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| JTAG_NEXUS_TCK | IOB | INPUT | LVCMOS25 | | | | | | |
| JTAG_NEXUS_TDI | IOB | INPUT | LVCMOS25 | | | | INFF1 | | IFD |
| JTAG_NEXUS_TDO | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| JTAG_NEXUS_TMS | IOB | INPUT | LVCMOS25 | | | | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
This design was not run using timing mode.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
No control set information for this architecture.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.