INFILE=C:\Users\Altium7\Documents\csaadVandamme\FPGA_projet\ProjectOutputs\Default - All Constraints\fpga_projet.ncd
OUTFILE=C:\Users\Altium7\Documents\csaadVandamme\FPGA_projet\ProjectOutputs\Default - All Constraints\fpga_projet_cclk.bit
FAMILY=Spartan3
PART=xc3s1500-4fg676
WORKINGDIR=C:\Users\Altium7\Documents\csaadVandamme\FPGA_projet\ProjectOutputs\Default - All Constraints
LICENSE=WebPack
USER_INFO=210736258_0_0_233