fpga_projet.unroutes
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Release 14.3 - par P.40xd (nt64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Wed May 17 18:19:30 2017
All signals are completely routed.
WARNING:ParHelpers:361 - There are 69 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
U3/TDO_ENABLE
U5/RegisterConfiguration/regout_0
U5/RegisterConfiguration/regout_1
U5/RegisterConfiguration/regout_10
U5/RegisterConfiguration/regout_11
U5/RegisterConfiguration/regout_12
U5/RegisterConfiguration/regout_13
U5/RegisterConfiguration/regout_14
U5/RegisterConfiguration/regout_15
U5/RegisterConfiguration/regout_16
U5/RegisterConfiguration/regout_17
U5/RegisterConfiguration/regout_18
U5/RegisterConfiguration/regout_19
U5/RegisterConfiguration/regout_2
U5/RegisterConfiguration/regout_20
U5/RegisterConfiguration/regout_21
U5/RegisterConfiguration/regout_22
U5/RegisterConfiguration/regout_23
U5/RegisterConfiguration/regout_24
U5/RegisterConfiguration/regout_25
U5/RegisterConfiguration/regout_26
U5/RegisterConfiguration/regout_27
U5/RegisterConfiguration/regout_28
U5/RegisterConfiguration/regout_29
U5/RegisterConfiguration/regout_3
U5/RegisterConfiguration/regout_30
U5/RegisterConfiguration/regout_31
U5/RegisterConfiguration/regout_4
U5/RegisterConfiguration/regout_5
U5/RegisterConfiguration/regout_6
U5/RegisterConfiguration/regout_7
U5/RegisterConfiguration/regout_8
U5/RegisterConfiguration/regout_9
U5/RegisterInput_Length/regout_0
U5/RegisterInput_Length/regout_1
U5/RegisterInput_Length/regout_10
U5/RegisterInput_Length/regout_11
U5/RegisterInput_Length/regout_12
U5/RegisterInput_Length/regout_13
U5/RegisterInput_Length/regout_14
U5/RegisterInput_Length/regout_15
U5/RegisterInput_Length/regout_2
U5/RegisterInput_Length/regout_3
U5/RegisterInput_Length/regout_4
U5/RegisterInput_Length/regout_5
U5/RegisterInput_Length/regout_6
U5/RegisterInput_Length/regout_7
U5/RegisterInput_Length/regout_8
U5/RegisterInput_Length/regout_9
U5/RegisterInput_Value/regout_0
U5/RegisterOutput_Length/regout_0
U5/RegisterOutput_Length/regout_1
U5/RegisterOutput_Length/regout_10
U5/RegisterOutput_Length/regout_11
U5/RegisterOutput_Length/regout_12
U5/RegisterOutput_Length/regout_13
U5/RegisterOutput_Length/regout_14
U5/RegisterOutput_Length/regout_15
U5/RegisterOutput_Length/regout_2
U5/RegisterOutput_Length/regout_3
U5/RegisterOutput_Length/regout_4
U5/RegisterOutput_Length/regout_5
U5/RegisterOutput_Length/regout_6
U5/RegisterOutput_Length/regout_7
U5/RegisterOutput_Length/regout_8
U5/RegisterOutput_Length/regout_9
U5/TAP1/exit1dr
U5/TAP1/reset
U7/CEO