.model Configurable_U1
.inputs D<7>
.inputs D<6>
.inputs D<5>
.inputs D<4>
.inputs D<3>
.inputs D<2>
.inputs D<1>
.inputs D<0>
.inputs C
.outputs PWM
.names n1
.names n2
1
.names D<0> D<1> reduce_nor_4/n1
1- 1
-1 1
.names n6 n7
0 1
.names n72 n70
0 1
.names n4 n5 n6
1- 1
-1 1
.names I<0> n2 n72
01 1
10 1
.subckt MUXCY i56 CI=-i56/CI DI=-i56/DI S=-i56/S O=+n55
.names n1 i56/CI
1 1
.names I<0> i56/DI
1 1
.names n54 i56/S
1 1
.loc Configurable_U1.VHD 39 I<7>
.latch n10 I<7> re C 0 n48
.loc Configurable_U1.VHD 39 I<6>
.latch n11 I<6> re C 0 n48
.loc Configurable_U1.VHD 39 I<5>
.latch n12 I<5> re C 0 n48
.loc Configurable_U1.VHD 39 I<4>
.latch n13 I<4> re C 0 n48
.loc Configurable_U1.VHD 39 I<3>
.latch n14 I<3> re C 0 n48
.loc Configurable_U1.VHD 39 I<2>
.latch n15 I<2> re C 0 n48
.loc Configurable_U1.VHD 39 I<1>
.latch n16 I<1> re C 0 n48
.loc Configurable_U1.VHD 39 I<0>
.latch n72 I<0> re C 0 n48
.names D<2> D<3> reduce_nor_4/n2
1- 1
-1 1
.names D<0> I<0> n54
11 1
00 1
.names reduce_nor_4/n3 reduce_nor_4/n6 reduce_nor_4/n7
1- 1
-1 1
.names reduce_nor_4/n4 reduce_nor_4/n5 reduce_nor_4/n6
1- 1
-1 1
.names D<6> D<7> reduce_nor_4/n5
1- 1
-1 1
.names D<4> D<5> reduce_nor_4/n4
1- 1
-1 1
.names reduce_nor_4/n1 reduce_nor_4/n2 reduce_nor_4/n3
1- 1
-1 1
.loc Configurable_U1.VHD 39 PWM
.latch n7 PWM re C 2
.names reduce_nor_4/n7 n5
0 1
.names n2 I<1> LessThan_7/n3
01 1
10 1
.names I<1> LessThan_7/n3 LessThan_7/n2 LessThan_7/n4
11- 1
-01 1
.names n2 I<2> LessThan_7/n5
01 1
10 1
.names I<2> LessThan_7/n5 LessThan_7/n4 LessThan_7/n6
11- 1
-01 1
.names n2 I<3> LessThan_7/n7
01 1
10 1
.names I<3> LessThan_7/n7 LessThan_7/n6 LessThan_7/n8
11- 1
-01 1
.names n2 I<4> LessThan_7/n9
01 1
10 1
.names I<4> LessThan_7/n9 LessThan_7/n8 LessThan_7/n10
11- 1
-01 1
.names n2 I<5> LessThan_7/n11
01 1
10 1
.names I<5> LessThan_7/n11 LessThan_7/n10 LessThan_7/n12
11- 1
-01 1
.names n2 I<6> LessThan_7/n13
01 1
10 1
.names I<6> LessThan_7/n13 LessThan_7/n12 LessThan_7/n14
11- 1
-01 1
.names n2 I<7> LessThan_7/n15
01 1
10 1
.names I<7> LessThan_7/n15 LessThan_7/n14 n48
11- 1
-01 1
.names I<0> n70 add_8/n2
11 1
.names D<1> I<1> n56
11 1
00 1
.subckt MUXCY i58 CI=-i58/CI DI=-i58/DI S=-i58/S O=+n57
.names n55 i58/CI
1 1
.names I<1> i58/DI
1 1
.names n56 i58/S
1 1
.names D<2> I<2> n58
11 1
00 1
.subckt MUXCY i60 CI=-i60/CI DI=-i60/DI S=-i60/S O=+n59
.names n57 i60/CI
1 1
.names I<2> i60/DI
1 1
.names n58 i60/S
1 1
.names D<3> I<3> n60
11 1
00 1
.subckt MUXCY i62 CI=-i62/CI DI=-i62/DI S=-i62/S O=+n61
.names n59 i62/CI
1 1
.names I<3> i62/DI
1 1
.names n60 i62/S
1 1
.names D<4> I<4> n62
11 1
00 1
.subckt MUXCY i64 CI=-i64/CI DI=-i64/DI S=-i64/S O=+n63
.names n61 i64/CI
1 1
.names I<4> i64/DI
1 1
.names n62 i64/S
1 1
.names D<5> I<5> n64
11 1
00 1
.subckt MUXCY i66 CI=-i66/CI DI=-i66/DI S=-i66/S O=+n65
.names n63 i66/CI
1 1
.names I<5> i66/DI
1 1
.names n64 i66/S
1 1
.names D<6> I<6> n66
11 1
00 1
.subckt MUXCY i68 CI=-i68/CI DI=-i68/DI S=-i68/S O=+n67
.names n65 i68/CI
1 1
.names I<6> i68/DI
1 1
.names n66 i68/S
1 1
.names D<7> I<7> n68
11 1
00 1
.subckt MUXCY i70 CI=-i70/CI DI=-i70/DI S=-i70/S O=+n4
.names n67 i70/CI
1 1
.names I<7> i70/DI
1 1
.names n68 i70/S
1 1
.names I<0> n70 LessThan_7/n2
1- 1
-1 1
.loc Configurable_U1.VHD 37
.subckt MUXCY i77 CI=-i77/CI DI=-i77/DI S=-i77/S O=+add_8/n4
.names add_8/n2 i77/CI
1 1
.names I<1> i77/DI
1 1
.names I<1> i77/S
1 1
.loc Configurable_U1.VHD 37
.subckt XORCY i78 CI=-i78/CI LI=-i78/LI O=+n16
.names add_8/n2 i78/CI
1 1
.names I<1> i78/LI
1 1
.loc Configurable_U1.VHD 37
.subckt MUXCY i80 CI=-i80/CI DI=-i80/DI S=-i80/S O=+add_8/n6
.names add_8/n4 i80/CI
1 1
.names I<2> i80/DI
1 1
.names I<2> i80/S
1 1
.loc Configurable_U1.VHD 37
.subckt XORCY i81 CI=-i81/CI LI=-i81/LI O=+n15
.names add_8/n4 i81/CI
1 1
.names I<2> i81/LI
1 1
.loc Configurable_U1.VHD 37
.subckt MUXCY i83 CI=-i83/CI DI=-i83/DI S=-i83/S O=+add_8/n8
.names add_8/n6 i83/CI
1 1
.names I<3> i83/DI
1 1
.names I<3> i83/S
1 1
.loc Configurable_U1.VHD 37
.subckt XORCY i84 CI=-i84/CI LI=-i84/LI O=+n14
.names add_8/n6 i84/CI
1 1
.names I<3> i84/LI
1 1
.loc Configurable_U1.VHD 37
.subckt MUXCY i86 CI=-i86/CI DI=-i86/DI S=-i86/S O=+add_8/n10
.names add_8/n8 i86/CI
1 1
.names I<4> i86/DI
1 1
.names I<4> i86/S
1 1
.loc Configurable_U1.VHD 37
.subckt XORCY i87 CI=-i87/CI LI=-i87/LI O=+n13
.names add_8/n8 i87/CI
1 1
.names I<4> i87/LI
1 1
.loc Configurable_U1.VHD 37
.subckt MUXCY i89 CI=-i89/CI DI=-i89/DI S=-i89/S O=+add_8/n12
.names add_8/n10 i89/CI
1 1
.names I<5> i89/DI
1 1
.names I<5> i89/S
1 1
.loc Configurable_U1.VHD 37
.subckt XORCY i90 CI=-i90/CI LI=-i90/LI O=+n12
.names add_8/n10 i90/CI
1 1
.names I<5> i90/LI
1 1
.loc Configurable_U1.VHD 37
.subckt MUXCY i92 CI=-i92/CI DI=-i92/DI S=-i92/S O=+add_8/n14
.names add_8/n12 i92/CI
1 1
.names I<6> i92/DI
1 1
.names I<6> i92/S
1 1
.loc Configurable_U1.VHD 37
.subckt XORCY i93 CI=-i93/CI LI=-i93/LI O=+n11
.names add_8/n12 i93/CI
1 1
.names I<6> i93/LI
1 1
.loc Configurable_U1.VHD 37
.subckt XORCY i95 CI=-i95/CI LI=-i95/LI O=+n10
.names add_8/n14 i95/CI
1 1
.names I<7> i95/LI
1 1