FPGA_projet.ucf 242 Bytes Edit Raw Blame History 1 2 3 4 5 6 7 8 NET "JTAG_NEXUS_TMS" LOC=P19; NET "JTAG_NEXUS_TDO" LOC=B23; NET "JTAG_NEXUS_TDI" LOC=R21; NET "JTAG_NEXUS_TCK" LOC=P21; NET "JTAG_NEXUS_TCK" CLOCK_DEDICATED_ROUTE = FALSE; NET "HA8" LOC=AB3; NET "HA2" LOC=AE4; NET "CLK_BRD" LOC=AE14;