Commit 2997ffb95ad192bfd424f72440fc0acbf8c7a012
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6591a8e7
Peut affecter des valeurs à des tableaux (RAM)
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@@ -0,0 +1,61 @@ | @@ -0,0 +1,61 @@ | ||
1 | +.equ PINA = 0x00 ; définition des adresses des ports | ||
2 | +.equ DDRA = 0x01 | ||
3 | +.equ PORTA = 0x02 | ||
4 | +.equ PINC = 0x06 | ||
5 | +.equ DDRC = 0x07 | ||
6 | +.equ PORTC = 0x08 | ||
7 | + | ||
8 | +.equ TEST = 0x0200 | ||
9 | + | ||
10 | +.equ RAMEND = 0x21FF | ||
11 | +.equ SPH = 0x3E ; initialisation de la pile | ||
12 | +.equ SPL = 0x3D | ||
13 | + | ||
14 | +.org 0x000 | ||
15 | + ; Vecteur RESET | ||
16 | + jmp debut | ||
17 | + | ||
18 | + | ||
19 | +.org 0x0080 | ||
20 | + | ||
21 | + | ||
22 | +debut: | ||
23 | + DDRA@IO <- 0xFF | ||
24 | + DDRC@IO <- 0xFF | ||
25 | + PORTC@IO <- 0x00 | ||
26 | + PORTA@IO <- 0x00 | ||
27 | + r11 <- 0x00 | ||
28 | + r10 <- 0x00 | ||
29 | + | ||
30 | +boucle: | ||
31 | + | ||
32 | + test[2] <- 0x22 | ||
33 | + PORTA@IO <- test[2] | ||
34 | + | ||
35 | + jmp sl | ||
36 | + ; test <- 0x22 | ||
37 | + | ||
38 | + LDI r16,0xAA | ||
39 | + | ||
40 | + LDI r26,0x02 | ||
41 | + LDI r27,0x00 | ||
42 | + | ||
43 | + ST X,r16 | ||
44 | + | ||
45 | + LD r10,X | ||
46 | + | ||
47 | + ;PORTA@IO <- test[1] | ||
48 | + | ||
49 | +sl: | ||
50 | + sleep | ||
51 | + saut sl | ||
52 | + | ||
53 | +tempo: | ||
54 | + ldi r24,8 | ||
55 | +tempoA: | ||
56 | + subi r22,1 | ||
57 | + sbci r23,0 | ||
58 | + sbci r24,0 | ||
59 | + brcc tempoA | ||
60 | + ret | ||
61 | + |
scripts/gram.txt
@@ -48,6 +48,14 @@ eti{NUM0}: | @@ -48,6 +48,14 @@ eti{NUM0}: | ||
48 | [blanc]* [VariableIO]:var [blanc]* [SymboleAffectation] [blanc]* [Expression]:exp [blanc]* [fin] | 48 | [blanc]* [VariableIO]:var [blanc]* [SymboleAffectation] [blanc]* [Expression]:exp [blanc]* [fin] |
49 | {exp} OUT {var},R16 | 49 | {exp} OUT {var},R16 |
50 | 50 | ||
51 | +[blanc]* [Tableau]:var [Expression]:ind [blanc]* "]" [blanc]* [SymboleAffectation] [blanc]* [Expression]:exp [blanc]* [fin] | ||
52 | +{ind} LDI R26,low({var}) | ||
53 | + LDI R27,high({var}) | ||
54 | + CLR R17 | ||
55 | + ADD R26,R16 | ||
56 | + ADC R27,R17 | ||
57 | +{exp} ST X,R16 | ||
58 | + | ||
51 | [blanc]* [Variable]:var [blanc]* [SymboleAffectation] [blanc]* [Expression]:exp [blanc]* [fin] | 59 | [blanc]* [Variable]:var [blanc]* [SymboleAffectation] [blanc]* [Expression]:exp [blanc]* [fin] |
52 | {exp} STS {var},R16 | 60 | {exp} STS {var},R16 |
53 | 61 |