periph_conf.h
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/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nucleo144-f722
* @{
*
* @file
* @brief Peripheral MCU configuration for the nucleo144-f722 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 216MHz */
#define CLOCK_CORECLOCK (216000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (216)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (9)
/** @} */
/**
* @name Timer configuration
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = TIM2,
.max = 0xffffffff,
.rcc_mask = RCC_APB1ENR_TIM2EN,
.bus = APB1,
.irqn = TIM2_IRQn
}
};
#define TIMER_0_ISR isr_tim2
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = USART3,
.rcc_mask = RCC_APB1ENR_USART3EN,
.rx_pin = GPIO_PIN(PORT_D, 9),
.tx_pin = GPIO_PIN(PORT_D, 8),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB1,
.irqn = USART3_IRQn,
#ifdef UART_USE_DMA
.dma_stream = 6,
.dma_chan = 4
#endif
},
{
.dev = USART6,
.rcc_mask = RCC_APB2ENR_USART6EN,
.rx_pin = GPIO_PIN(PORT_G, 9),
.tx_pin = GPIO_PIN(PORT_G, 14),
.rx_af = GPIO_AF8,
.tx_af = GPIO_AF8,
.bus = APB2,
.irqn = USART6_IRQn,
#ifdef UART_USE_DMA
.dma_stream = 5,
.dma_chan = 4
#endif
},
{
.dev = USART2,
.rcc_mask = RCC_APB1ENR_USART2EN,
.rx_pin = GPIO_PIN(PORT_D, 6),
.tx_pin = GPIO_PIN(PORT_D, 5),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB1,
.irqn = USART2_IRQn,
#ifdef UART_USE_DMA
.dma_stream = 4,
.dma_chan = 4
#endif
}
};
#define UART_0_ISR (isr_usart3)
#define UART_0_DMA_ISR (isr_dma1_stream6)
#define UART_1_ISR (isr_usart6)
#define UART_1_DMA_ISR (isr_dma1_stream5)
#define UART_2_ISR (isr_usart2)
#define UART_2_DMA_ISR (isr_dma1_stream4)
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */
/**
* @name ADC configuration
* @{
*/
#define ADC_NUMOF (0)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */