Blame view

RIOT/boards/mulle/include/board.h 4.87 KB
a752c7ab   elopes   add first test an...
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
  /*
   * Copyright (C) 2014 Eistec AB
   *
   * This file is subject to the terms and conditions of the GNU Lesser General
   * Public License v2.1. See the file LICENSE in the top level directory for more
   * details.
   */
  
  /**
   * @defgroup    boards_mulle Eistec Mulle
   * @ingroup     boards
   * @brief       Board specific files for Eistec Mulle IoT boards
   * @{
   *
   * @file
   * @brief       Board specific definitions for the Eistec Mulle IoT board
   *
   * @author      Joakim Nohlgård <joakim.nohlgard@eistec.se>
   */
  
  #ifndef BOARD_H
  #define BOARD_H
  
  #include "cpu.h"
  #include "periph_conf.h"
  #include "mulle-nvram.h"
  #include "mtd.h"
  
  /* Use the on board RTC 32kHz clock for LPTMR clocking. */
  #undef LPTIMER_CLKSRC
  /** @brief Clock source for the LPTMR module */
  #define LPTIMER_CLKSRC LPTIMER_CLKSRC_ERCLK32K
  
  /** Disable hardware watchdog, for debugging purposes, don't use this on production builds. */
  #define DISABLE_WDOG    1
  
  /**
   * @brief Use the UART1 for STDIO on this board
   */
  #define UART_STDIO_DEV      UART_DEV(1)
  
  /**
   * @brief   xtimer configuration
   * @{
   */
  #if 0
  /* LPTMR xtimer configuration */
  /* WIP, Use PIT for now */
  #define XTIMER_DEV                  (TIMER_LPTMR_DEV(0))
  /* LPTMR is 16 bits wide */
  #define XTIMER_WIDTH                (16)
  #define XTIMER_BACKOFF              (4)
  #define XTIMER_ISR_BACKOFF          (4)
  #define XTIMER_OVERHEAD             (3)
  #define XTIMER_HZ                   (32768ul)
  #else
  /* PIT xtimer configuration */
  #define XTIMER_DEV                  (TIMER_PIT_DEV(0))
  #define XTIMER_CHAN                 (0)
  #define XTIMER_BACKOFF              (40)
  #define XTIMER_ISR_BACKOFF          (40)
  #define XTIMER_OVERHEAD             (30)
  #endif
  /** @} */
  
  /**
   * @brief   LED pin definitions and handlers
   * @{
   */
  #define LED_PORT            PTC
  #define LED0_BIT            (15)
  #define LED1_BIT            (14)
  #define LED2_BIT            (13)
  
  #define LED0_PIN            GPIO_PIN(PORT_C, LED0_BIT)
  #define LED1_PIN            GPIO_PIN(PORT_C, LED1_BIT)
  #define LED2_PIN            GPIO_PIN(PORT_C, LED2_BIT)
  
  #define LED0_ON             (LED_PORT->PSOR = (1 << LED0_BIT))
  #define LED0_OFF            (LED_PORT->PCOR = (1 << LED0_BIT))
  #define LED0_TOGGLE         (LED_PORT->PTOR = (1 << LED0_BIT))
  
  #define LED1_ON             (LED_PORT->PSOR = (1 << LED1_BIT))
  #define LED1_OFF            (LED_PORT->PCOR = (1 << LED1_BIT))
  #define LED1_TOGGLE         (LED_PORT->PTOR = (1 << LED1_BIT))
  
  #define LED2_ON             (LED_PORT->PSOR = (1 << LED2_BIT))
  #define LED2_OFF            (LED_PORT->PCOR = (1 << LED2_BIT))
  #define LED2_TOGGLE         (LED_PORT->PTOR = (1 << LED2_BIT))
  /** @} */
  
  #ifdef __cplusplus
  extern "C" {
  #endif
  
  /**
   * @brief Initialize board specific hardware, including clock, LEDs and std-IO
   */
  void board_init(void);
  
  #ifdef __cplusplus
  }
  #endif
  
  /**
   * @name Define the interface to the AT86RF212B radio
   *
   * @todo Work around missing RESET pin on Mulle v0.6x
   *
   * {spi bus, spi speed, cs pin, int pin, reset pin, sleep pin}
   */
  #define AT86RF2XX_PARAMS_BOARD      {.spi = SPI_DEV(0), \
                                       .spi_clk = SPI_CLK_5MHZ, \
                                       .cs_pin = SPI_HWCS(1), \
                                       .int_pin = GPIO_PIN(PORT_B, 9), \
                                       .sleep_pin = GPIO_PIN(PORT_E, 6), \
                                       .reset_pin = GPIO_PIN(PORT_C, 12)}
  
  
  /**
   * @name LIS3DH configuration
   * @{
   */
  #define LIS3DH_INT1                 GPIO_PIN(PORT_C, 18)
  #define LIS3DH_INT2                 GPIO_PIN(PORT_C, 17)
  #define LIS3DH_CS                   SPI_HWCS(0)
  #define LIS3DH_CLK                  SPI_CLK_5MHZ
  #define LIS3DH_SPI                  SPI_DEV(0)
  /** @} */
  
  /**
   * @name Mulle power control configuration
   */
  /** @{ */
  #define MULLE_POWER_AVDD        GPIO_PIN(PORT_B, 17) /**< AVDD enable pin */
  #define MULLE_POWER_VPERIPH     GPIO_PIN(PORT_D,  7) /**< VPERIPH enable pin */
  #define MULLE_POWER_VSEC        GPIO_PIN(PORT_B, 16) /**< VSEC enable pin */
  /** @} */
  
  /**
   * @name Mulle NVRAM hardware configuration
   */
  /** @{ */
  #define MULLE_NVRAM_SPI_DEV             SPI_DEV(0)
  #define MULLE_NVRAM_SPI_CLK             SPI_CLK_5MHZ
  #define MULLE_NVRAM_SPI_CS              SPI_HWCS(3) /**< FRAM CS pin */
  #define MULLE_NVRAM_CAPACITY            512     /**< FRAM size, in bytes */
  #define MULLE_NVRAM_SPI_ADDRESS_COUNT   1       /**< FRAM addressing size, in bytes */
  /** @} */
  
  /**
   * @name Mulle NOR flash hardware configuration
   */
  /** @{ */
  #define MULLE_NOR_SPI_DEV               SPI_DEV(0)
  #define MULLE_NOR_SPI_CLK               SPI_CLK_5MHZ
  #define MULLE_NOR_SPI_CS                SPI_HWCS(2) /**< Flash CS pin */
  /** @} */
  /**
   * @name MTD configuration
   */
  /** @{ */
  extern mtd_dev_t *mtd0;
  #define MTD_0 mtd0
  /** @} */
  
  /**
   * @name Mulle Vchr, Vbat ADC lines
   */
  /** @{ */
  #define MULLE_VBAT_ADC_LINE           ADC_LINE(6)
  #define MULLE_VCHR_ADC_LINE           ADC_LINE(7)
  /** @} */
  #endif /* BOARD_H */
  /** @} */