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-- Company: 
-- Engineer: 
-- 
-- Create Date: 27.09.2023 17:03:49
-- Design Name: 
-- Module Name: display - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity display is
     port (
     clk_fpga : in STD_LOGIC;
     reset : in STD_LOGIC;
     aff : out STD_LOGIC_VECTOR(7 downto 0);
     an : out STD_LOGIC_VECTOR(3 downto 0)
     );
end display;

architecture Behavioral of display is

signal count_an : integer range 3 downto 0 := 0;
signal clk_enable : integer range 4999 downto 0 := 0;
signal clk_counter : integer range 2999999 downto 0 := 0;
constant nb0 : std_logic_vector(7 downto 0) := "11000000";
constant nb1 : std_logic_vector(7 downto 0) := "11111001";
constant nb2 : std_logic_vector(7 downto 0) := "10100100";
constant nb3 : std_logic_vector(7 downto 0) := "10110000";
constant nb4 : std_logic_vector(7 downto 0) := "10011001";
constant nb5 : std_logic_vector(7 downto 0) := "10010010";
constant nb6 : std_logic_vector(7 downto 0) := "10000010";
constant nb7 : std_logic_vector(7 downto 0) := "11111000";
constant nb8 : std_logic_vector(7 downto 0) := "10000000";
constant nb9 : std_logic_vector(7 downto 0) := "10010000";
constant seg0 : std_logic_vector(3 downto 0) := "1110";
constant seg1 : std_logic_vector(3 downto 0) := "1101";
constant seg2 : std_logic_vector(3 downto 0) := "1011";
constant seg3 : std_logic_vector(3 downto 0) := "0111";
signal chiffre4 : integer range 9 downto 0 := 0;
signal chiffre3 : integer range 9 downto 0 := 0;
signal chiffre2 : integer range 9 downto 0 := 0;
signal chiffre1 : integer range 9 downto 0 := 0;

type mynumbers is array(9 downto 0) of std_logic_vector(7 downto 0);
signal numbers : mynumbers := (nb9,nb8,nb7,nb6,nb5,nb4,nb3,nb2,nb1,nb0);

begin

-- display process
process(clk_fpga)
begin
    if clk_fpga'event and clk_fpga = '1' then
        if clk_enable = 4999 then
            clk_enable <= 0;
            if count_an = 0 then
                aff <= numbers(chiffre4); 
                an <= seg0;
                count_an <= count_an + 1;
            elsif count_an = 1 then
                aff <= numbers(chiffre3); 
                an <= seg1;
                count_an <= count_an + 1;
            elsif count_an = 2 then
                aff <= numbers(chiffre2);
                an <= seg2;       
                count_an <= count_an + 1;
            elsif count_an = 3 then 
                aff <= numbers(chiffre1);
                an <= seg3;
                count_an <= 0;
            end if;
        else
            clk_enable <= clk_enable + 1;
        end if;   
    end if;    
end process; 

-- process counter
process(clk_fpga)
begin
    if clk_fpga'event and clk_fpga = '1' then
        if clk_counter = 2999999 then 
            clk_counter <= 0; 
            if reset = '1' then 
                chiffre1 <= 0;
                chiffre2 <= 0;
                chiffre3 <= 0;
                chiffre4 <= 0;
            else if chiffre4 = 9 then
                chiffre4 <= 0; 
                if chiffre3 = 9 then 
                    chiffre3 <= 0;
                    if chiffre2 = 9 then 
                        chiffre2 <= 0;
                           if chiffre1 = 9 then 
                                chiffre1 <= 0;
                            else 
                            chiffre1 <= chiffre1 + 1;
                            end if;
                    else 
                        chiffre2 <= chiffre2 + 1;
                    end if;
                else 
                    chiffre3 <= chiffre3 + 1;
                end if;
            else 
                chiffre4 <= chiffre4 + 1;
            end if;
        else 
            clk_counter <= clk_counter + 1;
        end if;
    end if;
end process;
end Behavioral;