//***************************************************************************** // // hw_hibernate.h - Defines and Macros for the Hibernation module. // // Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // This is part of revision 9453 of the Stellaris Firmware Development Package. // //***************************************************************************** #ifndef STELLARIS_HW_HIBERNATE_H_ #define STELLARIS_HW_HIBERNATE_H_ #ifdef __cplusplus extern "C" { #endif //***************************************************************************** // // The following are defines for the Hibernation module register addresses. // //***************************************************************************** #define HIB_RTCC 0x400FC000 // Hibernation RTC Counter #define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0 #define HIB_RTCM1 0x400FC008 // Hibernation RTC Match 1 #define HIB_RTCLD 0x400FC00C // Hibernation RTC Load #define HIB_CTL 0x400FC010 // Hibernation Control #define HIB_IM 0x400FC014 // Hibernation Interrupt Mask #define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status #define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt // Status #define HIB_IC 0x400FC020 // Hibernation Interrupt Clear #define HIB_RTCT 0x400FC024 // Hibernation RTC Trim #define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds #define HIB_DATA 0x400FC030 // Hibernation Data //***************************************************************************** // // The following are defines for the bit fields in the HIB_RTCC register. // //***************************************************************************** #define HIB_RTCC_M 0xFFFFFFFF // RTC Counter #define HIB_RTCC_S 0 //***************************************************************************** // // The following are defines for the bit fields in the HIB_RTCM0 register. // //***************************************************************************** #define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0 #define HIB_RTCM0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the HIB_RTCM1 register. // //***************************************************************************** #define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1 #define HIB_RTCM1_S 0 //***************************************************************************** // // The following are defines for the bit fields in the HIB_RTCLD register. // //***************************************************************************** #define HIB_RTCLD_M 0xFFFFFFFF // RTC Load #define HIB_RTCLD_S 0 //***************************************************************************** // // The following are defines for the bit fields in the HIB_CTL register. // //***************************************************************************** #define HIB_CTL_WRC 0x80000000 // Write Complete/Capable #define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability #define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass #define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery // Comparator #define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts #define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default) #define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts #define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts #define HIB_CTL_BATCHK 0x00000400 // Check Battery Status #define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery #define HIB_CTL_VDD3ON 0x00000100 // VDD Powered #define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable #define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable #define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable #define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable #define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable #define HIB_CTL_CLKSEL 0x00000004 // Hibernation Module Clock Select #define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request #define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable //***************************************************************************** // // The following are defines for the bit fields in the HIB_IM register. // //***************************************************************************** #define HIB_IM_WC 0x00000010 // External Write Complete/Capable // Interrupt Mask #define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask #define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt // Mask #define HIB_IM_RTCALT1 0x00000002 // RTC Alert 1 Interrupt Mask #define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask //***************************************************************************** // // The following are defines for the bit fields in the HIB_RIS register. // //***************************************************************************** #define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw // Interrupt Status #define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt // Status #define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw // Interrupt Status #define HIB_RIS_RTCALT1 0x00000002 // RTC Alert 1 Raw Interrupt Status #define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status //***************************************************************************** // // The following are defines for the bit fields in the HIB_MIS register. // //***************************************************************************** #define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked // Interrupt Status #define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked // Interrupt Status #define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked // Interrupt Status #define HIB_MIS_RTCALT1 0x00000002 // RTC Alert 1 Masked Interrupt // Status #define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt // Status //***************************************************************************** // // The following are defines for the bit fields in the HIB_IC register. // //***************************************************************************** #define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked // Interrupt Clear #define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked // Interrupt Clear #define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked // Interrupt Clear #define HIB_IC_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt // Clear #define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt // Clear //***************************************************************************** // // The following are defines for the bit fields in the HIB_RTCT register. // //***************************************************************************** #define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value #define HIB_RTCT_TRIM_S 0 //***************************************************************************** // // The following are defines for the bit fields in the HIB_RTCSS register. // //***************************************************************************** #define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match #define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count #define HIB_RTCSS_RTCSSM_S 16 #define HIB_RTCSS_RTCSSC_S 0 //***************************************************************************** // // The following are defines for the bit fields in the HIB_DATA register. // //***************************************************************************** #define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data #define HIB_DATA_RTD_S 0 //***************************************************************************** // // The following definitions are deprecated. // //***************************************************************************** #ifndef DEPRECATED //***************************************************************************** // // The following are deprecated defines for the Hibernation module register // addresses. // //***************************************************************************** #define HIB_DATA_END 0x400FC130 // end of data area, exclusive //***************************************************************************** // // The following are deprecated defines for the bit fields in the HIB_RTCC // register. // //***************************************************************************** #define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask //***************************************************************************** // // The following are deprecated defines for the bit fields in the HIB_RTCM0 // register. // //***************************************************************************** #define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask //***************************************************************************** // // The following are deprecated defines for the bit fields in the HIB_RTCM1 // register. // //***************************************************************************** #define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask //***************************************************************************** // // The following are deprecated defines for the bit fields in the HIB_RTCLD // register. // //***************************************************************************** #define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask //***************************************************************************** // // The following are deprecated defines for the bit fields in the HIB_RIS // register. // //***************************************************************************** #define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt //***************************************************************************** // // The following are deprecated defines for the bit fields in the HIB_MIS // register. // //***************************************************************************** #define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt //***************************************************************************** // // The following are deprecated defines for the bit fields in the HIB_RTCT // register. // //***************************************************************************** #define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask //***************************************************************************** // // The following are deprecated defines for the bit fields in the HIB_DATA // register. // //***************************************************************************** #define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask #endif #ifdef __cplusplus } #endif #endif /* STELLARIS_HW_HIBERNATE_H_ */