fb11e647
vrobic
reseau statique a...
|
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
|
/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
#include <stdint.h>
#include <stddef.h>
#include "nvram.h"
#include "nvram-spi.h"
#include "byteorder.h"
#include "periph/spi.h"
#include "periph/gpio.h"
#include "xtimer.h"
/**
* @ingroup nvram
* @{
*
* @file
*
* @brief Device interface for various SPI connected NVRAM.
*
* Tested on:
* - Cypress/Ramtron FM25L04B.
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*/
typedef enum {
/** WRITE command byte, 0b0000 0010 */
NVRAM_SPI_CMD_WRITE = 0x02,
/** READ command byte, 0b0000 0011 */
NVRAM_SPI_CMD_READ = 0x03,
/** WREN command byte, 0b0000 0110 */
NVRAM_SPI_CMD_WREN = 0x06,
} nvram_spi_commands_t;
/** @brief Delay to wait between toggling CS pin, on most chips this can probably be
* removed. */
#define NVRAM_SPI_CS_TOGGLE_TICKS xtimer_ticks_from_usec(1)
/**
* @brief Copy data from system memory to NVRAM.
*
* @param[in] dev Pointer to NVRAM device descriptor
* @param[in] src Pointer to the first byte in the system memory address space
* @param[in] dst Starting address in the NVRAM device address space
* @param[in] len Number of bytes to copy
*
* @return Number of bytes written on success
* @return <0 on errors
*/
static int nvram_spi_write(nvram_t *dev, const uint8_t *src, uint32_t dst, size_t len);
/**
* @brief Copy data from NVRAM to system memory.
*
* @param[in] dev Pointer to NVRAM device descriptor
* @param[out] dst Pointer to the first byte in the system memory address space
* @param[in] src Starting address in the NVRAM device address space
* @param[in] len Number of bytes to copy
*
* @return Number of bytes read on success
* @return <0 on errors
*/
static int nvram_spi_read(nvram_t *dev, uint8_t *dst, uint32_t src, size_t len);
/**
* @brief Copy data from system memory to NVRAM.
*
* This is a special form of the WRITE command used by some Ramtron/Cypress
* 4Kbit FRAM devices which puts the 9th address bit inside the command byte to
* be able to use one byte for addressing instead of two.
*
* @param[in] dev Pointer to NVRAM device descriptor
* @param[in] src Pointer to the first byte in the system memory address space
* @param[in] dst Starting address in the NVRAM device address space
* @param[in] len Number of bytes to copy
*
* @return Number of bytes written on success
* @return <0 on errors
*/
static int nvram_spi_write_9bit_addr(nvram_t *dev, const uint8_t *src, uint32_t dst, size_t len);
/**
* @brief Copy data from NVRAM to system memory.
*
* This is a special form of the READ command used by some Ramtron/Cypress 4Kbit
* FRAM devices which puts the 9th address bit inside the command byte to be
* able to use one byte for addressing instead of two.
*
* @param[in] dev Pointer to NVRAM device descriptor
* @param[out] dst Pointer to the first byte in the system memory address space
* @param[in] src Starting address in the NVRAM device address space
* @param[in] len Number of bytes to copy
*
* @return Number of bytes read on success
* @return <0 on errors
*/
static int nvram_spi_read_9bit_addr(nvram_t *dev, uint8_t *dst, uint32_t src, size_t len);
int nvram_spi_init(nvram_t *dev, nvram_spi_params_t *spi_params, size_t size)
{
dev->size = size;
if (size > 0x100 && spi_params->address_count == 1) {
dev->write = nvram_spi_write_9bit_addr;
dev->read = nvram_spi_read_9bit_addr;
} else {
dev->write = nvram_spi_write;
dev->read = nvram_spi_read;
}
dev->extra = spi_params;
gpio_init(spi_params->cs, GPIO_OUT);
gpio_set(spi_params->cs);
return 0;
}
static int nvram_spi_write(nvram_t *dev, const uint8_t *src, uint32_t dst, size_t len)
{
nvram_spi_params_t *spi_dev = (nvram_spi_params_t *) dev->extra;
int status;
union {
uint32_t u32;
char c[4];
} addr;
/* Address is expected by the device as big-endian, i.e. network byte order,
* we utilize the network byte order macros here. */
addr.u32 = HTONL(dst);
/* Acquire exclusive bus access */
spi_acquire(spi_dev->spi);
/* Assert CS */
gpio_clear(spi_dev->cs);
/* Enable writes */
status = spi_transfer_byte(spi_dev->spi, NVRAM_SPI_CMD_WREN, NULL);
if (status < 0)
{
return status;
}
/* Release CS */
gpio_set(spi_dev->cs);
xtimer_spin(NVRAM_SPI_CS_TOGGLE_TICKS);
/* Re-assert CS */
gpio_clear(spi_dev->cs);
/* Write command and address */
status = spi_transfer_regs(spi_dev->spi, NVRAM_SPI_CMD_WRITE,
&addr.c[sizeof(addr.c) - spi_dev->address_count], NULL,
spi_dev->address_count);
if (status < 0)
{
return status;
}
/* Keep holding CS and write data */
status = spi_transfer_bytes(spi_dev->spi, (char *)src, NULL, len);
if (status < 0)
{
return status;
}
/* Release CS */
gpio_set(spi_dev->cs);
/* Release exclusive bus access */
spi_release(spi_dev->spi);
return status;
}
static int nvram_spi_read(nvram_t *dev, uint8_t *dst, uint32_t src, size_t len)
{
nvram_spi_params_t *spi_dev = (nvram_spi_params_t *) dev->extra;
int status;
union {
uint32_t u32;
char c[4];
} addr;
/* Address is expected by the device as big-endian, i.e. network byte order,
* we utilize the network byte order macros here. */
addr.u32 = HTONL(src);
/* Acquire exclusive bus access */
spi_acquire(spi_dev->spi);
/* Assert CS */
gpio_clear(spi_dev->cs);
/* Write command and address */
status = spi_transfer_regs(spi_dev->spi, NVRAM_SPI_CMD_READ,
&addr.c[sizeof(addr.c) - spi_dev->address_count],
NULL, spi_dev->address_count);
if (status < 0)
{
return status;
}
/* Keep holding CS and read data */
status = spi_transfer_bytes(spi_dev->spi, NULL, (char *)dst, len);
if (status < 0)
{
return status;
}
/* Release CS */
gpio_set(spi_dev->cs);
/* Release exclusive bus access */
spi_release(spi_dev->spi);
/* status contains the number of bytes actually read from the SPI bus. */
return status;
}
static int nvram_spi_write_9bit_addr(nvram_t *dev, const uint8_t *src, uint32_t dst, size_t len)
{
nvram_spi_params_t *spi_dev = (nvram_spi_params_t *) dev->extra;
int status;
uint8_t cmd;
uint8_t addr;
cmd = NVRAM_SPI_CMD_WRITE;
/* The upper address bit is mixed into the command byte on certain devices,
* probably just to save a byte in the SPI transfer protocol. */
if (dst > 0xff) {
cmd |= 0x08;
}
/* LSB of address */
addr = (dst & 0xff);
spi_acquire(spi_dev->spi);
gpio_clear(spi_dev->cs);
/* Enable writes */
status = spi_transfer_byte(spi_dev->spi, NVRAM_SPI_CMD_WREN, NULL);
if (status < 0)
{
return status;
}
gpio_set(spi_dev->cs);
xtimer_spin(NVRAM_SPI_CS_TOGGLE_TICKS);
gpio_clear(spi_dev->cs);
/* Write command and address */
status = spi_transfer_reg(spi_dev->spi, cmd, addr, NULL);
if (status < 0)
{
return status;
}
/* Keep holding CS and write data */
status = spi_transfer_bytes(spi_dev->spi, (char *)src, NULL, len);
if (status < 0)
{
return status;
}
gpio_set(spi_dev->cs);
spi_release(spi_dev->spi);
/* status contains the number of bytes actually written to the SPI bus. */
return status;
}
static int nvram_spi_read_9bit_addr(nvram_t *dev, uint8_t *dst, uint32_t src, size_t len)
{
nvram_spi_params_t *spi_dev = (nvram_spi_params_t *) dev->extra;
int status;
uint8_t cmd;
uint8_t addr;
cmd = NVRAM_SPI_CMD_READ;
/* The upper address bit is mixed into the command byte on certain devices,
* probably just to save a byte in the SPI transfer protocol. */
if (src > 0xff) {
cmd |= 0x08;
}
/* LSB of address */
addr = (src & 0xff);
spi_acquire(spi_dev->spi);
gpio_clear(spi_dev->cs);
/* Write command and address */
status = spi_transfer_reg(spi_dev->spi, (char)cmd, addr, NULL);
if (status < 0)
{
return status;
}
/* Keep holding CS and read data */
status = spi_transfer_bytes(spi_dev->spi, NULL, (char *)dst, len);
if (status < 0)
{
return status;
}
gpio_set(spi_dev->cs);
spi_release(spi_dev->spi);
/* status contains the number of bytes actually read from the SPI bus. */
return status;
}
/** @} */
|