Blame view

RIOT/boards/nucleo-f334/include/periph_conf.h 4.04 KB
fb11e647   vrobic   reseau statique a...
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
  /*
   * Copyright (C) 2015  Freie Universitรคt Berlin
   *
   * This file is subject to the terms and conditions of the GNU Lesser
   * General Public License v2.1. See the file LICENSE in the top level
   * directory for more details.
   */
  
  /**
   * @ingroup     boards_nucleo-f334
   * @{
   *
   * @file
   * @brief       Peripheral MCU configuration for the nucleo-f334 board
   *
   * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
   * @author      Kaspar Schleiser <kaspar.schleiser@fu-berlin.de>
   */
  
  #ifndef PERIPH_CONF_H_
  #define PERIPH_CONF_H_
  
  #include "periph_cpu.h"
  
  #ifdef __cplusplus
  extern "C" {
  #endif
  
  /**
   * @name Clock system configuration
   * @{
   **/
  #define CLOCK_HSE           (8000000U)          /* external oscillator */
  #define CLOCK_CORECLOCK     (72000000U)         /* desired core clock frequency */
  
  /* the actual PLL values are automatically generated */
  #define CLOCK_PLL_MUL       (CLOCK_CORECLOCK / CLOCK_HSE)
  #define CLOCK_AHB_DIV       RCC_CFGR_HPRE_DIV1
  #define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1
  #define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV2
  #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
  
  /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
  #define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
  #define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
  #define CLOCK_APB1          (CLOCK_CORECLOCK / 2)
  /** @} */
  
  /**
   * @brief   DAC configuration
   * @{
   */
  #define DAC_NUMOF           (0)
  /** @} */
  
  /**
   * @brief   DAC configuration
   * @{
   */
  #define DAC_NUMOF           (0)
  /** @} */
  
  /**
   * @brief Timer configuration
   * @{
   */
  static const timer_conf_t timer_config[] = {
      {
          .dev      = TIM2,
          .max      = 0xffffffff,
          .rcc_mask = RCC_APB1ENR_TIM2EN,
          .bus      = APB1,
          .irqn     = TIM2_IRQn
      }
  };
  
  #define TIMER_0_ISR         (isr_tim2)
  
  #define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
  /** @} */
  
  /**
   * @brief UART configuration
   * @}
   */
  #define UART_NUMOF          (1U)
  #define UART_0_EN           1
  #define UART_IRQ_PRIO       1
  
  /* UART 0 device configuration */
  #define UART_0_DEV          USART2
  #define UART_0_CLKEN()      (periph_clk_en(APB1, RCC_APB1ENR_USART2EN))
  #define UART_0_CLK          (CLOCK_CORECLOCK / 2)   /* UART clock runs with 32MHz (F_CPU / 1) */
  #define UART_0_IRQ_CHAN     USART2_IRQn
  #define UART_0_ISR          isr_usart2
  /* UART 0 pin configuration */
  #define UART_0_PORT         GPIOA
  #define UART_0_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
  #define UART_0_RX_PIN       3
  #define UART_0_TX_PIN       2
  #define UART_0_AF           7
  /** @} */
  
  /**
   * @brief   PWM configuration
   * @{
   */
  static const pwm_conf_t pwm_config[] = {
      {
          .dev      = TIM3,
          .rcc_mask = RCC_APB1ENR_TIM3EN,
          .pins     = { GPIO_PIN(PORT_C, 6), GPIO_PIN(PORT_C, 7),
                        GPIO_PIN(PORT_C, 8), GPIO_PIN(PORT_C, 9) },
          .af       = GPIO_AF2,
          .chan     = 4,
          .bus      = APB1
      }
  };
  
  #define PWM_NUMOF           (sizeof(pwm_config) / sizeof(pwm_config[0]))
  /** @} */
  
  /**
   * @name SPI configuration
   * @{
   */
  #define SPI_NUMOF           (1U)
  #define SPI_0_EN            1
  #define SPI_IRQ_PRIO        1
  
  /* SPI 0 device config */
  #define SPI_0_DEV               SPI1
  #define SPI_0_CLKEN()           (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
  #define SPI_0_CLKDIS()          (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
  #define SPI_0_IRQ               SPI1_IRQn
  #define SPI_0_IRQ_HANDLER       isr_spi1
  /* SPI 0 pin configuration */
  #define SPI_0_SCK_PORT          GPIOA
  #define SPI_0_SCK_PIN           5
  #define SPI_0_SCK_AF            5
  #define SPI_0_SCK_PORT_CLKEN()  (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
  #define SPI_0_MISO_PORT         GPIOA
  #define SPI_0_MISO_PIN          6
  #define SPI_0_MISO_AF           5
  #define SPI_0_MISO_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
  #define SPI_0_MOSI_PORT         GPIOA
  #define SPI_0_MOSI_PIN          7
  #define SPI_0_MOSI_AF           5
  #define SPI_0_MOSI_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
  /** @} */
  
  #ifdef __cplusplus
  }
  #endif
  
  #endif /* PERIPH_CONF_H_ */
  /** @} */