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/*
* Copyright (C) 2014-2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup cpu_cortexm_common ARM Cortex-M common
* @ingroup cpu
* @brief Common implementations and headers for Cortex-M family based
* micro-controllers
* @{
*
* @file
* @brief Basic definitions for the Cortex-M common module
*
* When ever you want to do something hardware related, that is accessing MCUs
* registers, just include this file. It will then make sure that the MCU
* specific headers are included.
*
* @author Stefan Pfeiffer <stefan.pfeiffer@fu-berlin.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*
* @todo remove include irq.h once core was adjusted
*/
#ifndef CPU_H_
#define CPU_H_
#include <stdio.h>
#include "irq.h"
#include "sched.h"
#include "thread.h"
#include "cpu_conf.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Some members of the Cortex-M family have architecture specific
* atomic operations in atomic_arch.c
*/
#if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
defined(CPU_ARCH_CORTEX_M4F)
#define ARCH_HAS_ATOMIC_COMPARE_AND_SWAP 1
#endif
/**
* @brief Interrupt stack canary value
*
* @note 0xe7fe is the ARM Thumb machine code equivalent of asm("bl #-2\n") or
* 'while (1);', i.e. an infinite loop.
* @internal
*/
#define STACK_CANARY_WORD (0xE7FEE7FEu)
/**
* @brief Initialization of the CPU
*/
void cpu_init(void);
/**
* @brief Initialize Cortex-M specific core parts of the CPU
*/
void cortexm_init(void);
/**
* @brief Prints the current content of the link register (lr)
*/
static inline void cpu_print_last_instruction(void)
{
uint32_t *lr_ptr;
__asm__ __volatile__("mov %0, lr" : "=r"(lr_ptr));
printf("%p\n", (void*) lr_ptr);
}
/**
* @brief Put the CPU into the 'wait for event' sleep mode
*
* This function is meant to be used for short periods of time, where it is not
* feasible to switch to the idle thread and back.
*/
static inline void cpu_sleep_until_event(void)
{
__WFE();
}
/**
* @brief Trigger a conditional context scheduler run / context switch
*
* This function is supposed to be called in the end of each ISR.
*/
static inline void cortexm_isr_end(void)
{
if (sched_context_switch_request) {
thread_yield();
}
}
#ifdef __cplusplus
}
#endif
#endif /* CPU_H_ */
/** @} */
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