Blame view

RIOT/boards/cc2650stk/include/periph_conf.h 1.47 KB
fb11e647   vrobic   reseau statique a...
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
  /*
   * Copyright (C) 2016 Leon George
   *
   * This file is subject to the terms and conditions of the GNU Lesser
   * General Public License v2.1. See the file LICENSE in the top level
   * directory for more details.
   */
  
  /**
   * @ingroup     boards_cc2650stk
   * @{
   *
   * @file
   * @brief       Peripheral MCU configuration for the CC2650STK board
   *
   * @author      Leon M. George <leon@georgemail.eu>
   */
  
  #ifndef PERIPH_CONF_H_
  #define PERIPH_CONF_H_
  
  #include "periph_cpu.h"
  
  #ifdef __cplusplus
  extern "C" {
  #endif
  
  /**
   * @brief   Clock configuration
   * @{
   */
  /* the main clock is fixed to 48MHZ */
  #define CLOCK_CORECLOCK     (48000000U)
  /** @} */
  
  /**
   * @brief   Timer configuration
   * @{
   */
  static const timer_conf_t timer_config[] = {
      {
          .dev  = GPT0,
          .num  = 0
      },
      {
          .dev  = GPT1,
          .num  = 1
      }
  };
  
  #define TIMER_0_ISR         isr_timer0_chan0
  #define TIMER_1_ISR         isr_timer1_chan0
  
  #define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
  /** @} */
  
  /**
   * @brief   UART configuration
   *
   * The used CC26x0 CPU only supports a single UART device, so all we need to
   * configure are the RX and TX pins.
   *
   * Optionally we can enable hardware flow control, by setting UART_HW_FLOW_CTRL
   * to 1 and defining pins for UART_CTS_PIN and UART_RTS_PIN.
   * @{
   */
  #define UART_NUMOF          (1)
  #define UART_RX_PIN         (28)
  #define UART_TX_PIN         (29)
  /** @} */
  
  #ifdef __cplusplus
  }
  #endif
  
  #endif /* PERIPH_CONF_H_ */
  /** @} */