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/*
* Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
* 2015 FreshTemp, LLC.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_saml21
* @{
*
* @file cpu.c
* @brief Implementation of the CPU initialization for Atmel SAML21 MCUs
*
* @author Kaspar Schleiser <kaspar@schleiser.de>
* @}
*/
#include "arch/lpm_arch.h"
#include "cpu.h"
static void _gclk_setup(int gclk, uint32_t reg)
{
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(gclk)) {}
GCLK->GENCTRL[gclk].reg = reg;
}
/**
* @brief Initialize the CPU, set IRQ priorities, clocks
*/
void cpu_init(void)
{
/* disable the watchdog timer */
WDT->CTRLA.bit.ENABLE = 0;
/* initialize the Cortex-M core */
cortexm_init();
/* turn on only needed APB peripherals */
MCLK->APBAMASK.reg =
MCLK_APBAMASK_PM
|MCLK_APBAMASK_MCLK
|MCLK_APBAMASK_RSTC
|MCLK_APBAMASK_OSCCTRL
|MCLK_APBAMASK_OSC32KCTRL
|MCLK_APBAMASK_SUPC
|MCLK_APBAMASK_GCLK
|MCLK_APBAMASK_WDT
|MCLK_APBAMASK_RTC
|MCLK_APBAMASK_EIC
|MCLK_APBAMASK_PORT
//|MCLK_APBAMASK_TAL
;
/* Software reset the GCLK module to ensure it is re-initialized correctly */
GCLK->CTRLA.reg = GCLK_CTRLA_SWRST;
while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) {}
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) {}
/* set OSC16M to 16MHz */
OSCCTRL->OSC16MCTRL.bit.FSEL = 3;
OSCCTRL->OSC16MCTRL.bit.ONDEMAND = 0;
OSCCTRL->OSC16MCTRL.bit.RUNSTDBY = 0;
/* Setup GCLK generators */
_gclk_setup(0, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M);
_gclk_setup(1, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSCULP32K);
lpm_arch_init();
}
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