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-- VHDL essai1diodes
-- 2017 3 28 9 8 36
-- Created By "Altium Designer VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 16.1.12.290
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-- VHDL essai1diodes
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Library IEEE;
Use     IEEE.std_logic_1164.all;

Entity projet_sc Is
  port
  (
    HA   : InOut STD_LOGIC_VECTOR(19 Downto 2);              -- ObjectKind=Port|PrimaryId=HA[19..2]
    LEDS : Out   STD_LOGIC_VECTOR(7 Downto 0)                -- ObjectKind=Port|PrimaryId=LEDS[7..0]
  );
  attribute MacroCell : boolean;

  attribute ConnectTo : string;
  attribute ConnectTo of HA   : Signal is "HDR_B-41,HDR_B-39,HDR_B-37,HDR_B-35,HDR_B-33,HDR_B-31,HDR_B-29,HDR_B-27,HDR_B-25,HDR_B-23,HDR_B-21,HDR_B-19,HDR_B-17,HDR_B-15,HDR_B-13,HDR_B-11,HDR_B-9,HDR_B-7";
  attribute ConnectTo of LEDS : Signal is "HDR_B-20,HDR_B-18,HDR_B-16,HDR_B-14,HDR_B-12,HDR_B-10,HDR_B-8,HDR_B-6";

  attribute TargetIdAlias : string;
  attribute TargetIdAlias of HA   : Signal is "HA19,HA18,HA17,HA16,HA15,HA14,HA13,HA12,HA11,HA10,HA9,HA8,HA7,HA6,HA5,HA4,HA3,HA2";
  attribute TargetIdAlias of LEDS : Signal is "LEDS7,LEDS6,LEDS5,LEDS4,LEDS3,LEDS2,LEDS1,LEDS0";


End projet_sc;
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Architecture Structure Of projet_sc Is
   Component Configurable_U1                                 -- ObjectKind=Part|PrimaryId=U1|SecondaryId=1
      port
      (
        I   : in  STD_LOGIC_VECTOR(17 Downto 0);             -- ObjectKind=Pin|PrimaryId=U1-I[17..0]
        O0  : out STD_LOGIC;                                 -- ObjectKind=Pin|PrimaryId=U1-O0
        O1  : out STD_LOGIC;                                 -- ObjectKind=Pin|PrimaryId=U1-O1
        O2  : out STD_LOGIC;                                 -- ObjectKind=Pin|PrimaryId=U1-O2
        O3  : out STD_LOGIC;                                 -- ObjectKind=Pin|PrimaryId=U1-O3
        O4  : out STD_LOGIC;                                 -- ObjectKind=Pin|PrimaryId=U1-O4
        O5  : out STD_LOGIC;                                 -- ObjectKind=Pin|PrimaryId=U1-O5
        O6  : out STD_LOGIC;                                 -- ObjectKind=Pin|PrimaryId=U1-O6
        O7  : out STD_LOGIC;                                 -- ObjectKind=Pin|PrimaryId=U1-O7
        O8  : out STD_LOGIC;                                 -- ObjectKind=Pin|PrimaryId=U1-O8
        O9  : out STD_LOGIC;                                 -- ObjectKind=Pin|PrimaryId=U1-O9
        O10 : out STD_LOGIC;                                 -- ObjectKind=Pin|PrimaryId=U1-O10
        O11 : out STD_LOGIC;                                 -- ObjectKind=Pin|PrimaryId=U1-O11
        O12 : out STD_LOGIC;                                 -- ObjectKind=Pin|PrimaryId=U1-O12
        O13 : out STD_LOGIC;                                 -- ObjectKind=Pin|PrimaryId=U1-O13
        O14 : out STD_LOGIC;                                 -- ObjectKind=Pin|PrimaryId=U1-O14
        O15 : out STD_LOGIC;                                 -- ObjectKind=Pin|PrimaryId=U1-O15
        O16 : out STD_LOGIC;                                 -- ObjectKind=Pin|PrimaryId=U1-O16
        O17 : out STD_LOGIC                                  -- ObjectKind=Pin|PrimaryId=U1-O17
      );
   End Component;

   Component Configurable_U2                                 -- ObjectKind=Part|PrimaryId=U2|SecondaryId=1
      port
      (
        I0 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U2-I0
        I1 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U2-I1
        I2 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U2-I2
        I3 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U2-I3
        I4 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U2-I4
        I5 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U2-I5
        I6 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U2-I6
        I7 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U2-I7
        O  : out STD_LOGIC_VECTOR(7 Downto 0)                -- ObjectKind=Pin|PrimaryId=U2-O[7..0]
      );
   End Component;


    Signal PinSignal_U1_O0 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_O0
    Signal PinSignal_U1_O1 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_O1
    Signal PinSignal_U1_O2 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_O2
    Signal PinSignal_U1_O3 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_O3
    Signal PinSignal_U1_O4 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_O4
    Signal PinSignal_U1_O5 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_O5
    Signal PinSignal_U1_O6 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_O6
    Signal PinSignal_U1_O7 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_O7
    Signal PinSignal_U2_O  : STD_LOGIC_VECTOR(7 Downto 0); -- ObjectKind=Net|PrimaryId=LEDS[7..0]



Begin
    U2 : Configurable_U2                                     -- ObjectKind=Part|PrimaryId=U2|SecondaryId=1
      Port Map
      (
        I0 => PinSignal_U1_O0,                               -- ObjectKind=Pin|PrimaryId=U2-I0
        I1 => PinSignal_U1_O1,                               -- ObjectKind=Pin|PrimaryId=U2-I1
        I2 => PinSignal_U1_O2,                               -- ObjectKind=Pin|PrimaryId=U2-I2
        I3 => PinSignal_U1_O3,                               -- ObjectKind=Pin|PrimaryId=U2-I3
        I4 => PinSignal_U1_O4,                               -- ObjectKind=Pin|PrimaryId=U2-I4
        I5 => PinSignal_U1_O5,                               -- ObjectKind=Pin|PrimaryId=U2-I5
        I6 => PinSignal_U1_O6,                               -- ObjectKind=Pin|PrimaryId=U2-I6
        I7 => PinSignal_U1_O7,                               -- ObjectKind=Pin|PrimaryId=U2-I7
        O  => PinSignal_U2_O                                 -- ObjectKind=Pin|PrimaryId=U2-O[7..0]
      );

    U1 : Configurable_U1                                     -- ObjectKind=Part|PrimaryId=U1|SecondaryId=1
      Port Map
      (
        I  => HA,                                            -- ObjectKind=Pin|PrimaryId=U1-I[17..0]
        O0 => PinSignal_U1_O0,                               -- ObjectKind=Pin|PrimaryId=U1-O0
        O1 => PinSignal_U1_O1,                               -- ObjectKind=Pin|PrimaryId=U1-O1
        O2 => PinSignal_U1_O2,                               -- ObjectKind=Pin|PrimaryId=U1-O2
        O3 => PinSignal_U1_O3,                               -- ObjectKind=Pin|PrimaryId=U1-O3
        O4 => PinSignal_U1_O4,                               -- ObjectKind=Pin|PrimaryId=U1-O4
        O5 => PinSignal_U1_O5,                               -- ObjectKind=Pin|PrimaryId=U1-O5
        O6 => PinSignal_U1_O6,                               -- ObjectKind=Pin|PrimaryId=U1-O6
        O7 => PinSignal_U1_O7                                -- ObjectKind=Pin|PrimaryId=U1-O7
      );

    -- Signal Assignments
    ---------------------
    LEDS <= PinSignal_U2_O; -- ObjectKind=Net|PrimaryId=LEDS[7..0]

End Structure;
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