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-- VHDL essai1diodes
-- 2017 3 28 10 9 45
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 16.1.12.290
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-- VHDL essai1diodes
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Library IEEE;
Use     IEEE.std_logic_1164.all;

Entity essai1diodes Is
  port
  (
    HA2  : In    STD_LOGIC;                                  -- ObjectKind=Port|PrimaryId=HA2
    HA3  : In    STD_LOGIC;                                  -- ObjectKind=Port|PrimaryId=HA3
    HA4  : In    STD_LOGIC;                                  -- ObjectKind=Port|PrimaryId=HA4
    HA5  : In    STD_LOGIC;                                  -- ObjectKind=Port|PrimaryId=HA5
    HA6  : In    STD_LOGIC;                                  -- ObjectKind=Port|PrimaryId=HA6
    HA7  : In    STD_LOGIC;                                  -- ObjectKind=Port|PrimaryId=HA7
    HA8  : In    STD_LOGIC;                                  -- ObjectKind=Port|PrimaryId=HA8
    LEDS : Out   STD_LOGIC_VECTOR(7 Downto 0)                -- ObjectKind=Port|PrimaryId=LEDS[7..0]
  );
  attribute MacroCell : boolean;

End essai1diodes;
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Architecture Structure Of essai1diodes Is
   Component Configurable_U2                                 -- ObjectKind=Part|PrimaryId=U2|SecondaryId=1
      port
      (
        I0 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U2-I0
        I1 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U2-I1
        I2 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U2-I2
        I3 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U2-I3
        I4 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U2-I4
        I5 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U2-I5
        I6 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U2-I6
        I7 : in  STD_LOGIC;                                  -- ObjectKind=Pin|PrimaryId=U2-I7
        O  : out STD_LOGIC_VECTOR(7 Downto 0)                -- ObjectKind=Pin|PrimaryId=U2-O[7..0]
      );
   End Component;


    Signal PinSignal_U2_O  : STD_LOGIC_VECTOR(7 Downto 0); -- ObjectKind=Net|PrimaryId=LEDS[7..0]
    Signal PowerSignal_VCC : STD_LOGIC; -- ObjectKind=Net|PrimaryId=VCC

Begin
    U2 : Configurable_U2                                     -- ObjectKind=Part|PrimaryId=U2|SecondaryId=1
      Port Map
      (
        I0 => HA2,                                           -- ObjectKind=Pin|PrimaryId=U2-I0
        I1 => HA3,                                           -- ObjectKind=Pin|PrimaryId=U2-I1
        I2 => HA4,                                           -- ObjectKind=Pin|PrimaryId=U2-I2
        I3 => HA5,                                           -- ObjectKind=Pin|PrimaryId=U2-I3
        I4 => HA6,                                           -- ObjectKind=Pin|PrimaryId=U2-I4
        I5 => HA7,                                           -- ObjectKind=Pin|PrimaryId=U2-I5
        I6 => HA8,                                           -- ObjectKind=Pin|PrimaryId=U2-I6
        I7 => PowerSignal_VCC,                               -- ObjectKind=Pin|PrimaryId=U2-I7
        O  => PinSignal_U2_O                                 -- ObjectKind=Pin|PrimaryId=U2-O[7..0]
      );

    -- Signal Assignments
    ---------------------
    LEDS            <= PinSignal_U2_O; -- ObjectKind=Net|PrimaryId=LEDS[7..0]
    PowerSignal_VCC <= '1'; -- ObjectKind=Net|PrimaryId=VCC

End Structure;
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