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Release 14.3 Trace  (nt64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

C:\Xilinx\14.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -l 30 -u 30 projet_sc.ncd
C:\Users\Altium-3\Desktop\blas_delaporte\ProjectOutputs\Default - All Constraints\projet_sc_map.pcf

Design file:              projet_sc.ncd
Physical constraint file: projet_sc_map.pcf
Device,package,speed:     xc3s1500,fg676,-4 (PRODUCTION 1.39 2012-10-12)
Report level:             summary report, limited to 0 items per constraint
                          unconstrained path report, limited to 30 items

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter 
   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock 
   Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 
   'Phase Error' calculations, these terms will be zero in the Clock 
   Uncertainty calculation.  Please make appropriate modification to 
   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase 
   Error.

Data Sheet report:
-----------------
No constraints were found to generate data for the Data Sheet Report section.
Use the Advanced Analysis (-a) option or generate global constraints for each
clock, its pad to setup and clock to pad paths, and a pad to pad constraint.

Analysis completed Tue Mar 28 09:09:07 2017 
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 168 MB