------------------------------------------------------------ -- VHDL Sheet1 -- 2017 3 21 12 7 4 -- Created By "DXP VHDL Generator" -- "Copyright (c) 2002-2014 Altium Limited" -- Product Version: 16.1.12.290 ------------------------------------------------------------ ------------------------------------------------------------ -- VHDL Sheet1 ------------------------------------------------------------ Library IEEE; Use IEEE.std_logic_1164.all; --synthesis translate_off Library GENERIC_LIB; Use GENERIC_LIB.all; --synthesis translate_on Entity Sheet1 Is port ( CLK_BRD : In STD_LOGIC; -- ObjectKind=Port|PrimaryId=CLK_BRD HA2 : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=HA2 LEDS : Out STD_LOGIC_VECTOR(7 Downto 0); -- ObjectKind=Port|PrimaryId=LEDS[7..0] SW_USER0 : In STD_LOGIC -- ObjectKind=Port|PrimaryId=SW_USER0 ); attribute MacroCell : boolean; End Sheet1; ------------------------------------------------------------ ------------------------------------------------------------ Architecture Structure Of Sheet1 Is Component CB4CLEB -- ObjectKind=Part|PrimaryId=U2|SecondaryId=1 port ( C : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U2-C CE : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U2-CE CEO : out STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U2-CEO CLR : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U2-CLR D : in STD_LOGIC_VECTOR(3 Downto 0); -- ObjectKind=Pin|PrimaryId=U2-D[3..0] L : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U2-L Q : out STD_LOGIC_VECTOR(3 Downto 0); -- ObjectKind=Pin|PrimaryId=U2-Q[3..0] TC : out STD_LOGIC -- ObjectKind=Pin|PrimaryId=U2-TC ); End Component; Component CLKGEN -- ObjectKind=Part|PrimaryId=U5|SecondaryId=1 port ( FREQ : out STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U5-FREQ TIMEBASE : in STD_LOGIC -- ObjectKind=Pin|PrimaryId=U5-TIMEBASE ); End Component; Component Configurable_U1 -- ObjectKind=Part|PrimaryId=U1|SecondaryId=1 port ( AOUT : out STD_LOGIC_VECTOR(3 Downto 0) -- ObjectKind=Pin|PrimaryId=U1-AOUT[3..0] ); End Component; Component Configurable_U3 -- ObjectKind=Part|PrimaryId=U3|SecondaryId=1 port ( I : in STD_LOGIC_VECTOR(3 Downto 0); -- ObjectKind=Pin|PrimaryId=U3-I[3..0] O0 : out STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U3-O0 O1 : out STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U3-O1 O2 : out STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U3-O2 O3 : out STD_LOGIC -- ObjectKind=Pin|PrimaryId=U3-O3 ); End Component; Component Configurable_U4 -- ObjectKind=Part|PrimaryId=U4|SecondaryId=1 port ( I0 : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U4-I0 I1 : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U4-I1 I2 : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U4-I2 I3 : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U4-I3 I4 : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U4-I4 I5 : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U4-I5 I6 : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U4-I6 I7 : in STD_LOGIC; -- ObjectKind=Pin|PrimaryId=U4-I7 O : out STD_LOGIC_VECTOR(7 Downto 0) -- ObjectKind=Pin|PrimaryId=U4-O[7..0] ); End Component; Signal PinSignal_U1_AOUT : STD_LOGIC_VECTOR(3 Downto 0); -- ObjectKind=Net|PrimaryId=NetU1_AOUT[3..0] Signal PinSignal_U2_Q : STD_LOGIC_VECTOR(3 Downto 0); -- ObjectKind=Net|PrimaryId=NetU2_Q[3..0] Signal PinSignal_U3_O0 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU3_O0 Signal PinSignal_U3_O1 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU3_O1 Signal PinSignal_U3_O2 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU3_O2 Signal PinSignal_U3_O3 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU3_O3 Signal PinSignal_U4_O : STD_LOGIC_VECTOR(7 Downto 0); -- ObjectKind=Net|PrimaryId=LEDS[7..0] Signal PinSignal_U5_FREQ : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU2_C Signal PowerSignal_GND : STD_LOGIC; -- ObjectKind=Net|PrimaryId=GND Signal PowerSignal_VCC : STD_LOGIC; -- ObjectKind=Net|PrimaryId=VCC Begin U5 : CLKGEN -- ObjectKind=Part|PrimaryId=U5|SecondaryId=1 Port Map ( FREQ => PinSignal_U5_FREQ, -- ObjectKind=Pin|PrimaryId=U5-FREQ TIMEBASE => CLK_BRD -- ObjectKind=Pin|PrimaryId=U5-TIMEBASE ); U4 : Configurable_U4 -- ObjectKind=Part|PrimaryId=U4|SecondaryId=1 Port Map ( I0 => PinSignal_U3_O0, -- ObjectKind=Pin|PrimaryId=U4-I0 I1 => PinSignal_U3_O1, -- ObjectKind=Pin|PrimaryId=U4-I1 I2 => PinSignal_U3_O2, -- ObjectKind=Pin|PrimaryId=U4-I2 I3 => PinSignal_U3_O3, -- ObjectKind=Pin|PrimaryId=U4-I3 I4 => PowerSignal_GND, -- ObjectKind=Pin|PrimaryId=U4-I4 I5 => PowerSignal_GND, -- ObjectKind=Pin|PrimaryId=U4-I5 I6 => PowerSignal_GND, -- ObjectKind=Pin|PrimaryId=U4-I6 I7 => PowerSignal_GND, -- ObjectKind=Pin|PrimaryId=U4-I7 O => PinSignal_U4_O -- ObjectKind=Pin|PrimaryId=U4-O[7..0] ); U3 : Configurable_U3 -- ObjectKind=Part|PrimaryId=U3|SecondaryId=1 Port Map ( I => PinSignal_U2_Q, -- ObjectKind=Pin|PrimaryId=U3-I[3..0] O0 => PinSignal_U3_O0, -- ObjectKind=Pin|PrimaryId=U3-O0 O1 => PinSignal_U3_O1, -- ObjectKind=Pin|PrimaryId=U3-O1 O2 => PinSignal_U3_O2, -- ObjectKind=Pin|PrimaryId=U3-O2 O3 => PinSignal_U3_O3 -- ObjectKind=Pin|PrimaryId=U3-O3 ); U2 : CB4CLEB -- ObjectKind=Part|PrimaryId=U2|SecondaryId=1 Port Map ( C => PinSignal_U5_FREQ, -- ObjectKind=Pin|PrimaryId=U2-C CE => PowerSignal_VCC, -- ObjectKind=Pin|PrimaryId=U2-CE CLR => PowerSignal_GND, -- ObjectKind=Pin|PrimaryId=U2-CLR D => PinSignal_U1_AOUT, -- ObjectKind=Pin|PrimaryId=U2-D[3..0] L => SW_USER0, -- ObjectKind=Pin|PrimaryId=U2-L Q => PinSignal_U2_Q -- ObjectKind=Pin|PrimaryId=U2-Q[3..0] ); U1 : Configurable_U1 -- ObjectKind=Part|PrimaryId=U1|SecondaryId=1 Port Map ( AOUT => PinSignal_U1_AOUT -- ObjectKind=Pin|PrimaryId=U1-AOUT[3..0] ); -- Signal Assignments --------------------- HA2 <= PinSignal_U5_FREQ; -- ObjectKind=Net|PrimaryId=NetU2_C LEDS <= PinSignal_U4_O; -- ObjectKind=Net|PrimaryId=LEDS[7..0] PowerSignal_GND <= '0'; -- ObjectKind=Net|PrimaryId=GND PowerSignal_VCC <= '1'; -- ObjectKind=Net|PrimaryId=VCC End Structure; ------------------------------------------------------------