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LIBRARY IEEE;
USE IEEE.Std_Logic_1164.all;
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--------------------------------------------------------------------------------
ENTITY Configurable_U1 IS
PORT(
O0 : OUT std_logic;
O1 : OUT std_logic;
O2 : OUT std_logic;
O3 : OUT std_logic;
O4 : OUT std_logic;
O5 : OUT std_logic;
O6 : OUT std_logic;
O7 : OUT std_logic;
O8 : OUT std_logic;
O9 : OUT std_logic;
O10 : OUT std_logic;
O11 : OUT std_logic;
O12 : OUT std_logic;
O13 : OUT std_logic;
O14 : OUT std_logic;
O15 : OUT std_logic;
O16 : OUT std_logic;
O17 : OUT std_logic;
I : IN std_logic_vector(17 downto 0)
);
END Configurable_U1;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
ARCHITECTURE structure OF Configurable_U1 IS
BEGIN
O0 <= I(0);
O1 <= I(1);
O2 <= I(2);
O3 <= I(3);
O4 <= I(4);
O5 <= I(5);
O6 <= I(6);
O7 <= I(7);
O8 <= I(8);
O9 <= I(9);
O10 <= I(10);
O11 <= I(11);
O12 <= I(12);
O13 <= I(13);
O14 <= I(14);
O15 <= I(15);
O16 <= I(16);
O17 <= I(17);
END structure;
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