Release 14.3 - Bitgen P.40xd (nt64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
Loading device for application Rf_Device from file '3s1500.nph' in environment
C:\Xilinx\14.3\ISE_DS\ISE\.
   "FPGA_projet" is an NCD, version 3.2, device xc3s1500, package fg676, speed
-4
Opened constraints file
C:\Users\Altium7\Documents\csaadVandamme\FPGA_projet\ProjectOutputs\Default -
All Constraints\FPGA_projet_map.pcf.

Wed May 17 18:19:43 2017

C:\Xilinx\14.3\ISE_DS\ISE\bin\nt64\unwrapped\Bitgen.exe -w -b -g TdoPin:Pullnone -g UserID:0xFFFFFFFF -g StartupClk:cclk fpga_projet.ncd fpga_projet_cclk.bit "C:\Users\Altium7\Documents\csaadVandamme\FPGA_projet\ProjectOutputs\Default - All Constraints\FPGA_projet_map.pcf" 

Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name          | Current Setting      |
+----------------------+----------------------+
| Compress             | (Not Specified)*     |
+----------------------+----------------------+
| Readback             | (Not Specified)*     |
+----------------------+----------------------+
| CRC                  | Enable*              |
+----------------------+----------------------+
| DebugBitstream       | No*                  |
+----------------------+----------------------+
| ConfigRate           | 6*                   |
+----------------------+----------------------+
| StartupClk           | Cclk**               |
+----------------------+----------------------+
| DCMShutdown          | Disable*             |
+----------------------+----------------------+
| DCIUpdateMode        | AsRequired*          |
+----------------------+----------------------+
| CclkPin              | Pullup*              |
+----------------------+----------------------+
| DonePin              | Pullup*              |
+----------------------+----------------------+
| HswapenPin           | Pullup*              |
+----------------------+----------------------+
| M0Pin                | Pullup*              |
+----------------------+----------------------+
| M1Pin                | Pullup*              |
+----------------------+----------------------+
| M2Pin                | Pullup*              |
+----------------------+----------------------+
| ProgPin              | Pullup*              |
+----------------------+----------------------+
| TckPin               | Pullup*              |
+----------------------+----------------------+
| TdiPin               | Pullup*              |
+----------------------+----------------------+
| TdoPin               | Pullnone             |
+----------------------+----------------------+
| TmsPin               | Pullup*              |
+----------------------+----------------------+
| UnusedPin            | Pulldown*            |
+----------------------+----------------------+
| GWE_cycle            | 6*                   |
+----------------------+----------------------+
| GTS_cycle            | 5*                   |
+----------------------+----------------------+
| LCK_cycle            | NoWait*              |
+----------------------+----------------------+
| Match_cycle          | NoWait               |
+----------------------+----------------------+
| DONE_cycle           | 4*                   |
+----------------------+----------------------+
| Persist              | No*                  |
+----------------------+----------------------+
| DriveDone            | No*                  |
+----------------------+----------------------+
| DonePipe             | No*                  |
+----------------------+----------------------+
| Security             | None*                |
+----------------------+----------------------+
| UserID               | 0xFFFFFFFF**         |
+----------------------+----------------------+
| ActivateGclk         | No*                  |
+----------------------+----------------------+
| ActiveReconfig       | No*                  |
+----------------------+----------------------+
| PartialMask0         | (Not Specified)*     |
+----------------------+----------------------+
| PartialMask1         | (Not Specified)*     |
+----------------------+----------------------+
| PartialMask2         | (Not Specified)*     |
+----------------------+----------------------+
| PartialGclk          | (Not Specified)*     |
+----------------------+----------------------+
| PartialLeft          | (Not Specified)*     |
+----------------------+----------------------+
| PartialRight         | (Not Specified)*     |
+----------------------+----------------------+
| TimeStamp            | Default*             |
+----------------------+----------------------+
| IEEE1532             | No*                  |
+----------------------+----------------------+
| Binary               | No*                  |
+----------------------+----------------------+
 *  Default setting.
 ** The specified setting matches the default setting.

There were 0 CONFIG constraint(s) processed from C:\Users\Altium7\Documents\csaadVandamme\FPGA_projet\ProjectOutputs\Default - All Constraints\FPGA_projet_map.pcf.


Running DRC.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c9 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c10 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c1 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c4 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c5 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c3 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c7 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c8 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c6 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c0 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c2 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   U3/U_FREQ/divisor_9_0_component_c8/u1_s is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   U3/U_FREQ/divisor_25_0_component_c9/u1_s is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net PinSignal_U8_TC is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net PinSignal_U3_FREQ is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal <U3/TDO_ENABLE> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/TAP1/exit1dr> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_11> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_10> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_13> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_12> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_21> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_20> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_15> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_14> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_23> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_22> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_31> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_30> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_17> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_16> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_25> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_24> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_19> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_18> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_27> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_26> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_29> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_28> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_11> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_10> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_13> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_12> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_15> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_14> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/TAP1/reset> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_11> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_10> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_13> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_12> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_15> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_14> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U7/CEO> is incomplete. The signal does
   not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_1> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_0> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_3> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_2> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_5> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_4> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_7> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_6> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_9> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_8> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Value/regout_0> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_1> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_0> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_3> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_2> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_5> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_4> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_7> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_6> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_9> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_8> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_1> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_0> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_3> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_2> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_5> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_4> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_7> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_6> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_9> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_8> is
   incomplete. The signal does not drive any load pins in the design.
DRC detected 0 errors and 84 warnings.  Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "fpga_projet_cclk.bit".
Saving bit stream in "fpga_projet_cclk.rbt".
Bitstream generation is complete.