--------------------------------------------------------------------------------
Release 14.3 Trace  (nt64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

C:\Xilinx\14.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -l 30 -u 30
fpga_projet.ncd
C:\Users\Altium7\Documents\csaadVandamme\FPGA_projet\ProjectOutputs\Default - All Constraints\FPGA_projet_map.pcf

Design file:              fpga_projet.ncd
Physical constraint file: FPGA_projet_map.pcf
Device,package,speed:     xc3s1500,fg676,-4 (PRODUCTION 1.39 2012-10-12)
Report level:             summary report, limited to 0 items per constraint
                          unconstrained path report, limited to 30 items

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter 
   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock 
   Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 
   'Phase Error' calculations, these terms will be zero in the Clock 
   Uncertainty calculation.  Please make appropriate modification to 
   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase 
   Error.

Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock JTAG_NEXUS_TCK
--------------+------------+------------+------------------+--------+
              |Max Setup to|Max Hold to |                  | Clock  |
Source        | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
--------------+------------+------------+------------------+--------+
JTAG_NEXUS_TDI|   -0.164(R)|    6.102(R)|n2k               |   0.000|
JTAG_NEXUS_TMS|   -2.346(R)|    5.690(R)|n2k               |   0.000|
--------------+------------+------------+------------------+--------+

Clock CLK_BRD to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
HA2         |    7.440(R)|n2j               |   0.000|
HA8         |   48.536(R)|PinSignal_U3_FREQ |   0.000|
------------+------------+------------------+--------+

Clock JTAG_NEXUS_TCK to Pad
--------------+------------+------------------+--------+
              | clk (edge) |                  | Clock  |
Destination   |   to PAD   |Internal Clock(s) | Phase  |
--------------+------------+------------------+--------+
HA8           |   23.674(R)|n2k               |   0.000|
JTAG_NEXUS_TDO|   26.294(R)|n2k               |   0.000|
--------------+------------+------------------+--------+

Clock to Setup on destination clock CLK_BRD
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK_BRD        |   43.573|         |         |         |
JTAG_NEXUS_TCK |   12.940|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock JTAG_NEXUS_TCK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
JTAG_NEXUS_TCK |    8.512|    7.426|    4.097|         |
---------------+---------+---------+---------+---------+


Analysis completed Wed May 17 18:19:33 2017 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 186 MB