The command line option -t can only be used when running in timing mode (-timing option). The option will be ignored. The -tx switch is not supported for this architecture, and will be ignored. Logical network U7/CEO has no load. The above info message is repeated 68 more times for the following (max. 5 shown): U5/RegisterInput_Value/regout_0, U5/RegisterConfiguration/regout_31, U5/RegisterConfiguration/regout_30, U5/RegisterConfiguration/regout_29, U5/RegisterConfiguration/regout_28 To see the details of these info messages, please use the -detail switch. No environment variables are currently set. All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. Clock buffer is designated to drive clock loads. BUFGMUX symbol "physical_group_n2j/n2j" (output signal=n2j) has a mix of clock and non-clock loads. The non-clock loads are: Pin I0 of U3/U_FREQ/freq_sig_m2_am Pin I0 of U3/U_FREQ/divisor_5_0_component_c0/clkd Pin I0 of U3/U_FREQ/divisor_5_0_component_c0/clko The function generator U5/TAP1/tapstate_r__not_0 failed to merge with F5 multiplexer U5/TAP1/i223. Tried to combine two collections of symbols from different positions within the same layer. The design will exhibit suboptimal timing. The function generator U5/TAP1/tapstate_r__not_0 failed to merge with F5 multiplexer U5/TAP1/i224. Unable to resolve the conflicts between two or more collections of symbols which have restrictive placement or routing requirements. The original symbols are: MUXF5 symbol "U5/TAP1/i224" (Output Signal = U5/TAP1/n237) LUT symbol "U5/TAP1/tapstate_r__not_0" (Output Signal = U5/TAP1/tapstate_r__not_0) MUXF5 symbol "U5/TAP1/i222" (Output Signal = U5/TAP1/n235) Failure 1: Unable to combine the following symbols into a single slice. MUXF5 symbol "U5/TAP1/i224" (Output Signal = U5/TAP1/n237) MUXF5 symbol "U5/TAP1/i222" (Output Signal = U5/TAP1/n235) LUT symbol "U5/TAP1/tapstate_r__not_0" (Output Signal = U5/TAP1/tapstate_r__not_0) There is more than one F5MUX. Failure 2: Unable to combine the following symbols into a single slice. MUXF6 symbol "U5/TAP1/i227" (Output Signal = U5/TAP1/n240) MUXF5 symbol "U5/TAP1/i225" (Output Signal = U5/TAP1/n238) MUXF6 symbol "U5/TAP1/i226" (Output Signal = U5/TAP1/n239) MUXF5 symbol "U5/TAP1/i223" (Output Signal = U5/TAP1/n236) There is more than one MUXF6. The design will exhibit suboptimal timing. Gated clock. Clock net U3/U_FREQ/clk_div_c9 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net U3/U_FREQ/clk_div_c10 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net U3/U_FREQ/clk_div_c1 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net U3/U_FREQ/clk_div_c4 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net U3/U_FREQ/clk_div_c5 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net U3/U_FREQ/clk_div_c3 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net U3/U_FREQ/clk_div_c7 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net U3/U_FREQ/clk_div_c8 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net U3/U_FREQ/clk_div_c6 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net U3/U_FREQ/clk_div_c0 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net U3/U_FREQ/clk_div_c2 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net U3/U_FREQ/divisor_9_0_component_c8/u1_s is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net U3/U_FREQ/divisor_25_0_component_c9/u1_s is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net PinSignal_U8_TC is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net PinSignal_U3_FREQ is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. The signal <U3/TDO_ENABLE> is incomplete. The signal does not drive any load pins in the design. The signal <U5/TAP1/exit1dr> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_11> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_10> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_13> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_12> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_21> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_20> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_15> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_14> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_23> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_22> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_31> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_30> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_17> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_16> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_25> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_24> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_19> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_18> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_27> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_26> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_29> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_28> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterOutput_Length/regout_11> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterOutput_Length/regout_10> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterOutput_Length/regout_13> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterOutput_Length/regout_12> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterOutput_Length/regout_15> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterOutput_Length/regout_14> is incomplete. The signal does not drive any load pins in the design. The signal <U5/TAP1/reset> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterInput_Length/regout_11> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterInput_Length/regout_10> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterInput_Length/regout_13> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterInput_Length/regout_12> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterInput_Length/regout_15> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterInput_Length/regout_14> is incomplete. The signal does not drive any load pins in the design. The signal <U7/CEO> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterInput_Length/regout_1> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterInput_Length/regout_0> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterInput_Length/regout_3> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterInput_Length/regout_2> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterInput_Length/regout_5> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterInput_Length/regout_4> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterInput_Length/regout_7> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterInput_Length/regout_6> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterInput_Length/regout_9> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterInput_Length/regout_8> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterInput_Value/regout_0> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_1> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_0> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_3> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_2> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_5> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_4> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_7> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_6> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_9> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterConfiguration/regout_8> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterOutput_Length/regout_1> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterOutput_Length/regout_0> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterOutput_Length/regout_3> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterOutput_Length/regout_2> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterOutput_Length/regout_5> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterOutput_Length/regout_4> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterOutput_Length/regout_7> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterOutput_Length/regout_6> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterOutput_Length/regout_9> is incomplete. The signal does not drive any load pins in the design. The signal <U5/RegisterOutput_Length/regout_8> is incomplete. The signal does not drive any load pins in the design.