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LIBRARY IEEE;
USE IEEE.Std_Logic_1164.all;
USE IEEE.Std_Logic_arith.all;
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ENTITY Configurable_U4 IS
  PORT(
      A    : IN std_logic_vector(7 downto 0) :=(OTHERS => 'U');
      B    : IN std_logic_vector(7 downto 0) :=(OTHERS => 'U');
      LT   : OUT std_logic := '0'
  );
END Configurable_U4;
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ARCHITECTURE structure OF Configurable_U4 IS
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SIGNAL SA : std_logic_vector(7 downto 0);
SIGNAL SB : std_logic_vector(7 downto 0);
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BEGIN
    SA <= A;
    SB <= B;
    PROCESS(SA, SB)
    BEGIN
        IF (SA < SB) THEN
            LT <= '1';
        ELSE
            LT <= '0';
        END IF;
    END PROCESS;
END structure;
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