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LIBRARY IEEE;
USE IEEE.Std_Logic_1164.all;
USE IEEE.Std_Logic_Unsigned.all;
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ENTITY Configurable_U1 IS
  PORT(
      D    : IN std_logic_vector(7 downto 0) := (OTHERS => 'U');
      C    : IN std_logic  := 'U';
      PWM  : OUT std_logic := '0'
  );
END Configurable_U1;
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ARCHITECTURE structure OF Configurable_U1 IS
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CONSTANT cCounterMax : std_logic_vector(7 downto 0) := (OTHERS => '1');
CONSTANT cZeroPW : std_logic_vector(7 downto 0) := (OTHERS => '0');
SIGNAL I : std_logic_vector(7 downto 0) := (Others=> '0');
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BEGIN
    PROCESS(C)
    BEGIN
        IF C'Event and C = '1' THEN
            IF (I > D) OR (D = cZeroPW) THEN
                PWM <= '0';
            ELSE 
                PWM <= '1';
            END IF;

            IF I >= cCounterMax THEN
                I <= (OTHERS => '0');
            ELSE
                I <= I + 1;
            END IF;
        END IF;
    END PROCESS;
END structure;
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