]> Release 14.3 Trace (nt64)Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.C:\Xilinx\14.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -l 30 -u 30 fpga_projet.ncd C:\Users\Altium7\Documents\csaadVandamme\FPGA_projet\ProjectOutputs\Default - All Constraints\FPGA_projet_map.pcf fpga_projet.ncdfpga_projet.ncdFPGA_projet_map.pcfC:/Users/Altium7/Documents/csaadVandamme/FPGA_projet/ProjectOutputs/Default - All Constraints/FPGA_projet_map.pcfxc3s1500-4PRODUCTION 1.39 2012-10-12030INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.JTAG_NEXUS_TCKJTAG_NEXUS_TDI-0.1646.102JTAG_NEXUS_TMS-2.3465.690CLK_BRDJTAG_NEXUS_TCKCLK_BRDCLK_BRD43.573JTAG_NEXUS_TCK12.940JTAG_NEXUS_TCKJTAG_NEXUS_TCK8.5127.4264.097Wed May 17 18:19:33 2017 TraceTrace Settings Peak Memory Usage: 186 MB