From 0011d96bdb60df258d245e8d9aec90e881d94459 Mon Sep 17 00:00:00 2001 From: Justine Senellart Date: Tue, 2 May 2017 22:32:34 +0200 Subject: [PATCH] Pas grand chose ici pour le moment mis à part le tuto --- fpga/Sheet1.SchDoc | Bin 0 -> 134144 bytes fpga/TestcapteurLed.SchDoc | Bin 0 -> 161792 bytes fpga/fpga generic library guide.pdf | Bin 0 -> 2653745 bytes fpga/tutoFPGA.PrjFpg | 1187 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fpga/tutoFPGA.PrjFpgStructure | 7 +++++++ fpga/tutoriel_nanoboard.pdf | Bin 0 -> 2045162 bytes 6 files changed, 1194 insertions(+), 0 deletions(-) create mode 100644 fpga/Sheet1.SchDoc create mode 100644 fpga/TestcapteurLed.SchDoc create mode 100644 fpga/fpga generic library guide.pdf create mode 100644 fpga/tutoFPGA.PrjFpg create mode 100644 fpga/tutoFPGA.PrjFpgStructure create mode 100644 fpga/tutoriel_nanoboard.pdf diff --git a/fpga/Sheet1.SchDoc b/fpga/Sheet1.SchDoc new file mode 100644 index 0000000..1f5c2af Binary files /dev/null and b/fpga/Sheet1.SchDoc differ diff --git a/fpga/TestcapteurLed.SchDoc b/fpga/TestcapteurLed.SchDoc new file mode 100644 index 0000000..68a57b1 Binary files /dev/null and b/fpga/TestcapteurLed.SchDoc differ diff --git a/fpga/fpga generic library guide.pdf b/fpga/fpga generic library guide.pdf new file mode 100644 index 0000000..1a36c8b Binary files /dev/null and b/fpga/fpga generic library guide.pdf differ diff --git a/fpga/tutoFPGA.PrjFpg b/fpga/tutoFPGA.PrjFpg new file mode 100644 index 0000000..5acd0ad --- /dev/null +++ b/fpga/tutoFPGA.PrjFpg @@ -0,0 +1,1187 @@ +[Design] +Version=1.0 +HierarchyMode=0 +ChannelRoomNamingStyle=0 +ReleasesFolder= +ReleaseVaultGUID= +ReleaseVaultName= +ChannelDesignatorFormatString=$Component_$RoomName +ChannelRoomLevelSeperator=_ +OpenOutputs=1 +ArchiveProject=0 +TimestampOutput=0 +SeparateFolders=0 +TemplateLocationPath= +PinSwapBy_Netlabel=1 +PinSwapBy_Pin=1 +AllowPortNetNames=0 +AllowSheetEntryNetNames=1 +AppendSheetNumberToLocalNets=0 +NetlistSinglePinNets=0 +DefaultConfiguration=Default - All Constraints +UserID=0xFFFFFFFF +DefaultPcbProtel=1 +DefaultPcbPcad=0 +ReorderDocumentsOnCompile=1 +NameNetsHierarchically=1 +PowerPortNamesTakePriority=0 +PushECOToAnnotationFile=1 +DItemRevisionGUID= +ReportSuppressedErrorsInMessages=0 +FSMCodingStyle=eFMSDropDownList_OneProcess +FSMEncodingStyle=eFMSDropDownList_OneHot +OutputPath= +LogFolderPath= +ManagedProjectGUID= +VHDL87=0 +Verilog95=0 +IncludePaths= +Defines= + +[Preferences] +PrefsVaultGUID= +PrefsRevisionGUID= + +[Document1] +DocumentPath=Sheet1.SchDoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=0 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=DHYUEABC + +[Document2] +DocumentPath=NB2DSK01_08_DB30_06_BoardMapping.Constraint +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId= + +[Document3] +DocumentPath=NB2DSK01.08.Constraint +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All 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+PageOptions28=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType29=Text Print +OutputName29=Text Print +OutputDocumentPath29= +OutputVariantName29= +OutputDefault29=0 +PageOptions29=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + +[OutputGroup8] +Name=Validation Outputs +Description= +TargetPrinter=HP LaserJet 8000 Series PCL 5 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Component states check +OutputName1=Vault's components states check +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=Configuration compliance +OutputName2=Environment configuration compliance check +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=Design Rules Check +OutputName3=Design Rules Check +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType4=Differences Report +OutputName4=Differences Report +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 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+Description= +TargetPrinter=HP LaserJet 8000 Series PCL 5 +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=AutoCAD dwg/dxf PCB +OutputName1=AutoCAD dwg/dxf File PCB +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=AutoCAD dwg/dxf Schematic +OutputName2=AutoCAD dwg/dxf File Schematic +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=ExportIDF +OutputName3=Export IDF +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=ExportSTEP +OutputName4=Export STEP +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +OutputType5=NetList Sch +OutputName5=NetList Sch +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 + +[Modification Levels] +Type1=1 +Type2=1 +Type3=1 +Type4=1 +Type5=1 +Type6=1 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=1 +Type12=1 +Type13=1 +Type14=1 +Type15=1 +Type16=1 +Type17=1 +Type18=1 +Type19=1 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+Type38=1 +Type39=1 +Type40=1 +Type41=1 +Type42=1 +Type43=1 +Type44=1 +Type45=1 + +[Electrical Rules Check] +Type1=1 +Type2=1 +Type3=3 +Type4=1 +Type5=3 +Type6=3 +Type7=1 +Type8=1 +Type9=1 +Type10=1 +Type11=2 +Type12=2 +Type13=2 +Type14=0 +Type15=0 +Type16=0 +Type17=0 +Type18=0 +Type19=0 +Type20=1 +Type21=1 +Type22=1 +Type23=1 +Type24=1 +Type25=2 +Type26=2 +Type27=2 +Type28=1 +Type29=1 +Type30=1 +Type31=3 +Type32=3 +Type33=3 +Type34=2 +Type35=1 +Type36=2 +Type37=1 +Type38=2 +Type39=2 +Type40=2 +Type41=0 +Type42=2 +Type43=1 +Type44=1 +Type45=2 +Type46=1 +Type47=2 +Type48=2 +Type49=1 +Type50=2 +Type51=1 +Type52=1 +Type53=1 +Type54=1 +Type55=1 +Type56=2 +Type57=1 +Type58=1 +Type59=2 +Type60=0 +Type61=3 +Type62=2 +Type63=3 +Type64=0 +Type65=3 +Type66=3 +Type67=2 +Type68=2 +Type69=2 +Type70=2 +Type71=2 +Type72=2 +Type73=2 +Type74=1 +Type75=2 +Type76=1 +Type77=1 +Type78=1 +Type79=1 +Type80=2 +Type81=3 +Type82=3 +Type83=3 +Type84=3 +Type85=3 +Type86=2 +Type87=2 +Type88=2 +Type89=1 +Type90=1 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+NetClassAutoNamedHarnessEnabled=0 +NetClassManualEnabled=1 +NetClassSeparateForBusSections=0 + +[LibraryUpdateOptions] +SelectedOnly=0 +UpdateVariants=1 +PartTypes=0 +FullReplace=1 +UpdateDesignatorLock=1 +UpdatePartIDLock=1 +PreserveParameterLocations=1 +PreserveParameterVisibility=1 +DoGraphics=1 +DoParameters=1 +DoModels=1 +AddParameters=0 +RemoveParameters=0 +AddModels=1 +RemoveModels=1 +UpdateCurrentModels=1 + +[DatabaseUpdateOptions] +SelectedOnly=0 +UpdateVariants=1 +PartTypes=0 + +[Comparison Options] +ComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 +ComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|Confirm=0|UseName=0|InclAllRules=0 +ComparisonOptions5=Kind=Code Memory|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 + +[SmartPDF] +PageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + diff --git a/fpga/tutoFPGA.PrjFpgStructure b/fpga/tutoFPGA.PrjFpgStructure new file mode 100644 index 0000000..12ec490 --- /dev/null +++ b/fpga/tutoFPGA.PrjFpgStructure @@ -0,0 +1,7 @@ +Record=TopLevelDocument|FileName=Sheet1.SchDoc +Record=NEXUS_CORE|ComponentDesignator=U1|BaseComponentDesignator=U1|DocumentName=Sheet1.SchDoc|LibraryReference=DIGITAL_IO|NexusDeviceId=DIGITAL_IO|SubProjectPath= |NEXUS_JTAG_INDEX=0|ComponentUniqueID=NJFYOXVU|Description=Configurable Digital IO|Comment=DIGITAL_IO|Component Kind=Standard|ComponentLink1Description=Core &Resource Usage|ComponentLink1URL=CR0134 FPGA Instrument Resource Usage.pdf|ConfigurationParameters={}Version[2.0]{}StorageType[3]{}InterfaceType[Parallel]{}SchCompWidth[140]{}NoInputs[ ]{}Output0Name[AOUT{1}3..0{2}]{}Output0Width[4]{}Output0InitValue[0]{}Output0Kind[Numeric]{}Output0NumRadix[Binary]{}Designator[U1]{}InternalID[0]{}|ConfiguratorName=DIGITAL_IO|Core Revision=1.00.00|Footprint= |HelpURL=https://wiki.altium.com/display/ADOH/Digital+IO+Module|Ibis Model= |LastRevisionNo=1.00.00|Library Name=FPGA Instruments.IntLib|Library Reference=DIGITAL_IO|NEXUS_CORE=Instrument|NEXUS_JTAG_DEVICE=True|NEXUS_JTAG_ORDER=0|PCB3D= |Published=28-Jun-2007|Publisher=Altium Limited|Signal Integrity= |Simulation= |UseInDSF=True +Record=NEXUS_CORE|ComponentDesignator=U5|BaseComponentDesignator=U5|DocumentName=Sheet1.SchDoc|LibraryReference=CLKGEN|NexusDeviceId=CLKGEN|SubProjectPath= |NEXUS_JTAG_INDEX=1|ComponentUniqueID=OGOATRHV|Description=Frequency Generator|Comment=CLKGEN|Component Kind=Standard|ComponentLink1Description=Core &Resource Usage|ComponentLink1URL=CR0134 FPGA Instrument Resource Usage.pdf#page=2|Core Revision=1.00.00|Footprint= |HelpURL=https://wiki.altium.com/display/ADOH/Frequency+Generator+Module|Ibis Model= |LastRevisionNo=1.00.00|Library Name=FPGA Instruments.IntLib|Library Reference=CLKGEN|NEXUS_CORE=Instrument|NEXUS_JTAG_DEVICE=True|NEXUS_JTAG_ORDER=0|PCB3D= |Published=3-Nov-2004|Publisher=Altium Limited|Signal Integrity= |Simulation= +Record=NEXUS_CORE_COMPONENT|BaseComponentDesignator=U1|DocumentName=Sheet1.SchDoc|LibraryReference=DIGITAL_IO|SubProjectPath= |Configuration= |Description=Configurable Digital IO|NexusDeviceId=DIGITAL_IO|SubPartUniqueId1=NJFYOXVU|SubPartDocPath1=Sheet1.SchDoc|Comment=DIGITAL_IO|Component Kind=Standard|ComponentLink1Description=Core &Resource Usage|ComponentLink1URL=CR0134 FPGA Instrument Resource Usage.pdf|ConfigurationParameters={}Version[2.0]{}StorageType[3]{}InterfaceType[Parallel]{}SchCompWidth[140]{}NoInputs[ ]{}Output0Name[AOUT{1}3..0{2}]{}Output0Width[4]{}Output0InitValue[0]{}Output0Kind[Numeric]{}Output0NumRadix[Binary]{}Designator[U1]{}InternalID[0]{}|ConfiguratorName=DIGITAL_IO|Core Revision=1.00.00|Footprint= |HelpURL=https://wiki.altium.com/display/ADOH/Digital+IO+Module|Ibis Model= |LastRevisionNo=1.00.00|Library Name=FPGA Instruments.IntLib|Library Reference=DIGITAL_IO|NEXUS_CORE=Instrument|NEXUS_JTAG_DEVICE=True|NEXUS_JTAG_ORDER=0|PCB3D= |Published=28-Jun-2007|Publisher=Altium Limited|Signal Integrity= |Simulation= |UseInDSF=True +Record=NEXUS_CORE_COMPONENT|BaseComponentDesignator=U5|DocumentName=Sheet1.SchDoc|LibraryReference=CLKGEN|SubProjectPath= |Configuration= |Description=Frequency Generator|NexusDeviceId=CLKGEN|SubPartUniqueId1=OGOATRHV|SubPartDocPath1=Sheet1.SchDoc|Comment=CLKGEN|Component Kind=Standard|ComponentLink1Description=Core &Resource Usage|ComponentLink1URL=CR0134 FPGA Instrument Resource Usage.pdf#page=2|Core Revision=1.00.00|Footprint= |HelpURL=https://wiki.altium.com/display/ADOH/Frequency+Generator+Module|Ibis Model= |LastRevisionNo=1.00.00|Library Name=FPGA Instruments.IntLib|Library Reference=CLKGEN|NEXUS_CORE=Instrument|NEXUS_JTAG_DEVICE=True|NEXUS_JTAG_ORDER=0|PCB3D= |Published=3-Nov-2004|Publisher=Altium Limited|Signal Integrity= |Simulation= +Record=Configuration|Name=Default - All Constraints|DeviceName=XC3S1500-4FG676C +Record=Configuration|Name=NB2DSK01_08_DB30_06|DeviceName=XC3S1500-4FG676C diff --git a/fpga/tutoriel_nanoboard.pdf b/fpga/tutoriel_nanoboard.pdf new file mode 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