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fpga/FPGA_projet/ProjectOutputs/Default - All Constraints/fpga_projet_summary.xml 409 Bytes
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  <?xml version="1.0" encoding="UTF-8"?>
  <!-- IMPORTANT: This is an internal file that has been generated
       by the Xilinx ISE software.  Any direct editing or
       changes made to this file may result in unpredictable
       behavior or data corruption.  It is strongly advised that
       users do not edit the contents of this file. -->

  <DesignSummary rev="12">

  <CmdHistory>
  </CmdHistory>

  </DesignSummary>