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fpga/FPGA_projet/ProjectOutputs/Default - All Constraints/fpga_projet_map.pcf 712 Bytes
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  //! **************************************************************************

  // Written by: Map P.40xd on Wed May 17 18:19:13 2017

  //! **************************************************************************

  

  SCHEMATIC START;

  COMP "HA2" LOCATE = SITE "AE4" LEVEL 1;

  COMP "HA8" LOCATE = SITE "AB3" LEVEL 1;

  COMP "JTAG_NEXUS_TDI" LOCATE = SITE "R21" LEVEL 1;

  COMP "JTAG_NEXUS_TCK" LOCATE = SITE "P21" LEVEL 1;

  PIN JTAG_NEXUS_TCK_pin<0> = BEL "JTAG_NEXUS_TCK" PINNAME PAD;

  PIN "JTAG_NEXUS_TCK_pin<0>" CLOCK_DEDICATED_ROUTE = FALSE;

  COMP "JTAG_NEXUS_TDO" LOCATE = SITE "B23" LEVEL 1;

  COMP "JTAG_NEXUS_TMS" LOCATE = SITE "P19" LEVEL 1;

  COMP "CLK_BRD" LOCATE = SITE "AE14" LEVEL 1;

  SCHEMATIC END;